JP7120520B2 - Humidity detector and temperature detector - Google Patents

Description

The present invention relates to a humidity detection device and a temperature detection device.

Humidity detectors include those of a capacitance type that use, as a dielectric, a moisture-sensitive film formed of a polymeric material whose dielectric constant changes according to the amount of moisture absorbed. In this capacitance type humidity detector, a humidity sensitive film is arranged between electrodes, and humidity (relative humidity) is obtained by measuring the capacitance between the electrodes.

Such a humidity detection device is packaged by, for example, sealing a sensor chip having a humidity detection section with a resin as a sealing member. Since the humidity detector needs to be in contact with the outside air as a detection target, the sealing member is formed with an opening for exposing the humidity detector (see Patent Document 1, for example).

Also known is a sensor chip provided with a temperature detection section for detecting the temperature of outside air in addition to the humidity detection section.

JP 2018-59716 A

When the sensor chip is provided with the temperature detection section in addition to the humidity detection section, both the humidity detection section and the temperature detection section need to be arranged in the opening so as to be exposed from the sealing member.

However, when a bandgap temperature sensor that utilizes the bandgap characteristics of a semiconductor is used as the temperature detection unit, the photoelectric effect occurs when light enters the temperature detection unit, causing the characteristics to fluctuate and the temperature to rise. detection accuracy may be degraded.

For this reason, it is conceivable to form a light-shielding film using a wiring layer on the light incident side of the temperature detection unit. It is necessary to form a slit (gap) in the Light may enter through this slit and enter the temperature detection section.

SUMMARY OF THE INVENTION An object of the present invention is to improve the light shielding property of a temperature detection unit.

The disclosed technology is a humidity detection device that includes a sensor chip having a humidity detection section and a temperature detection section, and a sealing member that seals the sensor chip with the humidity detection section and the temperature detection section exposed. The sensor chip includes a semiconductor substrate on which the temperature detecting portion is formed, a plurality of wiring layers formed on the semiconductor substrate, at least one wiring layer among the plurality of wiring layers, and the semiconductor substrate. one or more interlayer connection layers connecting between the plurality of wiring layers; a first light shielding wall formed by the substrate connection layer and surrounding the temperature detection section; A second light shielding wall formed of a connection layer and surrounding the temperature detection section, and a wiring layer formed of a wiring layer above the second light shielding wall among the plurality of wiring layers and configured to cover the temperature detection section. and a covering light shielding film.

ADVANTAGE OF THE INVENTION According to this invention, the light-shielding property of a temperature detection part can be improved.

It is a figure which illustrates schematic structure of the humidity detection apparatus which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA in FIG. 1; FIG. 3 is a plan view of the humidity detection device with the mold resin removed; It is a schematic plan view showing the configuration of a sensor chip. 1 is a circuit diagram illustrating the configuration of an ESD protection circuit; FIG. FIG. 3 is a diagram illustrating a layer structure of an NMOS transistor that constitutes an ESD protection circuit; 4 is a circuit diagram illustrating the configuration of a humidity detection unit; FIG. 4 is a circuit diagram illustrating the configuration of a temperature detection unit; FIG. It is a schematic sectional view for explaining the element structure of the sensor chip. FIG. 4 is a plan view illustrating shapes of a lower electrode and an upper electrode; FIG. 4 is a plan view illustrating the shape of an n-type diffusion layer that constitutes the heating unit; 3 is a block diagram illustrating the functional configuration of an ASIC chip; FIG. FIG. 4 is a plan view illustrating the pattern of the first plug layer; FIG. 14 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 13; 4 is a plan view illustrating patterns of the first wiring layer; FIG. FIG. 16 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 15; FIG. 4 is a plan view illustrating a pattern of a second plug layer; FIG. 18 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 17; It is a top view which illustrates the pattern of a 2nd wiring layer. FIG. 20 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 19; It is a figure which shows the example which used the resistance type temperature sensor as the temperature detection part.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description may be omitted. In addition, in the present disclosure, humidity when simply described as humidity means relative humidity.

[Outline configuration]
A configuration of the humidity detection device 10 according to one embodiment of the present invention will be described.

FIG. 1 is a diagram illustrating a schematic configuration of a humidity detection device 10 according to one embodiment of the invention. FIG. 1A is a top plan view of the humidity detection device 10. FIG. FIG. 1B is a bottom view of the humidity detection device 10 viewed from below. FIG. 1(C) is a side view of the humidity detection device 10 viewed from the lateral direction. FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA in FIG. 1(A).

The humidity detection device 10 has a substantially rectangular planar shape, and one of two pairs of opposing sides is parallel to the X direction and the other is parallel to the Y direction. The X direction and the Y direction are orthogonal to each other. Also, the humidity detection device 10 has a thickness in the Z direction perpendicular to the X and Y directions. The planar shape of the humidity detection device 10 is not limited to a rectangular shape, and may be circular, elliptical, polygonal, or the like.

The humidity detection device 10 includes a sensor chip 20 as a first semiconductor chip, an ASIC (Application Specific Integrated Circuit) chip 30 as a second semiconductor chip, a mold resin 40 as a sealing member, and a plurality of lead terminals 41. have

The sensor chip 20 is laminated on the ASIC chip 30 via a first DAF (Die Attach Film) 42 . That is, the sensor chip 20 and the ASIC chip 30 have a stack structure.

The sensor chip 20 and the ASIC chip 30 are electrically connected by a plurality of first bonding wires 43 . The ASIC chip 30 and the plurality of lead terminals 41 are electrically connected by a plurality of second bonding wires 44 .

The sensor chip 20 and the ASIC chip 30, the plurality of first bonding wires 43, the plurality of second bonding wires 44, and the plurality of lead terminals 41 laminated in this way are sealed with the mold resin 40 and packaged. ing. This package method is called a PLP (Plating Lead Package) method.

On the bottom surface of the ASIC chip 30, the second DAF 45 used for packaging by the PLP method remains, although the details will be described later. The second DAF 45 has a role of insulating the bottom surface of the ASIC chip 30 . A second DAF 45 and a plurality of lead terminals 41 are exposed on the lower surface of the humidity detection device 10 .

Each lead terminal 41 is made of nickel or copper. The first DAF 42 and the second DAF 45 are each made of an insulating material such as a mixture of resin and silica. The molding resin 40 is a black resin having a light shielding property such as an epoxy resin containing a mixture of carbon black, silica, or the like.

An opening 50 is formed on the upper surface side of the humidity detection device 10 to expose a part of the sensor chip 20 from the mold resin 40 . The opening 50 has, for example, a tapered wall, and the opening area becomes smaller downward. The lowermost portion of the opening 50 that actually exposes the sensor chip 20 is called an effective opening 51 .

When forming the opening 50 , the mold is pressed against the sensor chip 20 and sealed with the molding resin 40 . The pressing force exerted by the mold on the sensor chip 20 and the ASIC chip 30 at this time may cause damage such as chip cracking. In order to prevent this breakage, the thickness T1 of the sensor chip 20 and the thickness T2 of the ASIC chip 30 are each preferably 200 μm or more, for example.

FIG. 3 is a plan view of the humidity detection device 10 with the mold resin 40 removed. As shown in FIG. 3, the sensor chip 20 and the ASIC chip 30 each have a substantially rectangular planar shape and have two sides parallel to the X direction and two sides parallel to the Y direction. The sensor chip 20 is smaller than the ASIC chip 30 and is stacked on the surface of the ASIC chip 30 with the first DAF 42 interposed therebetween.

The sensor chip 20 is provided with a humidity detection section 21 , a temperature detection section 22 and a heating section 23 in a region exposed by the effective opening 51 . The heating portion 23 is formed on the lower surface side of the humidity detection portion 21 so as to cover the formation area of the humidity detection portion 21 . That is, the area of the heating section 23 is larger than that of the humidity detection section 21 . In this manner, the mold resin 40 as a sealing member seals the sensor chip 20 and the like while exposing the humidity detection section 21 and the temperature detection section 22 .

A plurality of bonding pads (hereinafter simply referred to as pads) 24 are formed at the end of the sensor chip 20 . Six pads 24 are formed in this embodiment. The pads 24 are made of, for example, aluminum or an aluminum silicon alloy (AlSi).

The ASIC chip 30 is a semiconductor chip for signal processing and control, and includes a humidity measurement processing unit 31, a temperature measurement processing unit 32, a heating control unit 33, and a failure determination unit 34 (see FIG. 12 for all), which will be described later. It is

A plurality of first pads 35 and a plurality of second pads 36 are provided in a region of the surface of the ASIC chip 30 that is not covered with the sensor chip 20 . The first pads 35 and the second pads 36 are made of, for example, aluminum or an aluminum silicon alloy (AlSi).

The first pads 35 are connected to corresponding pads 24 of the sensor chip 20 via first bonding wires 43 . The second pads 36 are connected to corresponding lead terminals 41 via second bonding wires 44 . The lead terminals 41 are arranged around the ASIC chip 30 . During manufacturing, the mounting position of the ASIC chip 30 is determined with the lead terminal 41 as a reference. The mounting position of the sensor chip 20 on the ASIC chip 30 is determined based on either the position of the ASIC chip 30 or the lead terminals 41 . The opening 50 is formed by a transfer molding method or the like using a mold, and the position of this mold is determined with the lead terminal 41 as a reference.

Reference numeral 25 shown in FIG. 3 represents a formation allowable region for the humidity detection section 21 and the temperature detection section 22 on the sensor chip 20 . The formation allowable region 25 is formed in the opening 50 so as to be reliably exposed from the opening 50 even when the largest misalignment occurs between the ASIC chip 30, the sensor chip 20, and the mold during mounting. It is set within the formation area of 50. If the humidity detector 21 and the temperature detector 22 are formed within the formation permissible region 25, they are reliably exposed from the opening 50 regardless of the positional deviation.

[Configuration of sensor chip]
Next, the configuration of the sensor chip 20 will be described.

FIG. 4 is a schematic plan view showing the configuration of the sensor chip 20. As shown in FIG. The aforementioned pad 24 is a terminal used for external voltage application and potential detection. In FIG. 4, the plurality of pads 24 shown in FIG. 3 are shown separately from the pads 24a-24f. The pads 24a to 24f are simply referred to as pads 24 when there is no need to distinguish between them.

The pad 24a functions as a ground electrode terminal (GND) grounded to ground potential. The pad 24a is electrically connected to each part such as the temperature detection part 22 and the heating part 23 through wiring and a substrate.

Pad 24 b is a lower electrode terminal (BOT) electrically connected to lower electrode 83 of humidity detector 21 . Pad 24b is used to supply drive voltage to lower electrode 83 . The pad 24 c is a humidity detection terminal (HMD) electrically connected to the upper electrode 84 of the humidity detection section 21 . The pad 24c is used to acquire a relative humidity detection signal from the upper electrode 84. FIG. The pad 24 d is a reference electrode terminal (REF) electrically connected to the reference electrode 82 of the humidity detection section 21 . Pad 24d is used to acquire a reference signal for humidity detection from reference electrode 82 .

The pad 24 e is a temperature detection terminal (TMP) electrically connected to the temperature detection section 22 . The pad 24e is used to acquire a temperature detection signal. The pad 24 f is a heating terminal (HT) electrically connected to the heating section 23 . Pad 24f is used to supply a drive voltage for driving heating unit 23 .

An electrostatic discharge (ESD) protection circuit 60 is connected to each of the pads 24b to 24f other than the pad 24a. Each ESD protection circuit 60 is connected between each of the pads 24b to 24f as input terminals or output terminals and the pad 24a as a ground electrode terminal. In this embodiment, the ESD protection circuit 60 is composed of one diode 61 . The diode 61 has an anode connected to the pad 24a and a cathode connected to one of the pads 24b to 24f.

The ESD protection circuit 60 is preferably arranged near the pads 24b-24f so as to be as far away from the effective opening 51 as possible. Since the ESD protection circuit 60 is covered with the mold resin 40, unnecessary charge generation due to the photoelectric effect does not occur.

[Configuration of ESD protection circuit]
Next, the configuration of the ESD protection circuit 60 will be described.

FIG. 5 is a circuit diagram illustrating the configuration of the ESD protection circuit 60. As shown in FIG. As shown in FIG. 5, the diode 61 forming the ESD protection circuit 60 is formed of, for example, an N-channel MOS (Metal-Oxide-Semiconductor) transistor (hereinafter referred to as an NMOS transistor). Specifically, the diode 61 is formed by short-circuiting the source, gate, and back gate of an NMOS transistor (so-called diode connection). This short circuit functions as an anode. The drain of this NMOS transistor functions as the cathode.

FIG. 6 is a diagram illustrating the layer structure of the NMOS transistor that constitutes the ESD protection circuit 60. As shown in FIG. This NMOS transistor has two n-type diffusion layers 71 and 72 formed on the surface layer of a p-type semiconductor substrate 70 for constituting the sensor chip 20 , a contact layer 73 and a gate electrode 74 . A gate electrode 74 is formed on the surface of the p-type semiconductor substrate 70 with a gate insulating film 75 interposed therebetween. A gate electrode 74 is arranged between the two n-type diffusion layers 71 and 72 .

For example, the n-type diffusion layer 71 functions as a source and the n-type diffusion layer 72 functions as a drain. Contact layer 73 is a low-resistance layer (p-type diffusion layer) for electrical connection with p-type semiconductor substrate 70 as a back gate. The n-type diffusion layer 71, the gate electrode 74 and the contact layer 73 are commonly connected and short-circuited. This short-circuit portion functions as an anode, and the n-type diffusion layer 72 functions as a cathode.

The p-type semiconductor substrate 70 is, for example, a p-type silicon substrate. The gate electrode 74 is made of metal or polycrystalline silicon (polysilicon). The gate insulating film 75 is made of, for example, an oxide film such as silicon dioxide.

[Configuration of Humidity Detector]
Next, the configuration of the humidity detector 21 will be described.

FIG. 7 is a circuit diagram illustrating the configuration of the humidity detection section 21. As shown in FIG. As shown in FIG. 7 , the humidity detection section 21 has a humidity detection capacitor 80 and a reference capacitor 81 .

One electrode (lower electrode 83) of the humidity detector 21 is connected to a pad 24b as a lower electrode terminal. The other electrode (upper electrode 84) of the humidity detection section 21 is connected to a pad 24c as a terminal for humidity detection. One electrode of the reference capacitor 81 is shared with one electrode (lower electrode 83 ) of the humidity detection section 21 . The other electrode (reference electrode 82) of the reference capacitor 81 is connected to the pad 24d as a reference electrode terminal.

The humidity detection capacitor 80 is provided with a humidity sensitive film 86, which will be described later, between electrodes. The humidity sensitive film 86 is made of a polymeric material such as polyimide that absorbs moisture in the air and changes its dielectric constant according to the amount of moisture absorbed. Therefore, the capacitance of the humidity detection capacitor 80 changes according to the amount of moisture absorbed by the humidity sensitive film 86 .

The reference capacitor 81 is provided with a second insulating film 111 (see FIG. 9), which will be described later, between electrodes. The second insulating film 111 is made of an insulating material such as silicon dioxide (SiO ₂ ) that does not absorb moisture. Therefore, the capacitance of the reference capacitor 81 does not change, or changes very little.

Since the amount of moisture contained in the humidity sensitive film 86 corresponds to the humidity around the humidity detection device 10, by detecting the difference between the capacitance of the humidity detection capacitor 80 and the capacitance of the reference capacitor 81, , relative humidity can be measured. This measurement of relative humidity is performed by the humidity measurement processor 31 (see FIG. 12) in the ASIC chip 30 based on the potential of the pad 24c as the humidity detection terminal and the potential of the pad 24d as the reference electrode terminal. .

[Configuration of Temperature Detector]
Next, the configuration of the temperature detection section 22 will be described.

FIG. 8 is a circuit diagram illustrating the configuration of the temperature detection section 22. As shown in FIG. The temperature detection unit 22 is a bandgap type temperature sensor that detects temperature by utilizing the characteristic that the electrical characteristics of the semiconductor bandgap change proportionally with changes in temperature. For example, the temperature detection unit 22 includes one or a plurality of bipolar transistors having two terminals by connecting any two of a base, an emitter, and a collector. The temperature can be measured by detecting the resistance value between the two terminals.

As shown in FIG. 8, in this embodiment, the temperature detection unit 22 is configured by connecting in parallel a plurality (e.g., eight) of npn-type bipolar transistors 90 whose bases and collectors are connected. By connecting a plurality of bipolar transistors 90 in parallel in this way, the junction area of the pn junction is increased and the ESD resistance is improved.

The emitter of bipolar transistor 90 is connected to pad 24a as a ground electrode terminal. The base and collector of the bipolar transistor 90 are connected to the pad 24e as a terminal for temperature detection.

The temperature is measured by the temperature measurement processor 32 (see FIG. 12) in the ASIC chip 30 based on the potential of the pad 24e.

[Sensor chip element structure]
Next, the element structure of the sensor chip 20 will be described.

FIG. 9 is a schematic cross-sectional view for explaining the element structure of the sensor chip 20. As shown in FIG. In FIG. 9, the pads 24a, 24b, 24c, and 24e are shown in the same cross section as the humidity detection section 21, the temperature detection section 22, and the heating section 23, which facilitates understanding of the structure. It does not mean that they actually exist within the same cross section. The cross sections of the humidity detection unit 21, the temperature detection unit 22, and the heating unit 23 are also simplified in order to facilitate understanding of the structure, and the positional relationship and the like of each unit are different from the actual ones.

As shown in FIG. 9, the sensor chip 20 is formed using the p-type semiconductor substrate 70 described above. This p-type semiconductor substrate 70 is formed with a first deep n-well 100a and a second deep n-well 100b. A temperature detector 22 is formed in the first deep n-well 100a. A heating portion 23 is formed in the second deep n-well 100b.

P-wells 103a and 103b are formed in the surface layer of the p-type semiconductor substrate 70 where neither the first deep n-well 100a nor the second deep n-well 100b are formed. Contact layers 104a and 104b made of p-type diffusion regions are formed on the surface layers of the p-wells 103a and 103b, respectively. The contact layers 104a and 104b are low-resistance layers (p-type diffusion layers) for electrical connection between a predetermined wiring layer formed on the p-type semiconductor substrate 70 and the p-type semiconductor substrate 70. FIG.

A p-well 101 and an n-well 102 are formed on the surface of the first deep n-well 100a. An n-type diffusion layer 91 and a p-type diffusion layer 92 are formed in the surface layer of the p-well 101 . An n-type diffusion layer 93 is formed in the surface layer of the n-well 102 . The n-type diffusion layer 91, the p-type diffusion layer 92, and the n-type diffusion layer 93 constitute the aforementioned npn-type bipolar transistor 90, functioning as an emitter, a base, and a collector, respectively.

A p-well 105 is formed on the surface of the second deep n-well 100b. One or more n-type diffusion layers 106 are formed in the surface layer of the p-well 105 . In this embodiment, a plurality of n-type diffusion layers 106 are formed. For example, each n-type diffusion layer 106 extends in a direction orthogonal to the plane of the drawing, and forms a one-dimensional lattice as a whole (see FIG. 11). The n-type diffusion layer 106 has a predetermined resistance value (for example, a sheet resistance value of about 3Ω) and functions as a resistor that generates heat when current flows. That is, the n-type diffusion layer 106 constitutes the heating portion 23 described above.

Each layer in the p-type semiconductor substrate 70 is formed using a normal semiconductor manufacturing process (CMOS process). Therefore, n-type diffusion layer 106 as a resistor is formed in the same manufacturing process as n-type diffusion layers 91 and 93 included in part of temperature detection section 22 . The n-type diffusion layers 106, 91 and 93 are simultaneously formed by an ion implantation process of doping the substrate with an n-type impurity (for example, phosphorus) by ion implantation. That is, the n-type diffusion layer 106 as a resistor has the same depth from the surface of the p-type semiconductor substrate 70 as the n-type diffusion layers 91 and 93 included in a part of the temperature detection section 22 . Further, the n-type diffusion layer 106 may have the same depth from the surface of the p-type semiconductor substrate 70 as the p-type diffusion layer 92 included in a part of the temperature detection section 22 .

The n-type diffusion layers 106, 91 and 93 can be formed by a thermal diffusion process in which impurities are added by heat treatment instead of the ion implantation process.

Also, the n-type diffusion layers 71 and 72 of the ESD protection circuit 60 described above are formed by the same manufacturing process (ion implantation process or thermal diffusion process) as the n-type diffusion layers 106, 91 and 93. The contact layer 73 is formed in the same manufacturing process (ion implantation process or thermal diffusion process) as the p-type diffusion layer 92, the contact layers 104a and 104b, and the like.

Other layers in the p-type semiconductor substrate 70 mainly function as contact layers, so description thereof is omitted.

A first insulating film 110 , a second insulating film 111 and a third insulating film 112 are laminated in this order on the surface of the p-type semiconductor substrate 70 . These are made of an insulating material such as silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

A first wiring layer 120 is formed on the first insulating film 110 . A second wiring layer 121 is formed on the second insulating film 111 . The second insulating film 111 covers the first wiring layer 120 . The third insulating film 112 covers the second wiring layer 121 . The first wiring layer 120 and the second wiring layer 121 are made of a conductive material such as aluminum (Al). As the conductive material of the first wiring layer 120 and the second wiring layer 121, it is possible to use AlSi, AlSiCu, Au/Ni, Cr, or the like.

A first plug layer 122 having a plurality of first plugs for connecting the first wiring layer 120 to the p-type semiconductor substrate 70 is formed in the first insulating film 110 . The first plug layer 122 is also called a substrate connection layer. A second plug layer 123 having a plurality of second plugs for connecting the first wiring layer 120 and the second wiring layer 121 is formed in the second insulating film 111 . The second plug layer 123 is also called an interlayer connection layer. The first plug layer 122 and the second plug layer 123 are made of a conductive material such as tungsten (W).

For example, the wiring 94 for connecting the base and collector of the bipolar transistor 90 described above is formed by the first wiring layer 120 and is connected to the p-type diffusion layer 92 and the n-type diffusion layer 93 via the first plug layer 122. Connected. Also, the wiring 94 is connected to the pad 24e as a terminal for temperature detection through the second plug layer 123 and the second wiring layer 121. As shown in FIG. Also, the n-type diffusion layer 91 as the emitter of the bipolar transistor 90 is connected through the first plug layer 122, the first wiring layer 120 and the second wiring layer 121 to the pad 24a as the ground electrode terminal.

A wiring 107 for grounding one end of the heating portion 23 to the ground potential is formed of the first wiring layer 120 and connected via the first plug layer 122 to the n-type diffusion layer 106 and the contact layer 104b. A wiring 108 for connecting the other end of the heating portion 23 to a pad 24f as a heating terminal is connected to the n-type diffusion layer 106 via the first plug layer 122, and is connected to the second plug layer 123 and It is connected to the pad 24 f through the second wiring layer 121 . Note that the wiring 108 is preferably wider than the other wirings in order to prevent electromigration due to a large current flowing through the heating portion 23 .

The reference electrode 82 of the reference capacitor 81 is formed of the first wiring layer 120 and is connected to the pad 24d (not shown in FIG. 9) as a reference electrode terminal through the second plug layer 123 and the second wiring layer 121. Connected.

A lower electrode 83 of the humidity detection capacitor 80 is formed of the second wiring layer 121 and electrically connected to the pad 24b as a lower electrode terminal. Actually, the lower electrode 83 is connected to a wiring (not shown) formed by the first wiring layer 120 via the second plug layer 123 . This wiring is connected to a wiring (not shown) formed by the second wiring layer 121 through the second plug layer 123, and is connected to the pad 24b.

Further, a wiring 85 for electrically connecting the upper electrode 84 of the humidity detection capacitor 80 to the pad 24c as a humidity detection terminal is formed of the second wiring layer 121. As shown in FIG. Actually, the wiring 85 is connected to a wiring (not shown) formed by the first wiring layer 120 via the second plug layer 123 . This wiring is connected to a wiring (not shown) formed by the second wiring layer 121 via the second plug layer 123, and is connected to the pad 24e.

Note that the lower electrode 83 is arranged at a position facing the reference electrode 82 with the second insulating film 111 interposed therebetween.

The pads 24a to 24f are formed on the third insulating film 112 with a conductive material such as aluminum, and are connected to the second wiring layer 121 through the third insulating film 112. FIG.

A humidity sensitive film 86 is formed on the third insulating film 112 . The humidity sensitive film 86 has a thickness of 0.5 μm to 1.5 μm and is made of a polymeric material that easily adsorbs and desorbs water molecules according to humidity. The moisture sensitive film 86 is, for example, a polyimide film with a thickness of 1 μm. The polymeric material forming the moisture-sensitive film 86 is not limited to polyimide, and may be cellulose, polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), or the like.

The upper surface of the humidity sensitive film 86 is flat, and a planar upper electrode 84 is formed on this upper surface. The upper electrode 84 is formed at a position facing the lower electrode 83 with the humidity sensitive film 86 interposed therebetween. A portion of the upper electrode 84 is connected to the wiring 85 . The upper electrode 84 is, for example, a conductive film made of aluminum or the like with a thickness of 200 nm. In addition, the upper electrode 84 is formed with a plurality of openings 84a so that water molecules in the air are efficiently taken into the humidity sensitive film 86. As shown in FIG.

An overcoat film 87 is provided on the humidity sensitive film 86 so as to cover the upper electrode 84 . The overcoat film 87 is made of a polymeric material, for example, the same material as the moisture sensitive film 86 . The thickness of the overcoat film 87 is, for example, 0.5 μm to 10 μm.

The humidity sensitive film 86 and the overcoat film 87 are formed with openings for exposing the pads 24a to 24f.

Thus, the lower electrode 83 and the upper electrode 84 constitute the parallel-plate humidity detection capacitor 80 . The lower electrode 83 and the reference electrode 82 constitute a parallel-plate reference capacitor 81 . The humidity detection capacitor 80 and the reference capacitor 81 are arranged above the heating section 23 .

Therefore, the heat generated by the heating portion 23 heats the humidity sensitive film 86 between the lower electrode 83 and the upper electrode 84 . As a result, the moisture-sensitive film 86 absorbs an amount of water molecules corresponding to the humidity when the temperature rises due to heating, so that the dielectric constant changes and the capacitance of the humidity detection capacitor 80 decreases. Also, the temperature detection unit 22 detects a temperature rise caused by the heating unit 23 .

FIG. 10 is a plan view illustrating shapes of the lower electrode 83 and the upper electrode 84. FIG. As shown in FIG. 10, both the lower electrode 83 and the upper electrode 84 are rectangular. The upper electrode 84 is formed so as to cover the lower electrode 83 .

The opening 84a is preferably as small as possible, and the smaller the opening, the more the electric field is prevented from leaking into the air. Actually, a large number of openings 84a are formed. In addition, the opening 84a is not limited to a square shape, and may be an elongated strip shape or a circular shape. Also, the openings 84a may be arranged in a zigzag pattern. The openings 84a are preferably circular and staggered.

Although not shown in FIG. 10, a rectangular reference electrode 82 is formed below the lower electrode 83 .

FIG. 11 is a plan view illustrating the shape of the n-type diffusion layer 106 forming the heating section 23. FIG. As shown in FIG. 11, the n-type diffusion layer 106 has a one-dimensional lattice shape in which a plurality of elongated strip-shaped regions are arranged in parallel. One end of the one-dimensional grid-like n-type diffusion layer 106 is connected to the wiring 107 described above, and the other end is connected to the wiring 108 described above. The heating unit 23 is positioned below the temperature detection unit 22 so as to cover the entire temperature detection unit 22 .

[Functional Configuration of ASIC Chip]
Next, functional units configured in the ASIC chip 30 will be described.

FIG. 12 is a block diagram illustrating the functional configuration of the ASIC chip 30. As shown in FIG. As shown in FIG. 12, the ASIC chip 30 includes a humidity measurement processing section 31, a temperature measurement processing section 32, a heating control section 33, and a failure determination section .

The humidity measurement processing unit 31 applies a predetermined drive voltage to the pad 24b as the lower electrode terminal, and detects the potential of the pad 24c as the humidity detection terminal and the potential of the pad 24d as the reference electrode terminal. Then, the humidity measurement processing unit 31 calculates the relative humidity (% RH) by performing signal processing based on the difference (potential difference) between the two detected values.

The temperature measurement processing unit 32 detects the potential of the pad 24e as a terminal for temperature detection, and calculates the temperature corresponding to the detected potential.

The heating control unit 33 applies a predetermined driving voltage to the pad 24f as a terminal for heating, thereby causing a current (for example, about 10 mA) to flow through the heating unit 23 to generate heat. The heating controller 33 controls the amount of heat generated by controlling the voltage applied to the pad 24f.

The failure determination section 34 performs failure determination based on the relative humidity measured by the humidity measurement processing section 31 and the temperature measured by the temperature measurement processing section 32 . The failure determination unit 34 provides the heating control unit 33 with instructions regarding the start and end of heating by the heating unit 23 at the time of failure determination. Specifically, the failure determination unit 34 determines failure when the temperature does not rise after the heating unit 23 generates heat, or when the temperature rises but the humidity does not decrease.

[Planar layout configuration of sensor chip]
Next, a more specific planar layout configuration of the sensor chip 20 will be described.

13 to 20 are diagrams showing the planar layout configuration and cross-sectional structure of the temperature detection section 22 of the sensor chip 20 and its peripheral formation region.

13 is a plan view illustrating the pattern of the first plug layer 122 formed on the p-type semiconductor substrate 70. FIG. 14 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 13. FIG.

As shown in FIG. 14, the p-type semiconductor substrate 70 is formed with an impurity diffusion layer, a well, a contact layer, etc. corresponding to the formation region of the temperature detection section 22 shown in FIG. Since these areas are the same as above, their description is omitted.

As shown in FIG. 13, the first plug layer 122 as a substrate connection layer includes a group of plugs 122a, light blocking walls 122b and 122c, and the like. The plug group 122a is formed by arranging a plurality of dot-like plugs. Each dot is, for example, a square with a side of 0.6 μm. The light shielding walls 122b and 122c are formed by linear plugs. The line width of the light shielding walls 122b and 122c is, for example, 0.6 μm.

The plug group 122a and the light shielding walls 122b and 122c are formed by forming openings (contact holes) of a predetermined pattern in the first insulating film 110 formed on the p-type semiconductor substrate 70, and filling the openings with a conductive material such as tungsten. It is formed by embedding.

FIG. 15 is a plan view illustrating the pattern of the first wiring layer 120 formed on the first plug layer 122. FIG. 16 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 15. FIG.

As shown in FIG. 15, the first wiring layer 120 includes wiring 94 electrically connected to the pad 24e as the temperature detection terminal, wiring 95 electrically connected to the pad 24c as the humidity detection terminal, It includes a wiring 96 electrically connected to the pad 24b as the lower electrode terminal, a conductive film 97 electrically connected to the pad 24a as the ground electrode terminal, and the like.

The wiring 94, the wiring 95, the wiring 96, and the conductive film 97 are connected to the pad 24e, the pad 24c, the pad 24b, and the pad 24a via wiring (not shown) formed by the second wiring layer 121, respectively. be.

The conductive film 97 has an opening 97a that exposes the temperature detection portion 22, and a wiring 97b for supplying a ground potential to the temperature detection portion 22 formed in the opening 97a.

The first wiring layer 120 is formed by depositing a conductive film such as aluminum on the first insulating film 110 and patterning this conductive film by photolithography and etching. Note that slits need to be formed between the wiring 94 and the conductive film 97, between the wiring 95 and the conductive film 97, and between the wiring 96 and the conductive film 97 for electrical isolation.

As shown in FIG. 16, the wiring 94 is connected to the p-type diffusion layer 92 and the n-type diffusion layer 93 in the p-type semiconductor substrate 70 via the plug group 122a. The conductive film 97 is connected to the contact layer 104a through the light blocking walls 122b and 122c. A wiring 97b formed integrally with the conductive film 97 is connected to the n-type diffusion layer 91 via the plug group 122a.

FIG. 17 is a plan view illustrating the pattern of the second plug layer 123 formed on the first wiring layer 120. FIG. 18 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 17. FIG.

As shown in FIG. 17, the second plug layer 123 as an interlayer connection layer includes plug groups 123a and 123b, light blocking walls 123c and 123d, and the like. The plug groups 123a and 123b are formed by arranging a plurality of dot-like plugs. Each dot is, for example, a square with a side of 0.6 μm. The light shielding walls 123c and 123d are formed by linear plugs. The line width of the light shielding walls 123c and 123d is, for example, 0.6 μm.

The plug groups 123a and 123b and the light shielding walls 123c and 123d are formed by forming openings (via holes) of a predetermined pattern in the second insulating film 111 formed on the first wiring layer 120, and filling the openings with a conductive material such as tungsten. is formed by embedding

FIG. 19 is a plan view illustrating the pattern of the second wiring layer 121 formed on the second plug layer 123. FIG. 20 is a cross-sectional view schematically showing a cross section taken along line BB in FIG. 19. FIG.

As shown in FIG. 19, the second wiring layer 121 includes the aforementioned lower electrode 83, wiring 85, light shielding film 88, and the like. The second wiring layer 121 is formed by depositing a conductive film such as aluminum on the second insulating film 111 and patterning this conductive film by photolithography and etching. Slits must be formed between the lower electrode 83 and the light shielding film 88 and between the wiring 85 and the light shielding film 88 for electrical isolation.

The lower electrode 83 is connected to the wiring 96 via the plug group 123a. The wiring 85 is connected to the wiring 95 via the plug group 123b. As shown in FIG. 20, the light shielding film 88 is connected to the conductive film 97 via the light shielding walls 123c and 123d.

The above-described second insulating film 111 is formed on the second wiring layer 121 , and the humidity sensitive film 86 is formed on the second insulating film 111 . An upper electrode 84 is formed on the moisture sensitive film 86 and connected to the wiring 85 . An overcoat film 87 is formed on the humidity sensitive film 86 so as to cover the upper electrode 84 .

[Light shielding structure of temperature detection part]
Next, the light shielding structure of the temperature detection section 22 will be described.

The light-shielding structure of the temperature detection unit 22 includes a light-shielding wall 122b (first light-shielding wall) formed by a first plug layer 122 as a substrate connection layer, a conductive film 97 formed by a first wiring layer 120, and an interlayer connection. A light shielding wall 123c (second light shielding wall) formed of the second plug layer 123 as a layer and a light shielding film 88 formed of the second wiring layer 121 are included.

Light shielding wall 122 b is formed on p-type semiconductor substrate 70 so as to surround temperature detection unit 22 . Specifically, the light shielding wall 122b surrounds the portion around the temperature detection unit 22 other than the wiring 94 as the signal line drawn out from the temperature detection unit 22 . Also, the upper end of the light shielding wall 122b is connected to the periphery of the opening 97a of the conductive film 97. As shown in FIG.

The light shielding wall 123 c is formed on the conductive film 97 so as to surround the temperature detection section 22 . Specifically, the light shielding wall 123c surrounds the portion around the temperature detection unit 22 other than the wiring 94 as the signal line drawn from the temperature detection unit 22 . The light shielding wall 123c is formed so as to be positioned outside the light shielding wall 122b. The light shielding wall 123c may be formed directly above the light shielding wall 122b.

The light shielding film 88 is connected to the upper end of the light shielding wall 123c and covers the temperature detecting section 22 from above.

In this manner, the temperature detection unit 22 is shielded from light by the light shielding walls 122b, 123c, and 123c.

[Light shielding structure of signal line]
Next, the light shielding structure of the signal line of the temperature detection section 22 will be described.

The light shielding structure of the wiring 94 is composed of the light shielding wall 122c and the light shielding wall 123d.

The light shielding walls 122c are arranged on the p-type semiconductor substrate 70 along both sides of the wiring 94 as the signal line. Also, the upper end of the light shielding wall 122 c is connected to the conductive film 97 .

The light shielding walls 123 d are arranged along both sides of the wiring 94 on the conductive film 97 . In addition, the light shielding wall 123d is formed so as to be positioned outside the light shielding wall 122c.

The light shielding film 88 is connected to the upper end of the light shielding wall 123d and covers the wiring 94 from above.

Therefore, the wiring 94 is shielded from light by the light shielding wall 122c and the light shielding wall 123d.

The wiring 94 is formed in a meandering shape outside the light shielding walls 123c and 122b for the purpose of adjusting the time constant of the signal by adding parasitic capacitance.

In addition, in FIGS. 13 and 17, the light shielding walls 122c and 123d are separated from the light shielding walls 122b and 123c, respectively, due to design rules. The light shielding wall 123d and the light shielding wall 123c may be connected.

Further, the signal line shielding structure may be formed for signal lines other than the wiring 94 .

[effect]
In the above-described embodiment, the temperature detection section 22 and the humidity detection section 21 are arranged so as to be exposed to the opening 50. Therefore, the light incident from the opening 50 passes through the translucent overcoat film 87 and the sensitive film. It permeates the wet film 86 . This transmitted light passes through the slit S1 between the light shielding film 88 and the lower electrode 83 and the slit S2 between the light shielding film 88 and the wiring 85 (see FIGS. 19 and 20 for both), and passes through the second wiring layer 121. may enter the Furthermore, the light incident under the second wiring layer 121 may enter under the first wiring layer 120 through the slit S3 (see FIGS. 15 and 20) between the conductive film 97 and the wiring 95 .

If light were incident on the temperature detection unit 22, a photoelectric effect would occur, generating unnecessary electric charges, which would change the electrical characteristics and possibly degrade the temperature detection accuracy.

In the above embodiment, as described above, a light shielding structure is provided for shielding the temperature detection section 22 by using the first plug layer 122, the first wiring layer 120, the second plug layer 123, and the second wiring layer 121. Therefore, it is possible to shield the light entering from the slits S1 to S3, etc., which are the entrance paths of the light, and prevent the occurrence of photoelectric conversion. As a result, the temperature detection accuracy of the temperature detection unit 22 is improved.

[Modification]
Various modifications of the above embodiment will be described below.

Although the sensor chip 20 is formed using the p-type semiconductor substrate 70 in the above embodiment, it can be formed using an n-type semiconductor substrate instead.

In the above-described embodiment, the wiring layers on the semiconductor substrate are two layers, that is, the first wiring layer 120 and the second wiring layer 121, but may be three or more layers. In this case, the light shielding film is formed by the uppermost wiring layer among the plurality of wiring layers. Further, in this case, the first light shielding wall is formed by the substrate connection layer that connects the lowest wiring layer among the plurality of wiring layers and the semiconductor substrate, and the plurality of interlayer connection layers that connect the plurality of wiring layers are formed. Each forms a second light shielding wall. When a plurality of second light shielding walls are present in this manner, it is preferable to form the second light shielding walls on the upper layer side so as to be located on the outer side. However, a plurality of second light shielding walls may be arranged at the same position on the XY plane.

Further, the light shielding film is not limited to the uppermost wiring layer, and may be formed of a wiring layer above the second light shielding wall. Further, the substrate connection layer is not limited to the lowest wiring layer, and may be connected to at least one wiring layer among a plurality of wiring layers.

In the above-described embodiment, the temperature detection unit 22 is composed of the npn-type bipolar transistor 90, but may be composed of a pnp-type bipolar transistor. Furthermore, the temperature detection section 22 may be configured with one or a plurality of pn junction diodes instead of the bipolar transistors.

Also, the temperature detection unit 22 may be a temperature sensor other than a bandgap type temperature sensor having a pn junction. For example, the temperature detection unit 22 may be a resistive temperature sensor that uses an impurity diffusion layer (n-type diffusion layer or p-type diffusion layer) as a resistor and detects temperature based on the temperature dependence of the resistance value. .

Moreover, the polycrystalline silicon (polysilicon) described above may be formed as n-type or p-type by a semiconductor process. For example, when the gate electrode 74 shown in FIG. 6 is made of polycrystalline silicon, by changing the impurity concentration and impurity species, it is possible to form the resistor in the same layer as the gate electrode 74 at the same time. Furthermore, the bridge circuit described below can be formed by a combination of polysilicon resistors and implant diffusion resistors.

FIG. 21 is a diagram showing an example in which the temperature detection unit is a resistance temperature sensor. A temperature detection unit 22a shown in FIG. 21 has a bridge circuit 200 in which a first resistor 201, a second resistor 202, a third resistor 203, and a fourth resistor 204 are connected to each other.

The first resistor 201 and the second resistor 202 are connected in series between the power supply potential (VDD) and the ground potential. Similarly, the third resistor 203 and the fourth resistor 204 are connected in series between the power supply potential and the ground potential.

The first to fourth resistors 201 to 204 are resistors made of an n-type diffusion layer or a p-type diffusion layer formed on the surface layer of the semiconductor substrate, or resistors made of polysilicon, and a combination of silicon impurity diffusion resistors. Therefore, as in the case where the temperature detection unit 22 is configured by a diode, the incident light may cause a photoelectric effect and deteriorate the temperature detection accuracy. Also in the resistive temperature sensor, it is preferable to block the light to prevent the occurrence of photoelectric conversion, as in the above embodiment.

The first resistor 201 and the fourth resistor 204 have substantially the same impurity concentration and substantially the same temperature coefficient. The second resistor 202 and the third resistor 203 have substantially the same impurity concentration and substantially the same temperature coefficient.

A potential V1 at the connection portion between the first resistor 201 and the second resistor 202 is input to the differential amplifier 210 via the external terminal OUT1. A potential V2 at the connection portion between the third resistor 203 and the fourth resistor 204 is input to the differential amplifier 210 via the external terminal OUT2. The external terminals OUT1 and OUT2 are formed by two pads 24 instead of the temperature detection terminals described above.

The differential amplifier 210 is provided in, for example, the ASIC chip 30, amplifies the difference between the potential V1 and the potential V2, and outputs a differential output Vout. Assuming that the resistance value of the first resistor 201 and the fourth resistor 204 is R1, and the resistance value of the second resistor 202 and the third resistor 203 is R2, the differential output value Vout is given by the following equation (1). expressed.

Vout=[(R1−R2)/(R1+R2)]×VDD (1)
Since the resistance values R1 and R2 change differently with temperature, the temperature can be obtained based on the differential output Vout. According to the equation (1), since the differential output Vout depends on the power supply potential VDD, it is preferable to obtain the temperature based on the value Vout/VDD obtained by dividing the differential output Vout by the power supply potential VDD.

Further, in the above embodiment, the humidity detection device 10 has a stack structure in which the sensor chip 20 and the ASIC chip 30 are laminated, but the present invention can be applied to humidity detection devices other than the stack structure.

Moreover, the present invention is not limited to a humidity detection device having a humidity detection section and a temperature detection section, but can also be applied to a temperature detection device having only a temperature detection section.

In addition, in the present disclosure, the positional relationship between two elements represented by the words “cover” and “on” means that the first element is indirectly provided on the surface of the second element via another element. It includes both cases where it is provided and cases where it is provided directly.

Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications can be made to the above-described embodiments without departing from the scope of the present invention. and substitutions can be added.

10 humidity detector, 20 sensor chip, 21 humidity detector, 22 temperature detector, 23 heating unit, 24, 24a to 24f bonding pad, 30 ASIC chip, 40 mold resin (sealing member), 41 lead terminal, 42 second 1 DAF, 45 2nd DAF, 50 opening, 51 effective opening, 60 ESD protection circuit, 61 diode, 70 p-type semiconductor substrate, 80 humidity detection capacitor, 81 reference capacitor, 82 reference electrode, 83 lower electrode, 84 upper part Electrode 84a Opening 86 Moisture Sensitive Film 87 Overcoat Film 88 Light Shielding Film 90 Bipolar Transistor 94 to 96 Wiring 97 Conductive Film 97a Opening 97b Wiring 107, 108 Wiring 110 First Insulating Film 111 Second insulating film 112 Third insulating film 120 First wiring layer 121 Second wiring layer 122 First plug layer (substrate connection layer) 122a Plug group 122b Light shielding wall (first light shielding wall) 122c Light shielding wall 123 second plug layer (interlayer connection layer) 123a group of plugs 123b group of plugs 123c light shielding wall (second light shielding wall) 123d light shielding wall

Claims (12)

A humidity detection device including a sensor chip having a humidity detection unit and a temperature detection unit, and a sealing member for sealing the sensor chip with the humidity detection unit and the temperature detection unit exposed,
The sensor chip is
a semiconductor substrate on which the temperature detection unit is formed;
a plurality of wiring layers formed on the semiconductor substrate;
a substrate connection layer that connects at least one wiring layer among the plurality of wiring layers and the semiconductor substrate;
one or more interlayer connection layers that connect between the plurality of wiring layers;
a first light shielding wall formed by the substrate connection layer and surrounding the temperature detection unit;
a second light shielding wall formed by the interlayer connection layer and surrounding the temperature detection unit;
and a light-shielding film formed of a wiring layer above the second light-shielding wall among the plurality of wiring layers and covering the upper side of the temperature detection unit. The humidity detection device according to claim 1, wherein the second light shielding wall is arranged outside the first light shielding wall. 3. The humidity detection device according to claim 1, wherein said first light shielding wall, said second light shielding wall, and said light shielding film are electrically connected to a ground electrode terminal formed on said sensor chip. A signal line is connected to the temperature detection unit,
4. The first light shielding wall and the second light shielding wall according to any one of claims 1 to 3, wherein the first light shielding wall and the second light shielding wall surround a portion of the periphery of the temperature detection unit other than the signal line drawn out from the temperature detection unit. humidity detector. The humidity detection device according to any one of claims 1 to 4, wherein the temperature detection section includes one or more bipolar transistors having bases and collectors connected to each other. 3. The base and the collector are impurity diffusion layers formed in the surface layer of the semiconductor substrate, respectively, and are connected to the interlayer connection layer and the lowest wiring layer among the plurality of wiring layers. 6. The humidity detector according to 5. The humidity detection unit is
a lower electrode formed of an uppermost wiring layer among the plurality of wiring layers;
a humidity sensitive film formed on the lower electrode;
an upper electrode formed on the humidity sensitive film;
The humidity detection device according to any one of claims 1 to 6, comprising: 8. The humidity detector according to claim 7, wherein the humidity sensitive film is made of polyimide. The humidity detection device according to any one of claims 1 to 8, wherein the light shielding film is made of aluminum or an aluminum silicon alloy, and the first light shielding wall and the second light shielding wall are made of tungsten. a semiconductor substrate on which a temperature detection portion is formed;
a plurality of wiring layers formed on the semiconductor substrate;
a substrate connection layer that connects at least one wiring layer among the plurality of wiring layers and the semiconductor substrate;
one or more interlayer connection layers that connect between the plurality of wiring layers;
a first light shielding wall formed by the substrate connection layer and surrounding the temperature detection unit;
a second light shielding wall formed by the interlayer connection layer and surrounding the temperature detection unit;
a light-shielding film formed of a wiring layer above the second light-shielding wall among the plurality of wiring layers and covering above the temperature detection unit;
A temperature sensing device having The temperature detection unit is a resistive temperature sensor comprising a bridge circuit in which a first resistor, a second resistor, a third resistor, and a fourth resistor are connected to each other,
The first resistor and the second resistor are connected in series between a power supply potential and a ground potential, and the third resistor and the fourth resistor are connected between the power supply potential and the ground potential. is connected in series with
11. The temperature detection device according to claim 10, wherein said first resistor, said second resistor, said third resistor, and said fourth resistor are formed on a surface layer of said semiconductor substrate. the first resistor and the fourth resistor have substantially the same impurity concentration and temperature coefficient;
12. The temperature detection device according to claim 11, wherein said second resistor and said third resistor have substantially the same impurity concentration and temperature coefficient.

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