JP2016532233A5 - - Google Patents

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Publication number
JP2016532233A5
JP2016532233A5 JP2016545961A JP2016545961A JP2016532233A5 JP 2016532233 A5 JP2016532233 A5 JP 2016532233A5 JP 2016545961 A JP2016545961 A JP 2016545961A JP 2016545961 A JP2016545961 A JP 2016545961A JP 2016532233 A5 JP2016532233 A5 JP 2016532233A5
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JP
Japan
Prior art keywords
address
cache
monitoring
core
unit
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JP2016545961A
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English (en)
Japanese (ja)
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JP6227151B2 (ja
JP2016532233A (ja
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Priority claimed from PCT/US2014/059130 external-priority patent/WO2015048826A1/en
Publication of JP2016532233A publication Critical patent/JP2016532233A/ja
Publication of JP2016532233A5 publication Critical patent/JP2016532233A5/ja
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Publication of JP6227151B2 publication Critical patent/JP6227151B2/ja
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JP2016545961A 2014-10-03 2014-10-03 アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 Active JP6227151B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/059130 WO2015048826A1 (en) 2013-09-27 2014-10-03 Scalably mechanism to implement an instruction that monitors for writes to an address

Publications (3)

Publication Number Publication Date
JP2016532233A JP2016532233A (ja) 2016-10-13
JP2016532233A5 true JP2016532233A5 (cg-RX-API-DMAC7.html) 2017-08-10
JP6227151B2 JP6227151B2 (ja) 2017-11-08

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ID=56973722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016545961A Active JP6227151B2 (ja) 2014-10-03 2014-10-03 アドレスへの書き込みに対する監視命令を実行するスケーラブル機構

Country Status (3)

Country Link
JP (1) JP6227151B2 (cg-RX-API-DMAC7.html)
KR (1) KR101979697B1 (cg-RX-API-DMAC7.html)
CN (1) CN105683922B (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112016007298T5 (de) * 2016-09-30 2019-06-13 Mitsubishi Electric Corporation Informationsverarbeitungsgerät
US10394678B2 (en) * 2016-12-29 2019-08-27 Intel Corporation Wait and poll instructions for monitoring a plurality of addresses
US10860487B2 (en) * 2019-04-17 2020-12-08 Chengdu Haiguang Integrated Circuit Design Co. Ltd. Multi-core processing device and method of transferring data between cores thereof
CN111857591B (zh) * 2020-07-20 2024-08-09 昆仑芯(北京)科技有限公司 用于执行指令的方法、装置、设备和计算机可读存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
US20070282928A1 (en) * 2006-06-06 2007-12-06 Guofang Jiao Processor core stack extension
US20080005504A1 (en) * 2006-06-30 2008-01-03 Jesse Barnes Global overflow method for virtualized transactional memory
US9081687B2 (en) * 2007-12-28 2015-07-14 Intel Corporation Method and apparatus for MONITOR and MWAIT in a distributed cache architecture

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