CN105683922B - 实现监视对地址的写入的指令的可扩展机制 - Google Patents

实现监视对地址的写入的指令的可扩展机制 Download PDF

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Publication number
CN105683922B
CN105683922B CN201480047555.XA CN201480047555A CN105683922B CN 105683922 B CN105683922 B CN 105683922B CN 201480047555 A CN201480047555 A CN 201480047555A CN 105683922 B CN105683922 B CN 105683922B
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cache
address
core
processor
monitoring
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CN105683922A (zh
Inventor
Y-C.刘
B.法希姆
E.G.霍尔诺尔
J.D.张伯伦
S.R.范多伦
A.胡安
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Intel Corp
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Intel Corp
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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201480047555.XA 2014-10-03 2014-10-03 实现监视对地址的写入的指令的可扩展机制 Active CN105683922B (zh)

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PCT/US2014/059130 WO2015048826A1 (en) 2013-09-27 2014-10-03 Scalably mechanism to implement an instruction that monitors for writes to an address

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CN105683922A CN105683922A (zh) 2016-06-15
CN105683922B true CN105683922B (zh) 2018-12-11

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JP (1) JP6227151B2 (cg-RX-API-DMAC7.html)
KR (1) KR101979697B1 (cg-RX-API-DMAC7.html)
CN (1) CN105683922B (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112016007298T5 (de) * 2016-09-30 2019-06-13 Mitsubishi Electric Corporation Informationsverarbeitungsgerät
US10394678B2 (en) * 2016-12-29 2019-08-27 Intel Corporation Wait and poll instructions for monitoring a plurality of addresses
US10860487B2 (en) * 2019-04-17 2020-12-08 Chengdu Haiguang Integrated Circuit Design Co. Ltd. Multi-core processing device and method of transferring data between cores thereof
CN111857591B (zh) * 2020-07-20 2024-08-09 昆仑芯(北京)科技有限公司 用于执行指令的方法、装置、设备和计算机可读存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097544A (zh) * 2006-06-30 2008-01-02 英特尔公司 虚拟化事务存储器的全局溢出方法
CN101460927A (zh) * 2006-06-06 2009-06-17 高通股份有限公司 处理器核心堆栈扩展
US20090172284A1 (en) * 2007-12-28 2009-07-02 Zeev Offen Method and apparatus for monitor and mwait in a distributed cache architecture

Family Cites Families (2)

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Publication number Priority date Publication date Assignee Title
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101460927A (zh) * 2006-06-06 2009-06-17 高通股份有限公司 处理器核心堆栈扩展
CN101097544A (zh) * 2006-06-30 2008-01-02 英特尔公司 虚拟化事务存储器的全局溢出方法
US20090172284A1 (en) * 2007-12-28 2009-07-02 Zeev Offen Method and apparatus for monitor and mwait in a distributed cache architecture

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KR20160041950A (ko) 2016-04-18
CN105683922A (zh) 2016-06-15
KR101979697B1 (ko) 2019-05-17
JP6227151B2 (ja) 2017-11-08
JP2016532233A (ja) 2016-10-13

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