JP6227151B2 - アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 - Google Patents

アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 Download PDF

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JP6227151B2
JP6227151B2 JP2016545961A JP2016545961A JP6227151B2 JP 6227151 B2 JP6227151 B2 JP 6227151B2 JP 2016545961 A JP2016545961 A JP 2016545961A JP 2016545961 A JP2016545961 A JP 2016545961A JP 6227151 B2 JP6227151 B2 JP 6227151B2
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cache
core
address
monitoring
unit
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JP2016532233A (ja
JP2016532233A5 (cg-RX-API-DMAC7.html
Inventor
リウ、エン−チェン
ファヒム、バハー
ジー． ハルノア、エリック
ジー． ハルノア、エリック
ディー． チャンベルライン、ジェフリー
ディー． チャンベルライン、ジェフリー
ドレン、ステファン アール． バン
ドレン、ステファン アール． バン
ジュアン、アントニオ
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Intel Corp
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Intel Corp
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Priority claimed from PCT/US2014/059130 external-priority patent/WO2015048826A1/en
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JP2016545961A 2014-10-03 2014-10-03 アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 Active JP6227151B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/059130 WO2015048826A1 (en) 2013-09-27 2014-10-03 Scalably mechanism to implement an instruction that monitors for writes to an address

Publications (3)

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JP2016532233A JP2016532233A (ja) 2016-10-13
JP2016532233A5 JP2016532233A5 (cg-RX-API-DMAC7.html) 2017-08-10
JP6227151B2 true JP6227151B2 (ja) 2017-11-08

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JP (1) JP6227151B2 (cg-RX-API-DMAC7.html)
KR (1) KR101979697B1 (cg-RX-API-DMAC7.html)
CN (1) CN105683922B (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3872629A3 (en) * 2020-07-20 2022-01-05 Beijing Baidu Netcom Science And Technology Co., Ltd. Method and apparatus for executing instructions, device, and computer readable storage medium

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112016007298T5 (de) * 2016-09-30 2019-06-13 Mitsubishi Electric Corporation Informationsverarbeitungsgerät
US10394678B2 (en) * 2016-12-29 2019-08-27 Intel Corporation Wait and poll instructions for monitoring a plurality of addresses
US10860487B2 (en) * 2019-04-17 2020-12-08 Chengdu Haiguang Integrated Circuit Design Co. Ltd. Multi-core processing device and method of transferring data between cores thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
US20070282928A1 (en) * 2006-06-06 2007-12-06 Guofang Jiao Processor core stack extension
US20080005504A1 (en) * 2006-06-30 2008-01-03 Jesse Barnes Global overflow method for virtualized transactional memory
US9081687B2 (en) * 2007-12-28 2015-07-14 Intel Corporation Method and apparatus for MONITOR and MWAIT in a distributed cache architecture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3872629A3 (en) * 2020-07-20 2022-01-05 Beijing Baidu Netcom Science And Technology Co., Ltd. Method and apparatus for executing instructions, device, and computer readable storage medium
US11748099B2 (en) 2020-07-20 2023-09-05 Beijing Baidu Netcom Science And Technology, Co., Ltd. Method for executing instructions, device, and computer readable storage medium

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KR20160041950A (ko) 2016-04-18
CN105683922A (zh) 2016-06-15
KR101979697B1 (ko) 2019-05-17
CN105683922B (zh) 2018-12-11
JP2016532233A (ja) 2016-10-13

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