KR101979697B1 - 어드레스로의 기입들을 모니터링하는 명령어를 구현하는 스케일가능형 메커니즘 - Google Patents

어드레스로의 기입들을 모니터링하는 명령어를 구현하는 스케일가능형 메커니즘 Download PDF

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KR101979697B1
KR101979697B1 KR1020167005327A KR20167005327A KR101979697B1 KR 101979697 B1 KR101979697 B1 KR 101979697B1 KR 1020167005327 A KR1020167005327 A KR 1020167005327A KR 20167005327 A KR20167005327 A KR 20167005327A KR 101979697 B1 KR101979697 B1 KR 101979697B1
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cache
core
address
monitor
processor
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KR20160041950A (ko
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옌-정 리우
바하 파힘
에릭 지. 할노르
제프리 디. 챔버레인
스테픈 알. 반 도렌
안토니오 후안
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인텔 코포레이션
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Priority claimed from PCT/US2014/059130 external-priority patent/WO2015048826A1/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020167005327A 2014-10-03 2014-10-03 어드레스로의 기입들을 모니터링하는 명령어를 구현하는 스케일가능형 메커니즘 Expired - Fee Related KR101979697B1 (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/059130 WO2015048826A1 (en) 2013-09-27 2014-10-03 Scalably mechanism to implement an instruction that monitors for writes to an address

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KR20160041950A KR20160041950A (ko) 2016-04-18
KR101979697B1 true KR101979697B1 (ko) 2019-05-17

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JP (1) JP6227151B2 (cg-RX-API-DMAC7.html)
KR (1) KR101979697B1 (cg-RX-API-DMAC7.html)
CN (1) CN105683922B (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112016007298T5 (de) * 2016-09-30 2019-06-13 Mitsubishi Electric Corporation Informationsverarbeitungsgerät
US10394678B2 (en) * 2016-12-29 2019-08-27 Intel Corporation Wait and poll instructions for monitoring a plurality of addresses
US10860487B2 (en) * 2019-04-17 2020-12-08 Chengdu Haiguang Integrated Circuit Design Co. Ltd. Multi-core processing device and method of transferring data between cores thereof
CN111857591B (zh) * 2020-07-20 2024-08-09 昆仑芯(北京)科技有限公司 用于执行指令的方法、装置、设备和计算机可读存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070282928A1 (en) * 2006-06-06 2007-12-06 Guofang Jiao Processor core stack extension
US20080005504A1 (en) * 2006-06-30 2008-01-03 Jesse Barnes Global overflow method for virtualized transactional memory
US20090172284A1 (en) * 2007-12-28 2009-07-02 Zeev Offen Method and apparatus for monitor and mwait in a distributed cache architecture

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070282928A1 (en) * 2006-06-06 2007-12-06 Guofang Jiao Processor core stack extension
US20080005504A1 (en) * 2006-06-30 2008-01-03 Jesse Barnes Global overflow method for virtualized transactional memory
US20090172284A1 (en) * 2007-12-28 2009-07-02 Zeev Offen Method and apparatus for monitor and mwait in a distributed cache architecture

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KR20160041950A (ko) 2016-04-18
CN105683922A (zh) 2016-06-15
JP6227151B2 (ja) 2017-11-08
CN105683922B (zh) 2018-12-11
JP2016532233A (ja) 2016-10-13

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