WO2018001528A1

WO2018001528A1 - Apparatus and methods to manage memory side cache eviction

Info

Publication number: WO2018001528A1
Application number: PCT/EP2016/065598
Authority: WO
Inventors: Alejandro Duran Gonzalez; Robert G. Blankenship; Francesc Guim Bernat; Karthik Kumar; Martin P. DIMITROV; Thomas WILLHALM
Original assignee: Intel Corporation
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2018-01-04
Also published as: DE112016007029T5

Abstract

A processor includes a processing core and a caching circuit, communicatively coupled to the processing core, comprising a dead block predictor (DBP) to predict that a cache line in a last-level cache (LLC) is not to be accessed until an eviction from the LLC, wherein responsive to predicting that the cache line is not to be accessed until the eviction, the caching circuit is to issue an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line.

Description

APPARATUS AND METHODS TO MANAGE MEMORY SIDE CACHE

EVICTION

TECHNICAL FIELD

[0001] Embodiments of the disclosure relate generally to a processing system, and, more specifically, to apparatus and methods to manage memory-side cache eviction.

BACKGROUND

[0002] Caches of a processor may be used to hold copies of data stored in memory in order to shorten the latency of subsequent accesses to the data by processing cores in the processor. In some scenarios, caches may be shared by multiple hardware processing components associated with the processor. The caches may be used to cache data both from memory-mapped input/output devices (MMIO), such as data from stored on a hard disk or in a basic input output system (BIOS) read only memory (ROM), as well as from random access memory (RAM).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific

embodiments, but are for explanation and understanding only.

[0004] Figure 1 illustrates a processing system according to an embodiment of the present disclosure.

[0005] Figure 2 illustrates a detailed processing system according to an embodiment of the present disclosure.

[0006] Figure 3 illustrates cross-function flowcharts using memory-side cache track logic to evict a cache line and read data from far memory according to an embodiment of the present disclosure.

[0007] Figure 4 is a flow diagram of a method to operate a processing system according to an embodiment of the disclosure.

[0008] Figure 5A is a block diagram illustrating a micro -architecture for a processor in which one embodiment of the disclosure may be used. [0009] Figure 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented according to at least one embodiment of the disclosure.

[0010] Figure 6 illustrates a block diagram of the micro-architecture for a processor in accordance with one embodiment of the disclosure.

[0011] Figure 7 is a block diagram illustrating a system in which an embodiment of the disclosure may be used.

[0012] Figure 8 is a block diagram of a system in which an embodiment of the disclosure may operate.

[0013] Figure 9 is a block diagram of a system in which an embodiment of the disclosure may operate.

[0014] Figure 10 is a block diagram of a System-on-a-Chip (SoC) in accordance with an embodiment of the present disclosure

[0015] Figure 11 is a block diagram of an embodiment of an SoC design in accordance with the present disclosure.

[0016] Figure 12 illustrates a block diagram of one embodiment of a computer system.

DETAILED DESCRIPTION

[0017] The memory associated with a processor may include a tiered memory structure including a memory-side cache (MSC) and a far memory. The processor may be associated with a cache structure including level 1 to level 3 (LI - L3) caches and a last-level cache (LLC). The contents stored in a cache line of the LLC may be evicted to the MSC. The MSC can be a near memory (i.e., a memory that is close to a processor) that caches contents from the LLC for a far memory (i.e., a memory that is farther away from the processor than the near memory) where the content of the evicted cache line is to be stored. Current implementations do not associate the evicted cache line with a reason of the cache eviction, which may cause inefficient evictions when entries in the MSC are further evicted to the far memory. Embodiments of the present disclosure provide a technical solution to substantially eliminate the inefficient eviction of MSC entries to the far memory by classifying the MSC entries according to the reason of their cache evictions. [0018] Figure 1 illustrates a processing system (e.g., a system-on-a chip (SoC)) 100 according to an embodiment of the present disclosure. Processing system 100 may include a processor 102 and a memory 104 that is tiered, including a memory- side cache (near memory) 122 and a far memory 124. Processor 102 can be a hardware processor such as, for example, a central processing unit (CPU). Processor 102 may further include one or more processing cores 106, a caching agent 108, and a memory controller 110 that are communicatively coupled to either other via an on-die interconnect 112. Processing core 106 may include logic circuits such as, for example, an instruction execution pipeline to execute operations (e.g., uops) and perform certain tasks. The tasks may include the execution of software applications 114 including operations (e.g., stores and loads) to access data in memory 104 via a hierarchical cache structure that may include level 1 to level 3 (LI - L3) caches associated with cores 106. Caching agent 108 and memory controller 110 may include logic circuits that manage the transactions between different levels of caches and memory 104. In one embodiment, caching agent 108 is a logic circuit unit that may process transactions with memory 104 and retain copies of the data stored in memory 104.

[0019] As shown in Figure 1, caching agent 108 may further include a last-level cache (LLC) 116. LLC 116 is the highest level of cache shared by processing cores 106 to store copies of data retrieved from memory 104 or copies of data to be evicted to memory 104. Compared to LI to L3 caches, LLC 116 is commonly the farthest from processing cores 106 and the closest to the memory 104. When processing cores 106 need to load data from a memory location in memory 104 or store data at a memory location in memory 104, processing core 106 may first check caches (in an order from LI to L3, and then LLC 116) for a corresponding entry (referred to as a cache line) containing the memory location (e.g., the memory address) and the copy of the data stored from the memory location. If processing cores 106 find the corresponding cache line, a cache hit has occurred, and processing cores 106 may access (read or write) the data stored in the cache. If processing cores 106 do not find the corresponding cache line in any of the caches (LI - L3 and LLC), a cache miss has occurred. In the event that a cache miss occurred in LLC 116 (i.e., no corresponding cache line in any of the caches), processing cores 106 may create a new cache line in LLC 116 for the corresponding memory address to store a copy of the data. The new cache line in LLC 116 may include a tag field to store the memory location (memory address), a data block to store the copy of the data (payload), and a flag bit to indicate whether the cache is valid or invalid that is set according to a cache coherent protocol. [0020] LLC 116 may include a limited number of cache lines. When the cache lines in LLC 116 are all used (i.e., populated with copies of memory data), in order to make room for a new cache line, caching agent 108 may need to evict content of one of the existing entries into memory 104 according to a cache replacement policy (e.g., the least-recently used (LRU) policy). In addition to evicting an existing cache line when LLC 116 is filled up, caching agent 108 may also include a dead block predictor (DBP) 118 that includes logic circuit to calculate the probability of a cache line or a block of cache lines (referred to as a cache block) that is not to be used.

[0021] A cache line (or cache block) in LLC 116 is alive from the time of its creation to the time of its last reference by processing cores 106. From the last reference time until its eviction, the cache line (or cache block) is deemed as dead. Thus, processor 102 can run more efficiently if dead blocks in LLC 116 may be predicted by DBP 118 earlier. DBP 116 may predict dead blocks in LLC 116 based on certain criteria such as, for example, tracing the content of a cache line from LLC 116 to LI - L3 caches, or the number of clock cycles that a cache line is alive. A cache line (or cache block) that is predicted not to be used until eviction is referred to as a dead block. DBP 118 may calculate the probability of a cache line being a dead block and when the probability exceeds a threshold value, determine a cache block as a dead block and request caching agent 118 to proactively evict the dead blocks in LLC 116, even before the LLC is filled up, to make the space occupied by dead blocks available for new cache lines, thus improving the efficiency of LLC 116.

[0022] When a cache line in LLC 116 is evicted either due to reaching the LLC capacity or due to eviction requests generated by DBP 118, caching agent 108 may send an evict message to memory controller 110 (also referred to as a memory management unit (MMU)). In some implementations, the evict message may include the virtual memory address and data payload. In response to receiving the evict message, memory controller 110 may perform virtual to physical memory address mapping using a page table accessible by the memory controller 110 and then store the data payload at the physical memory address in memory 104. Current implementations do not identify whether the cache eviction is caused by reaching LLC capacity limitation or by a dead block prediction generated from DBP 118. The lack of identification of the reason for cache evictions may cause inefficient eviction from MSC entries to the far memory. For example, an MSC entry generated due to reaching the LLC cache limit may be evicted to the far memory prior to an MSC entry generated due to a dead block. [0023] To accommodate large data, tiered structure of memory 104 can include different types of memory devices that have different sizes and access speeds. For example, multi-level memory 104 may include 3D cross-point non- volatile memory (3D XP memory) that tends to offer larger capacities than dynamic random-access memory (DRAM) but is associated with higher latencies. The 3D XP memory can be used as far memory 124 that is further away (or taking longer time to access) from processor 102. Multi-level memory 104 may also include high bandwidth memory (HBM) such as, for example, multi-channel DRAM (MCDRAM) that has a faster access speed but small capacity. As shown in Figure 1, the HBM may be employed as near memory 122 that processor 102 accesses first before accessing far memory 124.

[0024] In some implementations, near memory 122 may serve as a memory-side cache (MSC) for far memory 124. MSC 122 may contain MSC entries that store the data payload stored in far memory 124 and corresponding memory addresses of far memory 124. Thus, when a cache eviction occurs, memory controller 110 may first create a MSC entry in MSC 122 to store the data payload and the memory address identified in the evict message. MSC 122 may eventually evict the content in the MSC entry to far memory 124.

[0025] When a cache miss occurs in processor 102, processing cores 106 may first look at MSC 122 to determine whether MSC 122 has a copy of the data that is stored in multilevel memory 104. If MSC 122 contains the data, a MSC hit occurs. Processing cores 106 may access the data from MSC 122. If MSC 122 does not contain the data, a MSC miss occurs. Processing cores 106 need to access the data from far memory 124. Because the access to far memory is typically slow, MSC misses may significantly increase the time for processor 102 to complete a task.

[0026] After a LLC cache line is evicted to the memory 124, the LLC cache line is first cached, as an MSC cache entry, in MSC 122 before it is being further evicted to the far memory. Thus, processing cores 106 may access the MSC entries from MSC 122 if they are not evicted further to the far memory. If they are evicted to the far memory, the processing cores 106 need to retrieve from the far memory. The retrieval from the far memory can be quite expensive. Current implementations of pressing systems do not identify the reason of a cache eviction in the evict message transmitted from caching agent 108 to memory controller

110. Thus memory controller 122 creates MSC entries in MSC 122 without distinctions among those entries. In operation, however, the likelihood of an MSC entry being accessed by processing cores 106 may vary as a function of the reason that it was evicted by caching agent 108. For example, a MSC entry created due to reaching the capacity of LLC 116 is more likely to be accessed by processing cores 106 than those created due to the predictions generated by DBP 1 18.

[0027] Embodiments of the present disclosure provide a technical solution that provides information (e.g., a flag) in an evict message to identify the cause of cache eviction. Further, memory controller 110 may include a MSC tracking circuit 120 to track MSC entries associated with certain flags and evict these MSC entries according to an MSC replacement policy to improve the efficiency of MSC 122. In one embodiment, caching agent 122 may provide a one-bit indicator (DBP flag) in evict message 126 to indicate that the cache eviction was caused by DBP 118 (e.g., DBP flag = 1 to indicate dead block eviction and DBP flag = 0 to indicate non-dead block eviction). In another embodiment, caching agent 122 may provide an indicator that is more than one bit to indicate different types of eviction. The indicator can be a flag bit that is separate from the payload. Alternatively, the indicator can be inserted in the payload at a specific bit location (e.g., the first bit).

[0028] MSC tracking circuit 120 of memory controller 110 may receive evict message

126 with the DBP flag enabled to indicate a DBP cache eviction and create an entry in an MSC buffer 128 which is a region within MSC 122 to store temporary MSC entries. These temporary MSC entries stored in MSC buffer 128 (referred to as MSC buffer entries) are associated with a maximum life time value stored in a corresponding counter. An MSC buffer entry is ready to be evicted to a far memory when its maximum life time is reached. The MSC buffer entry in MSC buffer 128 may contain the data payload, the memory address of far memory 124 to store the data payload, and a time limit that, when reached, the entry is to be evicted to far memory 124 if the entry has not been accessed by processing cores 106 (or any other agents) within the time limit. In one embodiment, the time limit may be a predetermined number (N) of processor clock cycles passed since storing the entry in MSC buffer 128. In this way, the time of MSC entries in MSC 122 associated DBP cache evictions may be tracked using counters and evicted to far memory 124 if they are not touched by processing cores 106 within the time limit set in the MSC replacement policy. In the event that MSC tracking circuit 120 receives an evict message in which the DBP flag is not set (indicating a non-dead block eviction), memory controller 1 10 may create an MSC entry in MSC 122 (outside MSC buffer 128). This MSC entry is not associated with a dead block and is not tracked by MSC tracking circuit 120.

[0029] Figure 2 illustrates a detailed processing system 200 according to an embodiment of the present disclosure. As shown in Figure 2 (similar to Figure 1),

processing system 200 may include a memory controller 110 to receive evict messages 126 from a caching agent and to access (read or write) a multi-level memory 104. Memory controller 110 may include MSC tracking circuit 120 that may determine whether a flag (e.g., a DBP flag) in the evict message is enabled to indicate that the evicted cache line belongs to a special class (e.g., dead blocks) associated with a limited life time. Responsive to

determining that the flag in the evict message is enabled (e.g., DBP flag = 1), MSC tracking circuit 120 may create an MSC buffer entry in MSC buffer 128 which is part of MSC 122.

[0030] In one embodiment, MSC buffer 128 may include a number of MSC buffer entries 202 - 206. Each MSC buffer entry 202 - 206 may contain a first field to store a memory address (e.g., Memory address 1, 2, 3) and a second field to store a data payload (e.g., Payload 1, 2, 3). The data payload represents the content evicted from the LLC to memory 104, and the memory address represents the physical memory address associated with far memory 124 at which the data payload is stored. The MSC 122 is typically smaller but faster than far memory 124 so that a two-tiered memory 104 may handle a large quantity of data more efficiently. In one embodiment, MSC tracking circuit 120 may have access to a stack of counters 208 - 210. Each one of counters 208 - 212 is assigned to a respective one of MSC buffer entries 202 - 206 in a buffer region (MSC buffer 128) of MSC 122. For example, counters 208 - 212 may be associated with MSC buffer entries 202 -206, respectively. Responsive to determining that the flag in the evict message is enabled and creating a corresponding MSC buffer entry 202 -206, MSC tracking circuit 120 initiates the corresponding counter 208 - 212 to an initial value. In one embodiment, the initial value is a threshold time value indicating a maximum life time of the MSC buffer entry that, when reached, the MSC buffer entry is evicted to far memory 124. In one embodiment, an application programming interface (API) may be provided to software applications 114 executing on processing cores 106 to allow the application set the initial values in counters 208 - 212. For example, software applications may set a model-specific register (MSR) containing the maximum life time to a pre-set number of clock cycles

(MSR DBP MSC N CYCLES).

[0031] The counter value may be decreased each clock cycle. MSC tracking circuit

120 may track the counter value until it reaches zero, indicating that the MSC buffer entry 202 - 206 can be evicted to far memory 124. In one embodiment, when the counter value reaches the value of zero, memory controller 110 may initiate an eviction of the data payload to far memory 124 based on the memory address stored in the MSC buffer entry without waiting for further trigger events to occur. Alternatively, MSC tracking circuit 120 may reset the counter value to the maximum life time if the MSC buffer entry is accessed (read from or written to) by processing core 106 before the counter value reaches zero.

[0032] In another embodiment, after the counter value reaches the zero value, memory controller 110 does not evict the MSC buffer entry immediately. Instead, memory controller 110 waits for a further trigger event to initiate the eviction of the MSC buffer entry. In one embodiment, MSC tracking circuit 120 may monitor the number of pending requests (which can be any types of memory access requests received by memory controller 110) at interconnect egress ports associated with the on-die interconnect 112 as shown in Figure 1. The trigger event to initiate the eviction of the MSC buffer entry can occur when the number of requests on the interconnect egress ports is lower than a threshold value (e.g., 10). Thus, the eviction of the MSC buffer entry may happen based on a measurement of the utilization of the MSC 122 and the evict event may occur during memory controller 110 determines that there is a low utilization of memory controller 110.

[0033] In another embodiment, memory controller 110 may initiate the memory eviction based on other triggering events such as, for example, the history of prior memory evictions (e.g., which far memory regions are evicted to). Memory controller 110 may include a prediction circuit to detect the occurrences of these triggering events.

[0034] In the event that processing cores 106 executes an operation that reads data from memory 104, memory controller 110 may first check MSC 122 including MSC buffer 128 to determine whether the requested data is stored in MSC 122. In response to

determining that the data is stored in an entry of MSC 122 (e.g., in MSC buffer 128 before an eviction occurs or an MSC entry outside MSC buffer 128), memory controller 110 may retrieve the data from MSC 122 with less latency.

[0035] In one embodiment, MSC 122 and far memory 124 are mutually exclusive in the sense that an entry stored in one (e.g., MSC 122) is not stored in another (e.g., far memory 124). In the exclusive memory situation, the eviction may happen by executing a write of the MSC buffer entry in far memory 124. In another embodiment, MSC 122 and far memory 124 are inclusive in the sense that an entry stored in one (e.g., MSC 122) is also stored in another (e.g., far memory 124). In the inclusive memory situation, after writing the MSC buffer entry to far memory 124, memory controller 110 may further remove the MSC buffer entry in MSC buffer 128. For example, memory controller 1 10 may remove the MSC buffer entry 202 - 204 by setting status flag to invalid. In one embodiment, an MSC buffer entry may include a second flag (e.g., one bit) to indicate whether the MSC buffer entry is a valid entry or an invalid entry. [0036] Figure 3 illustrates cross-function flowcharts 300 using MSC tracking circuit to evict a cache line and read data from far memory according to an embodiment of the present disclosure. Figure 3 illustrates the flow of evicting a dirty cache line (@a) from LLC 116 and subsequently, reading data from far memory 124 (@b) by employing MSC tracking circuit 120.

[0037] As shown in Figure 3, embodiments of the present disclosure may help reduce the delay to retrieve data (@b) from far memory 124 and reduce the likelihood of committing an expensive error to retrieve an entry from the far memory. At 330, processing cores 106 may execute a memory operation (e.g., a memory write) that generates a cache line (@a) in LLC 116. The cache line (@a) may be modified due to operations executed by processing cores 106 to become a dirty cache line. At 332, DBP 118 of caching agent 108 may determine, based on a calculated probability that cache line (@a) is not being accessed until its eviction by processing cores 106, that cache line (@a) is a dead block that is not likely accessed by processing cores 106 again. In response to determining that the cache line (@a) is a dead block, at 334, caching agent 108 may evict the cache line (@a) from LLC 116 to an MSC buffer entry in MSC buffer 128 of MSC 122 and send an evict message including the memory address, the data payload, and a flag indicating that the cache line is evicted as a dead block. Memory controller 110 may create the MSC buffer entry including the memory address and the data payload (@a). In response to creating the MSC buffer entry, memory controller may initiate a counter assigned to the MSC buffer entry to a time limit value (e.g., number of processor clock cycles). The counter value may be decremented as the processor clock moves forward. At 336, MSC tracker logic 120 may monitor the counter value assigned to the MSC buffer entry to determine if the counter value has reached zero. If the counter value reaches zero, memory controller 110 may evict the content of the MSC buffer entry to far memory 124. Alternatively, MSC tracking circuit 120 may wait for a trigger event (e.g., when the utilization of resources is low according a number of requests on the online interconnect 112) to happen and in response to the occurrence of the trigger event after the counter reaches zero, evict the content of the MSC buffer entry to far memory 124.

[0038] Subsequently, at 338, processing cores 106 may execute a second operation that reads data (@b) from far memory 106. At 340, caching agent 108 may determine that LLC 116 (or any one of LI - L3 caches) does not contain a copy of the data (@b) and forward the read request to memory controller 110 to search for data (@b) in MSC 122. In response to determining that MSC 122 does not contain the data (@b), at 342, memory controller 110 may read that data (@b) stored in far memory 124 without the need to evict MSC buffer entry associated with cache line (@a). At 344, memory controller 110 may create a new MSC entry in MSC 122 associated with the data (@b), where the MSC entry may contain the memory address and the data payload. At 346, memory controller 110 may inform caching agent 108 to create a new cache line for the data (@b) retrieved from far memoryl24. At 348, processing cores 106 may receive the data (@b) retrieved from far memory 124. The embodiment of the present disclosure as shown in Figure 3 may reduce the data (@b) retrieval time by pre-evicting MSC buffer entry (@a) at an opportune time when MSC 122 is not busy, thus improving the performance of processor 102 and processing system 100.

[0039] Figure 4 is a flow diagram of a method to operate a processing system according to an embodiment of the disclosure. Method 400 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing system, a general purpose computer system, or a dedicated machine), firmware, or a combination thereof. In one embodiment, method 400 may be performed, in part, by processing logics of the caching agent 108 described with respect to Figure 1.

[0040] For simplicity of explanation, the method 400 is depicted and described as a series of acts. However, acts in accordance with this disclosure can occur in various orders and/or concurrently and with other acts not presented and described herein. Furthermore, not all illustrated acts may be performed to implement the method 400 in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the method 400 could alternatively be represented as a series of interrelated states via a state diagram or events.

[0041] Referring to Figure 4, at 402, a dead block predictor (DBP) of a caching agent may determine that a cache line of a last-level cache (LLC) is a dead block that needs to be evicted to a memory-side cache in a multi-level memory.

[0042] At 404, responsive to determining that the cache line is the dead block that needs to be evicted, the caching agent may generate an evict message to a memory controller. The evict message include a payload and a memory address that are stored in the cache line, and a flag indicating a DBP status of the cache line.

[0043] At 406, the caching agent may transmit the evict message to a memory-side cache (MSC) tracking circuit in the memory controller. The MSC tracking circuit may create an MSC entry in the MSC, where the MSC entry has a limited life time. [0044] Figure 5A is a block diagram illustrating a micro -architecture for a processor

500 that implements the processing device including heterogeneous cores in accordance with one embodiment of the disclosure. Specifically, processor 500 depicts an in-order

architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the disclosure.

[0045] Processor 500 includes a front end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570. The processor 500 may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, processor 500 may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like. In one embodiment, processor 500 may be a multi-core processor or may part of a multi-processor system.

[0046] The front end unit 530 includes a branch prediction unit 532 coupled to an instruction cache unit 534, which is coupled to an instruction translation lookaside buffer (TLB) 536, which is coupled to an instruction fetch unit 538, which is coupled to a decode unit 540. The decode unit 540 (also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points,

microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder 540 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit 534 is further coupled to the memory unit 570. The decode unit 540 is coupled to a rename/allocator unit 552 in the execution engine unit 550.

[0047] The execution engine unit 550 includes the rename/allocator unit 552 coupled to a retirement unit 554 and a set of one or more scheduler unit(s) 556. The scheduler unit(s)

556 represents any number of different schedulers, including reservations stations (RS), central instruction window, etc. The scheduler unit(s) 556 is coupled to the physical register file(s) unit(s) 558. Each of the physical register file(s) units 558 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s) 558 is overlapped by the retirement unit 554 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).

[0048] Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit 554 and the physical register file(s) unit(s) 558 are coupled to the execution cluster(s) 560. The execution cluster(s) 560 includes a set of one or more execution units 562 and a set of one or more memory access units 564. The execution units 562 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

[0049] While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 556, physical register file(s) unit(s) 558, and execution cluster(s) 560 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of

data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 564). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

[0050] The set of memory access units 564 is coupled to the memory unit 570, which may include a data prefetcher 580, a data TLB unit 572, a data cache unit (DCU) 574, and a level 2 (L2) cache unit 576, to name a few examples. In some embodiments DCU 574 is also known as a first level data cache (LI cache). The DCU 574 may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency. The data TLB unit 572 is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces. In one exemplary embodiment, the memory access units 564 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570. The L2 cache unit 576 may be coupled to one or more other levels of cache and eventually to a main memory.

[0051] In one embodiment, the data prefetcher 580 speculatively loads/prefetches data to the DCU 574 by automatically predicting which data a program is about to consume.

Prefeteching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., lower level caches or memory) to a higher-level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.

[0052] The processor 500 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).

[0053] It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

[0054] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (LI) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor.

Alternatively, all of the cache may be external to the core and/or the processor.

[0055] Figure 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processing device 500 of Figure 5A according to some embodiments of the disclosure. The solid lined boxes in Figure 5B illustrate an in-order pipeline, while the dashed lined boxes illustrates a register renaming, out-of-order issue/execution pipeline. In Figure 5B, a processor pipeline 500 includes a fetch stage 502, a length decode stage 504, a decode stage 506, an allocation stage 508, a renaming stage 510, a scheduling (also known as a dispatch or issue) stage 512, a register read/memory read stage 514, an execute stage 516, a write back/memory write stage 518, an exception handling stage 522, and a commit stage 524. In some embodiments, the ordering of stages 502-524 may be different than illustrated and are not limited to the specific ordering shown in Figure 5B.

[0056] Figure 6 illustrates a block diagram of the micro-architecture for a processor

600 in accordance with one embodiment of the disclosure. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end 601 is the part of the processor 600 that fetches instructions to be executed and prepares them to be used later in the processor pipeline.

[0057] The front end 601 may include several units. In one embodiment, the instruction prefetcher 626 fetches instructions from memory and feeds them to an instruction decoder 628 which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called "microinstructions" or "micro-operations" (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache 630 takes decoded uops and assembles them into program ordered sequences or traces in the uop queue 634 for execution. When the trace cache 630 encounters a complex instruction, the microcode ROM 632 provides the uops needed to complete the operation.

[0058] Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder 628 accesses the microcode ROM 632 to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder 628. In another embodiment, an instruction can be stored within the microcode ROM 632 should a number of micro-ops be needed to accomplish the operation. The trace cache 630 refers to an entry point programmable logic array (PLA) to determine a correct micro -instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM 632. After the microcode ROM 632 finishes sequencing micro-ops for an instruction, the front end 601 of the machine resumes fetching micro-ops from the trace cache 630.

[0059] The out-of-order execution engine 603 is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and reorder the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler 602, slow/general floating point scheduler 604, and simple floating point scheduler 606. The uop schedulers 602, 604, 606, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. The fast scheduler 602 of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

[0060] Register files 608, 610, sit between the schedulers 602, 604, 606, and the execution units 612, 614, 616, 618, 620, 622, 624 in the execution block 611. There is a separate register file 608, 610, for integer and floating point operations, respectively. Each register file 608, 610, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file 608 and the floating point register file 610 are also capable of communicating data with the other. For one embodiment, the integer register file 608 is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data. The floating point register file 610 of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

[0061] The execution block 611 contains the execution units 612, 614, 616, 618, 620,

622, 624, where the instructions are actually executed. This section includes the register files 608, 610, that store the integer and floating point data operand values that the microinstructions need to execute. The processor 600 of one embodiment is comprised of a number of execution units: address generation unit (AGU) 612, AGU 614, fast ALU 616, fast ALU 618, slow ALU 620, floating point ALU 622, floating point move unit 624. For one embodiment, the floating point execution blocks 622, 624, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU 622 of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the present disclosure, instructions involving a floating point value may be handled with the floating point hardware.

[0062] In one embodiment, the ALU operations go to the high-speed ALU execution units 616, 618. The fast ALUs 616, 618, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU 620 as the slow ALU 620 includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations are executed by the AGUs 612, 614. For one embodiment, the integer ALUs 616, 618, 620, are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs 616, 618, 620, can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating point units 622, 624, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating point units 622, 624, can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

[0063] In one embodiment, the uops schedulers 602, 604, 606, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor 600, the processor 600 also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

[0064] The processor 600 also includes logic to implement store address prediction for memory disambiguation according to embodiments of the disclosure. In one embodiment, the execution block 611 of processor 600 may include a store address predictor (not shown) for implementing store address prediction for memory disambiguation. [0065] The term "registers" may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective).

However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be

implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store thirty-two bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data.

[0066] For the discussions below, the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMXTM registers (also referred to as 'mm' registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as "SSEx") technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

[0067] Referring now to Figure 7, shown is a block diagram illustrating a system 700 in which an embodiment of the disclosure may be used. As shown in Figure 7,

multiprocessor system 700 is a point-to-point interconnect system, and includes a first processor 770 and a second processor 780 coupled via a point-to-point interconnect 750. While shown with only two processors 770, 780, it is to be understood that embodiments of the disclosure are not so limited. In other embodiments, one or more additional processors may be present in a given processor. .

[0068] Processors 770 and 780 are shown including integrated memory controller units 772 and 782, respectively. Processor 770 also includes as part of its bus controller units point-to-point (P-P) interfaces 776 and 778; similarly, second processor 780 includes P-P interfaces 786 and 788. Processors 770, 780 may exchange information via a point-to-point (P-P) interface 750 using P-P interface circuits 778, 788. As shown in Figure 7, IMCs 772 and 782 couple the processors to respective memories, namely a memory 732 and a memory 734, which may be portions of main memory locally attached to the respective processors.

[0069] Processors 770, 780 may each exchange information with a chipset 790 via individual P-P interfaces 752, 754 using point to point interface circuits 776, 794, 786, 798. Chipset 790 may also exchange information with a high-performance graphics circuit 738 via a high-performance graphics interface 739.

[0070] A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

[0071] Chipset 790 may be coupled to a first bus 716 via an interface 796. In one embodiment, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

[0072] As shown in Figure 7, various I/O devices 714 may be coupled to first bus

716, along with a bus bridge 718 which couples first bus 716 to a second bus 720. In one embodiment, second bus 720 may be a low pin count (LPC) bus. Various devices may be coupled to second bus 720 including, for example, a keyboard and/or mouse 722,

communication devices 727 and a storage unit 728 such as a disk drive or other mass storage device which may include instructions/code and data 730, in one embodiment. Further, an audio I/O 724 may be coupled to second bus 720. Note that other architectures are possible. For example, instead of the point-to-point architecture of Figure 7, a system may implement a multi-drop bus or other such architecture.

[0073] Referring now to Figure 8, shown is a block diagram of a system 800 in which one embodiment of the disclosure may operate. The system 800 may include one or more processors 810, 815, which are coupled to graphics memory controller hub (GMCH) 820. The optional nature of additional processors 815 is denoted in Figure 8 with broken lines.

[0074] Each processor 810, 815 may be some version of the circuit, integrated circuit, processor, and/or silicon integrated circuit as described above. However, it should be noted that it is unlikely that integrated graphics logic and integrated memory control units would exist in the processors 810, 815. Figure 8 illustrates that the GMCH 820 may be coupled to a memory 840 that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non- volatile cache. [0075] The GMCH 820 may be a chipset, or a portion of a chipset. The GMCH 820 may communicate with the processor(s) 810, 815 and control interaction between the processor(s) 810, 815 and memory 840. The GMCH 820 may also act as an accelerated bus interface between the processor(s) 810, 815 and other elements of the system 800. For at least one embodiment, the GMCH 820 communicates with the processor(s) 810, 815 via a multi-drop bus, such as a frontside bus (FSB) 895.

[0076] Furthermore, GMCH 820 is coupled to a display 845 (such as a flat panel or touchscreen display). GMCH 820 may include an integrated graphics accelerator. GMCH 820 is further coupled to an input/output (I/O) controller hub (ICH) 850, which may be used to couple various peripheral devices to system 800. Shown for example in the embodiment of Figure 8 is an external graphics device 860, which may be a discrete graphics device, coupled to ICH 850, along with another peripheral device 870.

[0077] Alternatively, additional or different processors may also be present in the system

800. For example, additional processor(s) 815 may include additional processors(s) that are the same as processor 810, additional processor(s) that are heterogeneous or asymmetric to processor 810, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There can be a variety of differences between the processor(s) 810, 815 in terms of a spectrum of metrics of merit including

architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processors 810, 815. For at least one embodiment, the various processors 810, 815 may reside in the same die package.

[0078] Referring now to Figure 9, shown is a block diagram of a system 900 in which an embodiment of the disclosure may operate. Figure 9 illustrates processors 970, 980. Processors 970, 980 may include integrated memory and I/O control logic ("CL") 972 and 982, respectively and intercommunicate with each other via point-to-point interconnect 950 between point-to-point (P-P) interfaces 978 and 988 respectively. Processors 970, 980 each communicate with chipset 990 via point-to-point interconnects 952 and 954 through the respective P-P interfaces 976 to 994 and 986 to 998 as shown. For at least one embodiment, the CL 972, 982 may include integrated memory controller units. CLs 972, 982 may include I/O control logic. As depicted, memories 932, 934 coupled to CLs 972, 982 and I/O devices 914 are also coupled to the control logic 972, 982. Legacy I/O devices 915 are coupled to the chipset 990 via interface 996.

[0079] Embodiments may be implemented in many different system types. Figure 10 is a block diagram of a SoC 1000 in accordance with an embodiment of the present disclosure.

Dashed lined boxes are optional features on more advanced SoCs. In Figure 10, an interconnect unit(s) 1012 is coupled to: an application processor 1020 which includes a set of one or more cores 1002A-N and shared cache unit(s) 1006; a system agent unit 1010; a bus controller unit(s) 1016; an integrated memory controller unit(s) 1014; a set or one or more media processors 1018 which may include integrated graphics logic 1008, an image processor 1024 for providing still and/or video camera functionality, an audio processor 1026 for providing hardware audio acceleration, and a video processor 1028 for providing video encode/decode acceleration; an static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, a memory module may be included in the integrated memory controller unit(s) 1014. In another

embodiment, the memory module may be included in one or more other components of the SoC 1000 that may be used to access and/or control a memory.

[0080] The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 1006, and external memory (not shown) coupled to the set of integrated memory controller units 1014. The set of shared cache units 1006 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last-level cache (LLC), and/or combinations thereof.

[0081] In some embodiments, one or more of the cores 1002A-N are capable of multithreading. The system agent 1010 includes those components coordinating and operating cores 1002A-N. The system agent unit 1010 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1002A-N and the integrated graphics logic 1008. The display unit is for driving one or more externally connected displays.

[0082] The cores 1002A-N may be homogenous or heterogeneous in terms of architecture and/or instruction set. For example, some of the cores 1002A-N may be in order while others are out-of-order. As another example, two or more of the cores 1002A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

[0083] The application processor 1020 may be a general-purpose processor, such as a

Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, Atom™ or Quark™ processor, which are available from Intel™ Corporation, of Santa Clara, Calif. Alternatively, the application processor 1020 may be from another company, such as ARM Holdings™, Ltd, MIPS™, etc. The application processor 1020 may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor 1020 may be implemented on one or more chips. The application processor 1020 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0084] Figure 11 is a block diagram of an embodiment of a system on-chip (SoC) design in accordance with the present disclosure. As a specific illustrative example, SoC 1100 is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

[0085] Here, SOC 1100 includes 2 cores— 1106 and 1107. Cores 1106 and 1107 may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MlPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores 1106 and 1107 are coupled to cache control 1108 that is associated with bus interface unit 1109 and L2 cache 1110 to communicate with other parts of system 1100. Interconnect 1110 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described disclosure.

[0086] Interconnect 1110 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 1130 to interface with a SIM card, a boot ROM 1135 to hold boot code for execution by cores 1106 and 1107 to initialize and boot SoC 1100, a SDRAM controller 1140 to interface with external memory (e.g. DRAM 1160), a flash controller 1145 to interface with non-volatile memory (e.g. Flash 1165), a peripheral control 1150 (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs 1120 and Video interface 1125 to display and receive input (e.g. touch enabled input), GPU 1115 to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the disclosure described herein. In addition, the system 1100 illustrates peripherals for communication, such as a Bluetooth module 1170, 3G modem 1175, GPS 1180, and Wi-Fi 1185.

[0087] Figure 12 illustrates a diagrammatic representation of a machine in the example form of a computer system 1200 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed.

In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0088] The computer system 1200 includes a processing device 1202, a main memory

1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1218, which communicate with each other via a bus 1230.

[0089] Processing device 1202 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1202 may also be one or more special- purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device 1202 may include one or processing cores. The processing device 1202 is configured to execute the processing logic 1226 for performing the operations and steps discussed herein.

[090] The computer system 1200 may further include a network interface device

1208 communicably coupled to a network 1220. The computer system 1200 also may include a video display unit 1210 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and a signal generation device 1216 (e.g., a speaker). Furthermore, computer system 1200 may include a graphics processing unit 1222, a video processing unit 1228, and an audio processing unit 1232. [091] The data storage device 1218 may include a machine-accessible storage medium 1224 on which is stored software 1226 implementing any one or more of the methodologies of functions described herein, such as implementing store address prediction for memory disambiguation as described above. The software 1226 may also reside, completely or at least partially, within the main memory 1204 as instructions 1226 and/or within the processing device 1202 as processing logic 1226 during execution thereof by the computer system 1200; the main memory 1204 and the processing device 1202 also constituting machine-accessible storage media.

[092] The machine-readable storage medium 1224 may also be used to store instructions 1226 implementing store address prediction and/or a software library containing methods that call the above applications. While the machine-accessible storage medium 1128 is shown in an example embodiment to be a single medium, the term "machine-accessible storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-accessible storage medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instruction for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-accessible storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

[093] The following examples pertain to further embodiments. Example 1 is a processor includes a processing core and a caching circuit, communicatively coupled to the processing core, comprising a dead block predictor (DBP) to predict that a cache line in a last- level cache (LLC) is not to be accessed until an eviction from the LLC, wherein responsive to predicting that the cache line is not to be accessed until the eviction, the caching circuit is to issue an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line.

[094] In Example 2, the subject matter of Example 1 further provides that the memory controller comprises a memory-side cache (MSC) tracking circuit to receive the evict message, responsive to detecting the DBP status in the evict message, create, in an MSC, an MSC entry in an MSC to store a payload and a memory location identified by a memory address to store the payload, initiate a counter associated with the MSC entry to a limit value, and responsive to detecting occurrence of a trigger event associated with the limit value, evict the MSC entry to the memory location of a far memory. [095] In Example 3, the subject matter of any of Examples 1 and 2 further provides that the memory controller is to receive a second evict message comprising the flag indicating a non-DBP status and create a second MSC entry that is not associated with a time limit.

[096] In Example 4, the subject matter of any of Examples 1 and 2 further provides that the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

[097] In Example 5, the subject matter of Example 4 further provides that the MSC tracking circuit is to, responsive to determining that a life time of the MSC entry reaches the maximum life time, evict the MSC entry to the far memory.

[098] In Example 6, the subject matter of Example 4 further provides that the MSC tracking circuit is to, responsive to determining that the life time of the MSC entry reaches the maximum life time, determine whether a further trigger event occurs, and responsive to detecting occurrence of the further event, evict the MSC entry to the far memory.

[099] In Example 6, the subject matter of Example 5 further provides that the MSC tracking circuit is to, responsive to determining that the life time of the MSC entry reaches the maximum life time, determine whether a further trigger event occurs, and responsive to detecting occurrence of the further event, evict the MSC entry to the far memory.

[0100] In Example 7, the subject matter of Example 4 further provides that the maximum life time is a maximum number of processor clock cycles that is set by an application executing on the processor.

[0101] Example 9 is a system-on-a-chip (SoC) comprising a multi-level memory system comprising a memory-side cache (MSC) and a far memory; and a processor, communicatively coupled to the multi-level memory system, comprising a processing core, and a caching circuit, communicatively coupled to the processing core, comprising a dead block predictor (DBP) to predict that a cache line in a last-level cache (LLC) is not to be accessed until an eviction from the LLC, wherein responsive to predicting that the cache line is not to be accessed until the eviction, the caching circuit is to issue an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line.

[0102] In Example 10, the subject matter of Example 9 further provides that the memory controller further comprises a memory-side cache (MSC) tracking circuit to receive the evict message, responsive to detecting the DBP status in the evict message, create, in the

MSC, an MSC entry to store a payload and a memory location identified by a memory address to store the payload, initiate a counter associated with the MSC entry to a limit value, and responsive to detecting occurrence of a trigger event associated with the limit value, evict the MSC entry to the memory location of the far memory.

[0103] In Example 11, the subject matter of any of Examples 9 and 10 further provides that the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

[0104] In Example 12, the subject matter of Example 11 further provides that the

MSC tracking circuit is to, responsive to determining that a life time of the MSC entry reaches the maximum life time, evict the MSC entry to the far memory.

[0105] In Example 13, the subject matter of Example 11 further provides that the

MSC tracking circuit is to, responsive to determining that the life time of the MSC entry reaches the maximum life time, determine whether a further trigger event occurs, and responsive to detecting occurrence of the further event, evict the MSC entry to the far memory.

[0106] In Example 14, the subject matter of Example 13 further provides that the further event is that a number of egress requests on an interconnect communicatively coupled to the processing core, the caching circuit, and the memory controller is smaller than a threshold value.

[0107] In Example 15, the subject matter of Example 11 further provides that the maximum life time is a maximum number of processor clock cycles that is set by an application executing on the processor.

[0108] Example 16 is a method comprising determining, by a dead block predictor

(DBP) of a caching circuit, that a cache line of a last-level cache (LLC) is a dead block, generating, by the caching circuit, an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line, and transmitting, by the caching circuit, the evict message to a memory-side cache (MSC) tracking circuit in the memory controller.

[0109] In Example 17, the subject matter of Example 16 further provides that the

MSC tracking circuit is further to receive the evict message, responsive to detecting the DBP status in the evict message, create, in an MSC, an MSC entry to store a payload and a memory location identified by a memory address to store the payload, initiate a counter associated with the MSC entry to a limit value, and responsive to detecting occurrence of a trigger event associated with the limit value, evict the MSC entry to the memory location of a far memory. [0110] In Example 18, the subject matter of Example 17 further provides that the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

[0111] Example 19 is an apparatus comprising: means for performing the method of any of Examples 16 to 18.

[0112] Example 20 is a machine-readable non-transitory medium having stored thereon program code that, when executed, perform operations comprising determining, by a dead block predictor (DBP) of a caching circuit, that a cache line of a last-level cache (LLC) is a dead block, generating, by the caching circuit, an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line, and

transmitting, by the caching circuit, the evict message to a memory-side cache (MSC) tracking circuit of the memory controller.

[0113] In Example 21 , the subject matter of Example 20 further provides that the

MSC track circuit is further to receive the evict message, responsive to detecting the DBP status in the evict message, create, in an MSC, an MSC entry to store a payload and a memory location identified by a memory address to store the payload, initiate a counter associated with the MSC entry to a limit value, and responsive to detecting occurrence of a trigger event associated with the limit value, evict the MSC entry to the memory location of a far memory.

[0114] In Example 22, the subject matter of any of Examples 20 and 21 further provides that the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

[0115] While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations there from. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this disclosure.

[0116] A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners.

First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

[0117] A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the microcontroller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non- transitory medium. Furthermore, in another embodiment, use of a module refers to the non- transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0118] Use of the phrase 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

[0119] Furthermore, use of the phrases 'to,' 'capable of/to,' and or 'operable to,' in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

[0120] A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1 's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of 910 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

[0121] Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

[0122] The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine- accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

[0123] Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD- ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0124] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0125] In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Furthermore, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.

Claims

CLAIMS What is claimed is:

1. A processor comprising:

a processing core; and

a caching circuit, communicatively coupled to the processing core, comprising a dead block predictor (DBP) to predict that a cache line in a last-level cache (LLC) is not to be accessed until an eviction from the LLC, wherein responsive to predicting that the cache line is not to be accessed until the eviction, the caching circuit is to issue an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line.

2. The processor of claim 1, wherein the memory controller comprises a memory-side cache (MSC) tracking circuit to:

receive the evict message;

responsive to detecting the DBP status in the evict message, create, in an MSC, an MSC entry in an MSC to store a payload and a memory location identified by a memory address to store the payload;

initiate a counter associated with the MSC entry to a limit value; and

responsive to detecting occurrence of a trigger event associated with the limit value, evict the MSC entry to the memory location of a far memory.

3. The processor of any of claims 1 and 2, wherein the memory controller is to:

receive a second evict message comprising the flag indicating a non-DBP status; and create a second MSC entry that is not associated with a time limit.

4. The processor of any of claims 1 and 2, wherein the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

5. The processor of claim 4, wherein the MSC tracking circuit is to, responsive to determining that a life time of the MSC entry reaches the maximum life time, evict the MSC entry to the far memory.

6. The processor of claim 4, wherein the MSC tracking circuit is to, responsive to determining that the life time of the MSC entry reaches the maximum life time, determine whether a further trigger event occurs, and responsive to detecting occurrence of the further event, evict the MSC entry to the far memory.

7. The processor of claim 6, wherein the further event is that a number of egress requests on an interconnect communicatively coupled to the processing core, the caching circuit, and the memory controller is smaller than a threshold value.

8. The processor of claim 4, wherein the maximum life time is a maximum number of processor clock cycles that is set by an application executing on the processor.

9. A system-on-a-chip (SoC) comprising:

a multi-level memory system comprising a memory-side cache (MSC) and a far memory;

a processor, communicatively coupled to the multi-level memory system, comprising: a processing core; and

10. The SoC of claim 9, wherein the memory controller further comprises a memory-side cache (MSC) tracking circuit to:

receive the evict message;

responsive to detecting the DBP status in the evict message, create, in the MSC, an MSC entry to store a payload and a memory location identified by a memory address to store the payload;

initiate a counter associated with the MSC entry to a limit value; and

responsive to detecting occurrence of a trigger event associated with the limit value, evict the MSC entry to the memory location of the far memory.

11. The SoC of any of claims 9 and 10, wherein the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

12. The SoC of claim 11, wherein the MSC tracking circuit is to, responsive to

determining that a life time of the MSC entry reaches the maximum life time, evict the MSC entry to the far memory.

13. The SoC of claim 11, wherein the MSC tracking circuit is to, responsive to

determining that the life time of the MSC entry reaches the maximum life time, determine whether a further trigger event occurs, and responsive to detecting occurrence of the further event, evict the MSC entry to the far memory.

14. The SoC of claim 13, wherein the further event is that a number of egress requests on an interconnect communicatively coupled to the processing core, the caching circuit, and the memory controller is smaller than a threshold value.

15. The SoC of claim 11, wherein the maximum life time is a maximum number of processor clock cycles that is set by an application executing on the processor.

16. A method comprising :

determining, by a dead block predictor (DBP) of a caching circuit, that a cache line of a last-level cache (LLC) is a dead block;

generating, by the caching circuit, an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line; and

transmitting, by the caching circuit, the evict message to a memory-side cache (MSC) tracking circuit in the memory controller.

17. The method of claim 16, wherein the MSC tracking circuit is further to:

receive the evict message;

responsive to detecting the DBP status in the evict message, create, in an MSC, an MSC entry to store a payload and a memory location identified by a memory address to store the payload;

initiate a counter associated with the MSC entry to a limit value; and

18. The method of claim 17, wherein the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.

19. An apparatus comprising: means for performing the method of any of claims 16 to 18.

20. A machine-readable non-transitory medium having stored thereon program code that, when executed, perform operations comprising:

21. The machine-readable non-transitory medium of claim 20, wherein the MSC track circuit is further to:

receive the evict message;

initiate a counter associated with the MSC entry to a limit value; and

22. The machine-readable non-transitory medium of any of claims 20 and 21, wherein the limit value is a time limit that indicates a maximum life time for the MSC entry before the MSC entry is evicted to the far memory.