JP2016504757A - ウェハレベルパッケージされた回路デバイスのための集積型接合ラインスペーサ - Google Patents
ウェハレベルパッケージされた回路デバイスのための集積型接合ラインスペーサ Download PDFInfo
- Publication number
- JP2016504757A JP2016504757A JP2015541791A JP2015541791A JP2016504757A JP 2016504757 A JP2016504757 A JP 2016504757A JP 2015541791 A JP2015541791 A JP 2015541791A JP 2015541791 A JP2015541791 A JP 2015541791A JP 2016504757 A JP2016504757 A JP 2016504757A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wafer
- solder metal
- metal stack
- cap wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0035—Packages or encapsulation for maintaining a controlled atmosphere inside of the chamber containing the MEMS
- B81B7/0041—Packages or encapsulation for maintaining a controlled atmosphere inside of the chamber containing the MEMS maintaining a controlled atmosphere with techniques not provided for in B81B7/0038
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0172—Seals
- B81C2203/019—Seals characterised by the material or arrangement of seals between parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2746—Plating
- H01L2224/27462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2746—Plating
- H01L2224/27464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/83139—Guiding structures on the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8314—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/83141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Micromachines (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims (26)
- ウェハレベルパッケージされた回路デバイスを形成する方法であって、
デバイスウェハを形成するステップを含み、当該デバイスウェハが、当該デバイスウェハの基板の第1の領域に残された第1の1以上の材料層の群を含み、前記方法が、さらに、
前記デバイスウェハに取り付けられるように構成されたキャップウェハを形成するステップを含み、当該キャップウェハが、当該キャップウェハの基板の第2の領域に残された第2の1以上の材料層の群を含み、
前記デバイスウェハと前記キャップウェハとを接合した時に、前記第1の1以上の材料層の群と前記第2の1以上の材料層の群との結合層により、集積型接合ギャップ調整構造が画定される、前記方法。 - 前記第1の1以上の材料層の群が、前記デバイスウェハのための集積回路及びシールリングの1以上を形成するために用いられる材料であり、
前記第2の1以上の材料層の群が、前記キャップウェハのための反射防止コーティング及びシールリングの1以上を形成するために用いられる材料である、請求項1に記載の方法。 - 前記第1の1以上の材料層の群が、さらに、
前記デバイスウェハの前記基板上に形成されたポリイミド層と、
前記ポリイミド層上に形成されたはんだ金属スタック層とを含む、請求項2に記載の方法。 - 前記はんだ金属スタック層が、チタン/ニッケル/金スタック層を含む、請求項3に記載の方法。
- 前記第2の1以上の材料層の群が、さらに、
前記デバイスウェハの前記基板上に形成された反射防止コーティング層と、
前記反射防止コーティング層上に形成されたはんだ金属スタック層とを含む、請求項2に記載の方法。 - 前記はんだ金属スタック層が、チタン/ニッケル/金スタック層を含む、請求項5に記載の方法。
- 前記第2の1以上の材料層の群が、さらに、前記はんだ金属層スタック層の上に形成された真空ゲッタ層を含む、請求項5に記載の方法。
- 前記真空ゲッタ層が、チタン、ジルコニウム、鉄、及びバナジウムの1以上を含む、請求項7に記載の方法。
- さらに、前記キャップウェハを前記デバイスウェハに接合することで、前記集積型接合ギャップ調整構造(BGCS)が確定されるステップを含む、請求項1に記載の方法。
- 前記集積型BGCSが約10ミクロン(μm)の厚さを有する、請求項9に記載の方法。
- 前記第1の領域が前記デバイスウェハのスクライブ領域に対応し、且つ、前記第2の領域が前記キャップウェハのスクライブ領域に対応している、請求項1に記載の方法。
- ウェハレベルパッケージされた回路デバイスを形成する方法であって、
デバイスウェハを形成するステップを含み、当該デバイスウェハが、当該デバイスウェハの基板の第1の領域に形成されたポリイミド層と、前記ポリイミド層上に形成された第1のはんだ金属スタック層とを含み、前記ポリイミド層が、前記デバイスウェハ上の集積回路の微小電気機械システム(MEMS)の形成においても用いられたポリイミド層と同一のポリイミド層であり、前記第1のはんだ金属スタック層もまた、前記デバイスウェハのためのシールリングを形成するために用いられた第1のはんだ金属スタック層と同一の第1のはんだ金属スタック層であり、前記方法が、さらに、
キャップウェハを形成するステップを含み、当該キャップウェハが、当該キャップウェハの基板の第2の領域に形成された反射防止コーティング層と、前記反射防止コーティング層上に形成された第2のはんだ金属スタック層とを含み、前記反射防止コーティング層が、前記キャップウェハのキャビティ部上にも形成された反射防止コーティング層と同一の反射防止コーティング層であり、前記第2のはんだ金属スタック層もまた、前記キャップウェハのためのシールリングを形成するために用いられた第2のはんだ金属スタック層と同一の第2のはんだ金属スタック層であり、前記方法が、さらに、
前記キャップウェハが前記デバイスウェハに接合され、それにより、前記ポリイミド層、前記第1のはんだ金属スタック層、前記第2のはんだ金属スタック層、及び、前記反射防止コーティング層を含む集積型接合ギャップ調整構造が画定されるステップを含む、前記方法。 - 前記キャップウェハを形成するステップが、さらに、真空ゲッタ層を前記第2のはんだ金属スタック層上に形成するステップを含み、前記真空ゲッタ層が、前記キャップウェハの前記キャビティ部の前記反射防止コーティング層上にも形成された真空ゲッタ層と同一の真空ゲッタ層であり、
前記集積型接合ギャップ調整構造が、前記ポリイミド層、前記第1のはんだ金属スタック層、前記真空ゲッタ層、前記第2のはんだ金属スタック層、及び、前記反射防止コーティング層を含む、請求項12に記載の方法。 - 前記第1の及びはんだ金属スタック層が、チタン/ニッケル/金スタック層を含む、請求項13に記載の方法。
- 前記集積型接合ギャップ調整構造が約10ミクロン(μm)の厚さを有する、請求項13に記載の方法。
- 前記ポリイミド層が約1.0ミクロン(μm)〜約2.0μmの厚さを有し、
前記第1のはんだ金属スタック層が約0.4μm〜約0.8μmの厚さを有し、
前記真空ゲッタ層が約0.3μm〜約2.0μmの厚さを有し、
前記第2のはんだ金属スタック層が約0.4μm〜約0.8μmの厚さを有し、
前記反射防止コーティング層が約5.5μm〜約8.0μmの厚さを有する、請求項13に記載の方法。 - 前記第1の領域が前記デバイスウェハのスクライブ領域に対応し、且つ、前記第2の領域が前記キャップウェハのスクライブ領域に対応している、請求項12に記載の方法。
- ウェハレベルパッケージされた回路デバイスであって、
キャップウェハに接合されたデバイスウェハを備え、
前記デバイスウェハが、前記デバイスウェハの基板の第1の領域に形成されたポリイミド層と、前記ポリイミド層上に形成された第1のはんだ金属スタック層とを含み、前記ポリイミド層が、前記デバイスウェハ上の集積回路の形成においても用いられたポリイミド層と同一のポリイミド層であり、且つ、前記第1のはんだ金属スタック層もまた、前記デバイスウェハのためのシールリングを形成するために用いられた第1のはんだ金属スタック層と同一の第1のはんだ金属スタック層であり、
前記キャップウェハが、前記キャップウェハの基板の第2の領域に形成された反射防止コーティング層と、前記反射防止コーティング層上に形成された第2のはんだ金属スタック層とを含み、前記反射防止コーティング層が、前記キャップウェハのキャビティ部上にも形成された反射防止コーティング層と同一の反射防止コーティング層であり、且つ、前記第2のはんだ金属スタック層もまた、前記キャップウェハのためのシールリングを形成するために用いられた第2のはんだ金属スタック層と同一の第2のはんだ金属スタック層であり、前記回路デバイスが、さらに、
前記デバイスウェハと前記キャップウェハとの間に配置された、集積型接合ギャップ調整構造(BGCS)を備え、前記集積型BGCSが、前記ポリイミド層、前記第1のはんだ金属スタック層、前記第2のはんだ金属スタック層、及び、前記反射防止コーティング層を含む、前記回路デバイス。 - 前記キャップウェハが、さらに、前記第2のはんだ金属スタック層上に形成された真空ゲッタ層を含み、前記真空ゲッタ層が、前記キャップウェハの前記キャビティ部の前記反射防止コーティング層上にも形成された真空ゲッタ層と同一の真空ゲッタ層であり、
前記集積型接合ギャップ調整構造が、前記ポリイミド層、前記第1のはんだ金属スタック層、前記真空ゲッタ層、前記第2のはんだ金属スタック層、及び、前記反射防止コーティング層を含む、請求項18に記載の装置。 - 前記第1の及びはんだ金属スタック層が、チタン/ニッケル/金スタック層を含む、請求項18に記載の装置。
- 前記集積型接合ギャップ調整構造が約10ミクロン(μm)の厚さを有する、請求項18に記載の装置。
- 前記ポリイミド層が約1.0ミクロン(μm)〜約2.0μmの厚さを有し、
前記第1のはんだ金属スタック層が約0.4μm〜約0.8μmの厚さを有し、
前記真空ゲッタ層が約0.3μm〜約2.0μmの厚さを有し、
前記第2のはんだ金属スタック層が約0.4μm〜約0.8μmの厚さを有し、
前記反射防止コーティング層が約5.5μm〜約8.0μmの厚さを有する、請求項18に記載の装置。 - 前記第1の領域が前記デバイスウェハのスクライブ領域に対応し、且つ、前記第2の領域が前記キャップウェハのスクライブ領域に対応している、請求項18に記載の装置。
- ウェハレベルパッケージされた回路デバイスを形成する方法であって、
デバイスウェハを形成するステップと、
キャップウェハを形成するステップと、
前記キャップウェハ又は前記デバイスウェハのいずれかの上に、前記キャップウェハ又は前記デバイスウェハのいずれかの形成において用いられ、且つ前記キャップウェハ又は前記デバイスウェハのいずれかの基板の所定領域に残された1以上の材料層を含む接合ギャップ調整構造を形成するステップと、
前記キャップウェハを前記デバイスウェハに接合するステップとを含む、前記方法。 - 前記接合ギャップ調整構造が前記キャップ層上に形成され、さらに、真空ゲッタ層、はんだ金属スタック層、及び、反射防止コーティング層の1以上を含む、請求項24に記載の方法。
- 前記接合ギャップ調整構造が前記ウェハ層上に形成され、さらに、はんだ金属スタック層、及び、ポリイミド層の1以上を含む、請求項24に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/667,458 | 2012-11-02 | ||
US13/667,458 US8736045B1 (en) | 2012-11-02 | 2012-11-02 | Integrated bondline spacers for wafer level packaged circuit devices |
PCT/US2013/066266 WO2014070534A2 (en) | 2012-11-02 | 2013-10-23 | Integrated bondline spacers for wafer level packaged circuit devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016504757A true JP2016504757A (ja) | 2016-02-12 |
JP6412009B2 JP6412009B2 (ja) | 2018-10-24 |
Family
ID=50621587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015541791A Expired - Fee Related JP6412009B2 (ja) | 2012-11-02 | 2013-10-23 | ウェハレベルパッケージされた回路デバイスのための集積型接合ラインスペーサ |
Country Status (8)
Country | Link |
---|---|
US (3) | US8736045B1 (ja) |
EP (2) | EP3340294A1 (ja) |
JP (1) | JP6412009B2 (ja) |
KR (1) | KR102164880B1 (ja) |
CA (1) | CA2889975C (ja) |
IL (2) | IL238325A0 (ja) |
NO (1) | NO2994775T3 (ja) |
WO (1) | WO2014070534A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019208072A (ja) * | 2015-10-20 | 2019-12-05 | レイセオン カンパニー | パッケージ圧力を低下させるための外部ゲッターの使用 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8736045B1 (en) * | 2012-11-02 | 2014-05-27 | Raytheon Company | Integrated bondline spacers for wafer level packaged circuit devices |
US9673169B2 (en) | 2013-02-05 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for a wafer seal ring |
US9287188B2 (en) * | 2013-02-05 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for a seal ring structure |
US9540231B2 (en) * | 2014-01-28 | 2017-01-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | MEMS device with a bonding layer embedded in the cap |
CN104851848A (zh) * | 2014-02-17 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | 一种c-sam中接合晶圆的密封结构及其制备方法 |
US9688529B2 (en) * | 2014-06-10 | 2017-06-27 | Qorvo Us, Inc. | Glass wafer assembly |
US9334154B2 (en) | 2014-08-11 | 2016-05-10 | Raytheon Company | Hermetically sealed package having stress reducing layer |
US9637372B2 (en) | 2015-04-27 | 2017-05-02 | Nxp Usa, Inc. | Bonded wafer structure having cavities with low pressure and method for forming |
US9771258B2 (en) * | 2015-06-24 | 2017-09-26 | Raytheon Company | Wafer level MEMS package including dual seal ring |
US20170081178A1 (en) * | 2015-09-22 | 2017-03-23 | Freescale Semiconductor, Inc. | Semiconductor device package with seal structure |
DE102015224519A1 (de) * | 2015-12-08 | 2017-06-08 | Robert Bosch Gmbh | MEMS-Bauteil mit zwei unterschiedlichen Innendrücken |
CN105731355B (zh) * | 2016-04-29 | 2017-05-31 | 合肥芯福传感器技术有限公司 | 一体化多功能陶瓷封装管壳 |
US10950567B2 (en) * | 2017-03-29 | 2021-03-16 | Mitsubishi Electric Corporation | Hollow sealed device and manufacturing method therefor |
CN107055456A (zh) * | 2017-04-14 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | 微机电系统器件的封装结构及方法 |
CN107572474B (zh) * | 2017-08-22 | 2019-04-12 | 华中科技大学 | 一种封装间距可高精度控制的mems封装结构的封装方法 |
CN109879240B (zh) * | 2017-12-06 | 2021-11-09 | 有研工程技术研究院有限公司 | 一种厚膜吸气材料的制备方法 |
CN113603053B (zh) * | 2018-01-23 | 2024-01-23 | 苏州明皜传感科技股份有限公司 | 微机电系统装置 |
US10830787B2 (en) * | 2018-02-20 | 2020-11-10 | General Electric Company | Optical accelerometers for use in navigation grade environments |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010017805A (ja) * | 2008-07-09 | 2010-01-28 | Tohoku Univ | 機能デバイス及びその製造方法 |
JP2012104815A (ja) * | 2010-11-05 | 2012-05-31 | Raytheon Co | ディスポーザブル接合ギャップ制御構造 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5232962A (en) | 1991-10-09 | 1993-08-03 | Quantum Materials, Inc. | Adhesive bonding composition with bond line limiting spacer system |
US6521477B1 (en) | 2000-02-02 | 2003-02-18 | Raytheon Company | Vacuum package fabrication of integrated circuit components |
US20020179921A1 (en) * | 2001-06-02 | 2002-12-05 | Cohn Michael B. | Compliant hermetic package |
US7952189B2 (en) * | 2004-05-27 | 2011-05-31 | Chang-Feng Wan | Hermetic packaging and method of manufacture and use therefore |
US7576427B2 (en) | 2004-05-28 | 2009-08-18 | Stellar Micro Devices | Cold weld hermetic MEMS package and method of manufacture |
US7442570B2 (en) * | 2005-03-18 | 2008-10-28 | Invensence Inc. | Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom |
US20070190747A1 (en) * | 2006-01-23 | 2007-08-16 | Tessera Technologies Hungary Kft. | Wafer level packaging to lidded chips |
US20120132522A1 (en) | 2007-07-19 | 2012-05-31 | Innovative Micro Technology | Deposition/bonding chamber for encapsulated microdevices and method of use |
US20090266480A1 (en) | 2008-04-29 | 2009-10-29 | International Business Machines Corporation | Process for Preparing a Solder Stand-Off |
DE102008042106A1 (de) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Verkapselung, MEMS sowie Verfahren zum Verkapseln |
US8644125B2 (en) * | 2008-09-30 | 2014-02-04 | Intel Corporation | Seek scan probe (SSP) cantilever to mover wafer bond stop |
TWI511243B (zh) | 2009-12-31 | 2015-12-01 | Xintec Inc | 晶片封裝體及其製造方法 |
US8809784B2 (en) | 2010-10-21 | 2014-08-19 | Raytheon Company | Incident radiation detector packaging |
US8736045B1 (en) | 2012-11-02 | 2014-05-27 | Raytheon Company | Integrated bondline spacers for wafer level packaged circuit devices |
-
2012
- 2012-11-02 US US13/667,458 patent/US8736045B1/en active Active
-
2013
- 2013-10-23 JP JP2015541791A patent/JP6412009B2/ja not_active Expired - Fee Related
- 2013-10-23 EP EP18155856.0A patent/EP3340294A1/en active Pending
- 2013-10-23 CA CA2889975A patent/CA2889975C/en active Active
- 2013-10-23 WO PCT/US2013/066266 patent/WO2014070534A2/en active Application Filing
- 2013-10-23 EP EP13850327.1A patent/EP2915190B1/en active Active
- 2013-10-23 KR KR1020157014027A patent/KR102164880B1/ko active IP Right Grant
-
2014
- 2014-03-10 US US14/202,756 patent/US9187312B2/en active Active
- 2014-05-07 NO NO14726898A patent/NO2994775T3/no unknown
- 2014-08-11 US US14/456,156 patent/US9174836B2/en active Active
-
2015
- 2015-04-16 IL IL238325A patent/IL238325A0/en active IP Right Grant
-
2018
- 2018-08-26 IL IL261373A patent/IL261373B/en active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010017805A (ja) * | 2008-07-09 | 2010-01-28 | Tohoku Univ | 機能デバイス及びその製造方法 |
JP2012104815A (ja) * | 2010-11-05 | 2012-05-31 | Raytheon Co | ディスポーザブル接合ギャップ制御構造 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019208072A (ja) * | 2015-10-20 | 2019-12-05 | レイセオン カンパニー | パッケージ圧力を低下させるための外部ゲッターの使用 |
Also Published As
Publication number | Publication date |
---|---|
KR102164880B1 (ko) | 2020-10-13 |
IL261373B (en) | 2021-04-29 |
IL261373A (en) | 2018-10-31 |
US8736045B1 (en) | 2014-05-27 |
CA2889975A1 (en) | 2014-05-08 |
CA2889975C (en) | 2022-01-04 |
NO2994775T3 (ja) | 2018-02-03 |
US9174836B2 (en) | 2015-11-03 |
EP2915190A4 (en) | 2016-09-14 |
US20140124899A1 (en) | 2014-05-08 |
US20140346643A1 (en) | 2014-11-27 |
EP2915190B1 (en) | 2018-03-07 |
IL238325A0 (en) | 2015-06-30 |
KR20150082363A (ko) | 2015-07-15 |
US9187312B2 (en) | 2015-11-17 |
WO2014070534A3 (en) | 2015-07-16 |
JP6412009B2 (ja) | 2018-10-24 |
WO2014070534A2 (en) | 2014-05-08 |
US20140193948A1 (en) | 2014-07-10 |
EP2915190A2 (en) | 2015-09-09 |
EP3340294A1 (en) | 2018-06-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6412009B2 (ja) | ウェハレベルパッケージされた回路デバイスのための集積型接合ラインスペーサ | |
US6521477B1 (en) | Vacuum package fabrication of integrated circuit components | |
US6479320B1 (en) | Vacuum package fabrication of microelectromechanical system devices with integrated circuit components | |
US7943411B2 (en) | Apparatus and method of wafer bonding using compatible alloy | |
US7485956B2 (en) | Microelectronic package optionally having differing cover and device thermal expansivities | |
EP1272422A2 (en) | Vacuum package fabrication of microelectromechanical system devices with integrated circuit components | |
IL243086A (en) | Packing solder barrier at the level of the analyzer for use as a vacuum generator | |
CN106098625B (zh) | 等离子划片的芯片包封结构及制作方法 | |
JP2005167209A (ja) | デバイスの溶融密封方法及びシステム | |
US8043880B2 (en) | Microelectronic device | |
US7622334B2 (en) | Wafer-level packaging cutting method capable of protecting contact pads | |
TWI817960B (zh) | 異物除去方法及光檢測裝置之製造方法 | |
Wang et al. | Wafer-level vacuum sealing by transfer bonding of silicon caps for small footprint and ultra-thin MEMS packages | |
US20130307137A1 (en) | Chip package and method for forming the same | |
US7510947B2 (en) | Method for wafer level packaging and fabricating cap structures | |
WO2009038686A2 (en) | Hermetic wafer level cavity package | |
TWI769343B (zh) | 晶圓 | |
US20120012963A1 (en) | Micro device packaging | |
EP2287910A1 (en) | Improvements in or relating to filters in an image sensor | |
TWI397159B (zh) | 微機電系統晶片及其封裝方法 | |
JPH0864558A (ja) | マイクロ電子機械式デバイスを製造する方法 | |
TWI509757B (zh) | 微機電系統晶片及其封裝方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20161004 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170809 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170829 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20171113 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180306 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180531 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180904 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180927 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6412009 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |