JP2016225365A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP2016225365A
JP2016225365A JP2015107717A JP2015107717A JP2016225365A JP 2016225365 A JP2016225365 A JP 2016225365A JP 2015107717 A JP2015107717 A JP 2015107717A JP 2015107717 A JP2015107717 A JP 2015107717A JP 2016225365 A JP2016225365 A JP 2016225365A
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power semiconductor
electrode
conductor member
semiconductor device
chip
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佐武郎 田中
Saburo Tanaka
佐武郎 田中
孝信 梶原
Takanobu Kajiwara
孝信 梶原
達也 深瀬
Tatsuya Fukase
達也 深瀬
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

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Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device which enables improvement of the reliability and reduces a mounting area of a chip type electronic component to achieve downsizing.SOLUTION: A power semiconductor device 100 includes: a lead frame including a first electrode 11 and a second electrode 12 which are separated from each other; a power semiconductor element mounted on the lead frame; a multilayer ceramic capacitor 30 which is disposed on the first electrode 11 and provided with external electrodes 32, 33 located at both sides; and an electric insulator which seals a part of the lead frame, the power semiconductor element, and the capacitor 30. The lower external electrode 32 of the capacitor 30 is joined to the first electrode 11, and the upper external electrode 33 is joined to the second electrode 12 through a conductor member 80 having an L-shaped part 81. The conductor member 80 has rigidity lower than that of the capacitor 30.SELECTED DRAWING: Figure 2

Description

本発明は、リードフレームの上にパワー半導体素子が実装されたパワー半導体装置に関し、特に車載機器に搭載されるパワー半導体装置に関するものである。   The present invention relates to a power semiconductor device in which a power semiconductor element is mounted on a lead frame, and more particularly to a power semiconductor device mounted on an in-vehicle device.

従来、車載機器に搭載されるパワー半導体装置としては、配線パターンが形成された電気絶縁基板の上にパワー半導体素子を半田付けし、これを配線部材で接続したものを樹脂封止したケース型のパワー半導体装置と、ダイオード、MOSFETなどのパワー半導体素子をトランスファ成型したディスクリート型のパワー半導体装置とを組み合わせたものが用いられてきた。   Conventionally, as a power semiconductor device mounted on an in-vehicle device, a case type in which a power semiconductor element is soldered on an electrically insulating substrate on which a wiring pattern is formed, and connected with a wiring member is resin-sealed. A combination of a power semiconductor device and a discrete power semiconductor device in which a power semiconductor element such as a diode or MOSFET is transfer-molded has been used.

パワー半導体素子のうちMOSFET、IGBT(Insulated Gate Bipolar Transistor)などのスイッチング素子では、スイッチングにより間欠的に電流が流れ、電圧変動が生じてしまう。この電圧変動を低減させるため、素子の近傍にコンデンサを設けるのが一般的である。しかし、コンデンサを設けると半導体装置が大型化するという問題があり、特に、配置スペースが限られた車載機器に搭載されるパワー半導体装置ではこの問題が顕著である。   In switching elements such as MOSFETs and IGBTs (Insulated Gate Bipolar Transistors) among power semiconductor elements, current flows intermittently due to switching and voltage fluctuation occurs. In order to reduce this voltage variation, a capacitor is generally provided in the vicinity of the element. However, when a capacitor is provided, there is a problem that the semiconductor device is increased in size, and this problem is particularly remarkable in a power semiconductor device that is mounted on an in-vehicle device having a limited arrangement space.

特許文献1には、小電力を扱う集積回路(ICチップ)がモールド成型された半導体装置であって、リードフレームにおいて、電源供給用の電極とICチップ搭載ステージを支持するダイパッドとの間にチップ型コンデンサが設けられたものが開示されている。このチップ型コンデンサは、電源−接地間を接続するバイパスコンデンサとして機能する。この半導体装置によれば、全体をモールド成型することにより実装密度が向上する。   Patent Document 1 discloses a semiconductor device in which an integrated circuit (IC chip) that handles low power is molded, and a chip between a power supply electrode and a die pad that supports an IC chip mounting stage in a lead frame. A type capacitor is disclosed. This chip type capacitor functions as a bypass capacitor for connecting the power source and the ground. According to this semiconductor device, the mounting density is improved by molding the whole.

また、特許文献2には、互いに分離した電極が形成された基板の上に電子部品を実装する方法であって、基板の上に電気絶縁膜等のスペーサを一時的に配置して電子部品の高さを確保した状態で、電子部品の両側に設けられたリードを、半田を用いて基板の電極に接合する方法が開示されている。この方法によれば、半田の厚さを増加させることにより、温度サイクルを受けたときに基板と電子部品との熱膨張係数の差に起因した応力集中を緩和して、半田および電子部品の劣化を防止できる。   Further, Patent Document 2 is a method of mounting an electronic component on a substrate on which electrodes separated from each other are formed, and a spacer such as an electric insulating film is temporarily disposed on the substrate so that the electronic component is mounted. A method is disclosed in which leads provided on both sides of an electronic component are joined to electrodes of a substrate using solder in a state where the height is secured. According to this method, by increasing the thickness of the solder, the stress concentration caused by the difference in thermal expansion coefficient between the substrate and the electronic component is alleviated when subjected to a temperature cycle, and the deterioration of the solder and the electronic component Can be prevented.

特開昭59−072757号公報JP 59-072757 A 特開2004−31768号公報JP 2004-31768 A

しかし、特許文献1に記載されているように、リードフレームのダイパッドの上に、コンデンサのようなチップ型電子部品を実装してモールド成型した場合、大電力を扱うパワー半導体素子が温度サイクルを受けると、装置を構成する金属部材とモールド樹脂との間の線膨張係数の差に起因してコンデンサに応力集中が生じる。これにより、コンデンサが劣化したり故障したりする可能性があり、信頼性の点で問題がある。   However, as described in Patent Document 1, when a chip-type electronic component such as a capacitor is mounted on a die pad of a lead frame and molded, a power semiconductor element that handles high power undergoes a temperature cycle. In addition, stress concentration occurs in the capacitor due to a difference in linear expansion coefficient between the metal member constituting the apparatus and the mold resin. As a result, there is a possibility that the capacitor may deteriorate or break down, which is problematic in terms of reliability.

また、特許文献2に記載された方法では、電子部品の両側に設けられたリードが電極に接合されるので、電子部品の実装面積が大きくなり、パワー半導体装置の小型化が妨げられる。   Further, in the method described in Patent Document 2, since the leads provided on both sides of the electronic component are joined to the electrodes, the mounting area of the electronic component is increased, and miniaturization of the power semiconductor device is prevented.

本発明は、上記課題を解決するためになされたものであり、信頼性が向上し、かつ、チップ型電子部品の実装面積を低下させることにより小型化したパワー半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and has an object to provide a power semiconductor device that is reduced in size by improving reliability and reducing the mounting area of a chip-type electronic component. To do.

上記目的を達成するために、本発明に係るパワー半導体装置は、互いに分離した第1電極および第2電極を含むリードフレームと、リードフレームの上に実装されたパワー半導体素子と、第1電極の上に配置され、両端に外部電極が設けられたチップ型電子部品と、リードフレームの一部、パワー半導体素子およびチップ型電子部品を封止する絶縁体とを備え、チップ型電子部品の一方の外部電極は、第1電極に接合され、チップ型電子部品の他方の外部電極は、L字状部を有する導体部材を介して第2電極に接合され、導体部材は、チップ型電子部品よりも剛性が低いことを特徴とする。   To achieve the above object, a power semiconductor device according to the present invention includes a lead frame including a first electrode and a second electrode separated from each other, a power semiconductor element mounted on the lead frame, and a first electrode. A chip-type electronic component disposed on the both ends and provided with external electrodes at both ends, and a part of the lead frame, a power semiconductor element, and an insulator that seals the chip-type electronic component. The external electrode is joined to the first electrode, the other external electrode of the chip-type electronic component is joined to the second electrode via a conductor member having an L-shaped part, and the conductor member is more than the chip-type electronic component. It is characterized by low rigidity.

本発明によれば、チップ型電子部品よりも剛性が低いL字状部を有する導体部材を介してチップ型電子部品が第2電極の上に接合されていることにより、応力が作用すると導体部材のL字状部が優先的に変形するため、チップ型電子部品への応力集中を緩和できる。このようにして、パワー半導体装置の信頼性を向上させることができる。   According to the present invention, when the chip-type electronic component is joined onto the second electrode via the conductor member having the L-shaped portion having lower rigidity than the chip-type electronic component, the conductor member is subjected to stress. Since the L-shaped part of this is preferentially deformed, stress concentration on the chip-type electronic component can be alleviated. In this way, the reliability of the power semiconductor device can be improved.

また、チップ型電子部品の一方の外部電極のみが第1電極に接合されることにより、導体部材と第2電極との接合面積を小さくしてチップ型電子部品の実装面積を低下させ、パワー半導体装置を小型化できる。   In addition, since only one external electrode of the chip-type electronic component is bonded to the first electrode, the bonding area between the conductor member and the second electrode is reduced, so that the mounting area of the chip-type electronic component is reduced, and the power semiconductor The device can be miniaturized.

本発明の実施の形態1に係るパワー半導体装置を上方から見た断面図である。It is sectional drawing which looked at the power semiconductor device which concerns on Embodiment 1 of this invention from upper direction. 図1の積層セラミックコンデンサ部分を側方から見た断面図である。It is sectional drawing which looked at the multilayer ceramic capacitor part of FIG. 1 from the side. 本発明の実施の形態2に係るパワー半導体装置を示す、図2に対応する断面図である。It is sectional drawing corresponding to FIG. 2 which shows the power semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2の第1変形例に係るパワー半導体装置の導体部材の一部を示す斜視図である。It is a perspective view which shows a part of conductor member of the power semiconductor device which concerns on the 1st modification of Embodiment 2 of this invention. 本発明の実施の形態2の第2変形例に係るパワー半導体装置の導体部材の一部を示す、(a)図4に対応する斜視図、(b)断面図である。5A is a perspective view corresponding to FIG. 4 and FIG. 5B is a cross-sectional view showing a part of a conductor member of a power semiconductor device according to a second modification of the second embodiment of the present invention. 本発明の実施の形態3に係るパワー半導体装置の一部を示す斜視図である。It is a perspective view which shows a part of power semiconductor device which concerns on Embodiment 3 of this invention.

以下、本発明の実施の形態に係るパワー半導体装置について、図面を参照しながら説明する。各図において、同一または同様の構成部分には同一の符号を付している。また、方向を表す用語「上、下、右、左、水平、垂直」などは、図面中の方向を特定するための便宜的なものであり、装置の設置方向などを限定するものではない。   Hereinafter, a power semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. Further, the terms “upper, lower, right, left, horizontal, vertical” and the like representing the direction are for the purpose of specifying the direction in the drawing, and do not limit the installation direction of the apparatus.

実施の形態1.
図1は、本発明の実施の形態1に係るパワー半導体装置を上方から見た断面図であり、図2は図1の一部を側方から見た断面図である。図中、互いに垂直なx方向とy方向で規定されるxy面内の方向を水平方向、水平面に垂直なz方向を垂直方向と称す。
図1に示すように、パワー半導体装置100は、リードフレーム10と、パワー半導体素子21〜23と、積層セラミックコンデンサ30と、抵抗素子40と、絶縁体(電気絶縁体)50とを備える。パワー半導体素子21〜23、積層セラミックコンデンサ30および抵抗素子40は、チップ型の電子部品である。
Embodiment 1 FIG.
1 is a cross-sectional view of a power semiconductor device according to a first embodiment of the present invention as viewed from above, and FIG. 2 is a cross-sectional view of a part of FIG. 1 as viewed from the side. In the figure, the direction in the xy plane defined by the x direction and the y direction perpendicular to each other is referred to as the horizontal direction, and the z direction perpendicular to the horizontal plane is referred to as the vertical direction.
As shown in FIG. 1, the power semiconductor device 100 includes a lead frame 10, power semiconductor elements 21 to 23, a multilayer ceramic capacitor 30, a resistance element 40, and an insulator (electrical insulator) 50. The power semiconductor elements 21 to 23, the multilayer ceramic capacitor 30 and the resistance element 40 are chip-type electronic components.

パワー半導体装置100は、電気絶縁性の接着剤、基板またはシートなどを介して被固定物、例えば車載機器に固定される。あるいは、パワー半導体装置100は、当該被固定物に対向する面に絶縁層を有していて、半田、放熱グリースなどを用いて被固定物に対して加圧固定されてもよい。   The power semiconductor device 100 is fixed to an object to be fixed, for example, an in-vehicle device via an electrically insulating adhesive, a substrate, a sheet, or the like. Alternatively, the power semiconductor device 100 may have an insulating layer on the surface facing the object to be fixed, and may be pressure-fixed to the object to be fixed using solder, heat radiation grease, or the like.

リードフレーム10は配線パターン状に形成されている。リードフレーム10は、数Aから数百A程度の大電流が流れるパワー端子11〜15と、パワー半導体素子21〜23に制御信号(例えばゲート信号)を伝送する信号端子16〜18とを有する。端子11〜18は、互いに分離しており、絶縁体50から外部に突出している。パワー端子12,14は、減衰器を構成する抵抗素子40により接続されている。パワー端子11〜15は、電力供給装置および電源(バッテリなど)に中継部材を介して接続される。信号端子16〜18は制御基板に接続される。   The lead frame 10 is formed in a wiring pattern. The lead frame 10 has power terminals 11 to 15 through which a large current of several A to several hundreds A flows, and signal terminals 16 to 18 that transmit control signals (for example, gate signals) to the power semiconductor elements 21 to 23. The terminals 11 to 18 are separated from each other and protrude from the insulator 50 to the outside. The power terminals 12 and 14 are connected by a resistance element 40 constituting an attenuator. The power terminals 11 to 15 are connected to a power supply device and a power source (battery or the like) via a relay member. The signal terminals 16 to 18 are connected to the control board.

リードフレーム10の各端子11〜18は、プレス加工、エッチング加工などにより成型されている。この成型工程により、各端子11〜18の上面(主面)の間には、数μmから数百μmの段差(垂直方向の長さ(高さ)の差)が必然的に生じる。このように、各端子11〜18は略同一平面内に配置されている。リードフレーム10は金属製であって、例えばコバール、銅板、銅合金板にニッケル(Ni)めっきしたものが用いられる。   Each of the terminals 11 to 18 of the lead frame 10 is formed by pressing, etching, or the like. By this molding process, a step (a difference in length (height) in the vertical direction) of several μm to several hundred μm inevitably occurs between the upper surfaces (main surfaces) of the terminals 11 to 18. Thus, each terminal 11-18 is arrange | positioned in the substantially same plane. The lead frame 10 is made of metal, for example, Kovar, copper plate, copper alloy plate plated with nickel (Ni) is used.

パワー半導体素子21〜23は、MOSFET、IGBTなどのスイッチング素子である。パワー半導体素子21,22,23は、半田、導電性ペースト(例えば銀ペースト)のような導電性接合材を用いて、それぞれパワー端子11,13,14の上に実装されている。パワー半導体素子21,22,23の主電極は、2本で対になった配線部材61,62,63により、それぞれパワー端子13,14,15に電気的に接続されている。パワー半導体素子21,22,23の制御電極は、配線部材64,65,66により、それぞれ信号端子16,17,18に電気的に接続されている。配線部材61〜66は、例えば、超音波接合により設けられるアルミ製(または銅製)の円形断面(または矩形断面)のワイヤ状部材であってもよいし、半田付けされる金属ターミナルであってもよい。   The power semiconductor elements 21 to 23 are switching elements such as MOSFETs and IGBTs. The power semiconductor elements 21, 22, and 23 are mounted on the power terminals 11, 13, and 14, respectively, using a conductive bonding material such as solder and conductive paste (for example, silver paste). The main electrodes of the power semiconductor elements 21, 22, and 23 are electrically connected to the power terminals 13, 14, and 15 by two wiring members 61, 62, and 63, respectively. The control electrodes of the power semiconductor elements 21, 22, and 23 are electrically connected to the signal terminals 16, 17, and 18 by wiring members 64, 65, and 66, respectively. For example, the wiring members 61 to 66 may be aluminum (or copper) circular cross-section (or rectangular cross-section) wire-like members provided by ultrasonic bonding, or may be soldered metal terminals. Good.

パワー半導体素子21〜23は、珪素(Si)により形成されてもよいし、珪素に比べてバンドギャップが大きいワイドギャップ半導体材料により形成されてもよい。ワイドギャップ半導体材料は、例えば炭化珪素(SiC)、窒化ガリウム(GaN)系材料、ダイヤモンドである。ワイドギャップ半導体材料により形成されたパワー半導体素子21〜23は、耐電圧性が高く許容電流密度も高いために小型化できる。小型化したパワー半導体素子21〜23を用いることにより、これを組み込んだパワー半導体装置100も小型化できる。   The power semiconductor elements 21 to 23 may be formed of silicon (Si), or may be formed of a wide gap semiconductor material having a band gap larger than that of silicon. The wide gap semiconductor material is, for example, silicon carbide (SiC), gallium nitride (GaN) -based material, or diamond. The power semiconductor elements 21 to 23 formed of a wide gap semiconductor material have a high withstand voltage and a high allowable current density, and thus can be miniaturized. By using the miniaturized power semiconductor elements 21 to 23, the power semiconductor device 100 incorporating this can also be miniaturized.

積層セラミックコンデンサ(以下、コンデンサと称す)30は、パワー端子11の上に配置されている。コンデンサ30は、パワー半導体素子21〜23のスイッチングによる電圧変動を低減させる機能を有する。この機能を果たすために、コンデンサ30は好ましくはパワー半導体素子21の近傍に配置される。コンデンサ30は、積層体31と、積層体31の両端に設けられた外部電極32,33とを有する。積層体31の内部では、図2に示すようにセラミック誘電体31aと内部電極31bとが交互に積層されている。コンデンサ30は、セラミック誘電体31aと内部電極31bの積層方向が水平方向に一致する(または略一致する)ように配置される。なお、図2では積層方向がx方向であるが、水平方向であればよい。これにより、外部電極32,33は上下に対向する。外部電極32,33は、積層体31の内部電極31bに交互に接続されている。   A multilayer ceramic capacitor (hereinafter referred to as a capacitor) 30 is disposed on the power terminal 11. The capacitor 30 has a function of reducing voltage fluctuation due to switching of the power semiconductor elements 21 to 23. In order to fulfill this function, the capacitor 30 is preferably arranged in the vicinity of the power semiconductor element 21. The capacitor 30 includes a multilayer body 31 and external electrodes 32 and 33 provided at both ends of the multilayer body 31. Inside the multilayer body 31, ceramic dielectric bodies 31a and internal electrodes 31b are alternately laminated as shown in FIG. The capacitor 30 is arranged so that the stacking direction of the ceramic dielectric 31a and the internal electrode 31b matches (or substantially matches) the horizontal direction. In FIG. 2, the stacking direction is the x direction, but it may be in the horizontal direction. Thereby, the external electrodes 32 and 33 face each other vertically. The external electrodes 32 and 33 are alternately connected to the internal electrode 31 b of the multilayer body 31.

コンデンサ30の一方(下側)の外部電極(下側外部電極)32は、導電性接合材71を用いてパワー端子11に接合されている。コンデンサ30の他方(上側)の外部電極(上側外部電極)33は、導電性接合材72を用いて導体部材80に接合されている。導体部材80は、導電性接合材73を用いてパワー端子12に接合されている。この導体部材80の剛性は、コンデンサ30および導電性接合材71〜73よりも低い。導電性接合材71〜73は、例えば半田、導電性ペースト(例えば銀ペースト)である。   One (lower) external electrode (lower external electrode) 32 of the capacitor 30 is bonded to the power terminal 11 using a conductive bonding material 71. The other (upper) external electrode (upper external electrode) 33 of the capacitor 30 is bonded to the conductor member 80 using a conductive bonding material 72. The conductor member 80 is bonded to the power terminal 12 using a conductive bonding material 73. The rigidity of the conductor member 80 is lower than that of the capacitor 30 and the conductive bonding materials 71 to 73. The conductive bonding materials 71 to 73 are, for example, solder or conductive paste (for example, silver paste).

使用時、パワー端子11はパワー端子12に比べて電位が高い。このように、コンデンサ30は、使用時に互いに電位が異なる2つの隣接端子間に実装される。なお、パワー端子11,12は、それぞれ第1電極、第2電極の一例である。   In use, the power terminal 11 has a higher potential than the power terminal 12. Thus, the capacitor 30 is mounted between two adjacent terminals having different potentials when used. The power terminals 11 and 12 are examples of the first electrode and the second electrode, respectively.

導体部材80は、L字状部81と、L字状部81の一端(下端)から水平方向(図中のx方向)に延びてパワー端子12に接合される板状の被接合部84とを有する。L字状部81は、コンデンサ30の上側外部電極33に接合されて水平方向(図中のx方向)に沿って延びる第1板部82と、一端で第1板部82に接続されかつ他端で被接合部84に接合されて垂直方向に沿って延びる第2板部83とを有する。このように、導体部材80は、2つのパワー端子11,12を三次元的に橋渡ししている。なお、第1板部82と第2板部83とが直交している必要はない。被接合部84の面積は、下側外部電極32の面積よりも小さい。   The conductor member 80 includes an L-shaped portion 81, a plate-shaped bonded portion 84 that extends in the horizontal direction (x direction in the drawing) from one end (lower end) of the L-shaped portion 81 and is bonded to the power terminal 12. Have The L-shaped portion 81 is joined to the upper external electrode 33 of the capacitor 30 and extends along the horizontal direction (x direction in the figure), and is connected to the first plate portion 82 at one end and the other. The second plate portion 83 is joined to the joined portion 84 at the end and extends along the vertical direction. As described above, the conductor member 80 bridges the two power terminals 11 and 12 three-dimensionally. The first plate portion 82 and the second plate portion 83 do not have to be orthogonal. The area of the bonded portion 84 is smaller than the area of the lower external electrode 32.

図2に示すように、被接合部84は、第2板部83の下端から水平方向(図中のx方向)に距離D延びている。また、第2板部83の垂直方向の長さ(高さ)をHとする。第2板部83の高さ、すなわち導体部材80の高さHは、距離Dに対して2倍以上5倍以下の大きさであることが好ましい。導体部材80の高さHの大きさをこの範囲内とすることで、導体部材80のL字状部81の剛性を低下させてL字状部81を優先的に変形させやすいことがわかっている。   As shown in FIG. 2, the bonded portion 84 extends a distance D from the lower end of the second plate portion 83 in the horizontal direction (x direction in the drawing). The length (height) of the second plate portion 83 in the vertical direction is H. The height of the second plate portion 83, that is, the height H of the conductor member 80 is preferably 2 times or more and 5 times or less the distance D. It has been found that by setting the height H of the conductor member 80 within this range, the rigidity of the L-shaped portion 81 of the conductor member 80 can be reduced and the L-shaped portion 81 can be preferentially deformed. Yes.

導体部材80は、一枚の導体板を折り曲げて成型されてもよいし、複数枚の導体板を接合して成型してもよい。一枚の導体板で導体部材80を成型することにより、導体部材80を容易に形成できる利点がある。   The conductor member 80 may be formed by bending a single conductor plate, or may be formed by joining a plurality of conductor plates. There is an advantage that the conductor member 80 can be easily formed by molding the conductor member 80 with a single conductor plate.

絶縁体50は、例えばエポキシ樹脂であって、リードフレーム10の一部、リードフレーム10の上に設けられたパワー半導体素子21〜23、コンデンサ30、抵抗素子40などを封止する。   The insulator 50 is, for example, an epoxy resin, and seals a part of the lead frame 10, the power semiconductor elements 21 to 23, the capacitor 30, the resistance element 40, and the like provided on the lead frame 10.

以上のような構成を有するパワー半導体装置100は、例えば以下の工程S1〜S3により製造できる。
(S1)配線パターン状に配設されたリードフレーム10の上に導電性接合材を用いて各チップ部品を接合する。
(S2)配線部材3をパワー半導体素子21〜23と端子11〜18に超音波接合し、中間構造体を製造する。
(S3)絶縁体50を用いて中間構造体をトランスファ成型する。
工程S1で、コンデンサ30は、導電性接合材71を用いてパワー端子11の上に下側外部電極32を接合し、続いて導電性接合材72,73を用いて上側外部電極33とパワー端子12の上に導体部材80を接合することにより実装される。
The power semiconductor device 100 having the above configuration can be manufactured, for example, by the following steps S1 to S3.
(S1) Each chip component is bonded onto the lead frame 10 arranged in a wiring pattern using a conductive bonding material.
(S2) The wiring member 3 is ultrasonically bonded to the power semiconductor elements 21 to 23 and the terminals 11 to 18 to manufacture an intermediate structure.
(S3) The intermediate structure is transfer molded using the insulator 50.
In step S1, the capacitor 30 joins the lower external electrode 32 on the power terminal 11 using the conductive bonding material 71, and then uses the conductive bonding materials 72 and 73 to connect the upper external electrode 33 and the power terminal. It is mounted by bonding a conductor member 80 on 12.

パワー半導体装置100では、制御基板に接続された信号端子16〜18から伝送される制御信号によりパワー半導体素子21〜23がスイッチングを行い、出力を行うパワー端子11〜15に通電する電流量が制御される。   In the power semiconductor device 100, the power semiconductor elements 21 to 23 are switched by the control signals transmitted from the signal terminals 16 to 18 connected to the control board, and the amount of current supplied to the power terminals 11 to 15 for output is controlled. Is done.

次に、本実施形態1により得られる効果について説明する。
この効果の説明において、本実施形態1と同様にリードフレームの2つの端子間にコンデンサの両端の外部電極がそれぞれ接合された構造を「比較例」と称す。比較例は、本実施形態1でいうと、外部電極32,33がそれぞれパワー端子11,12に接合される構成である。すなわち従来構造では、外部電極32,33が左右に対向することになる。
Next, effects obtained by the first embodiment will be described.
In the description of this effect, the structure in which the external electrodes at both ends of the capacitor are joined between the two terminals of the lead frame as in the first embodiment is referred to as a “comparative example”. In the comparative example, in the first embodiment, the external electrodes 32 and 33 are joined to the power terminals 11 and 12, respectively. That is, in the conventional structure, the external electrodes 32 and 33 are opposed to the left and right.

一般に、車載用のパワー半導体装置は、車載機器の動作、パワー半導体素子が設置される雰囲気の変動、パワー半導体素子の通電などにより、その温度が大きく変動する。したがって、リードフレームの上にコンデンサを実装してモールド成型する場合、比較例の構造では、装置を構成する金属部材とモールド樹脂との間の線膨張係数の差に起因してコンデンサに応力集中が生じるおそれがある。また、トランスファ成型前の中間構造体(本実施形態1では上記工程S2で製造される)を製造ライン上で搬送する際にも、搬送時の振動、または搬送時に作用する外力に起因して、コンデンサに応力集中が生じるおそれがある。さらに、上記の通り、リードフレームを構成する端子間には、数μmから数百μm程度の段差が存在するところ、中間構造体をモールド成型すると、100気圧程度にも達する成型圧、モールド成型時の型締めにより、この段差が小さくなるように応力が作用することがある。これらにより、コンデンサまたは半田にクラックが生じ、コンデンサとリードフレームとの接合部の破断、コンデンサの劣化、故障といった問題が発生しうる。   Generally, the temperature of an in-vehicle power semiconductor device varies greatly due to the operation of the in-vehicle device, the change in atmosphere in which the power semiconductor element is installed, the energization of the power semiconductor element, and the like. Therefore, when a capacitor is mounted on a lead frame and molded, the structure of the comparative example causes stress concentration in the capacitor due to the difference in coefficient of linear expansion between the metal member constituting the device and the mold resin. May occur. Also, when the intermediate structure before transfer molding (produced in the above-described step S2 in the first embodiment) is transported on the production line, due to vibration during transport or external force acting during transport, There is a risk of stress concentration in the capacitor. Further, as described above, there is a step of about several μm to several hundred μm between the terminals constituting the lead frame. When the intermediate structure is molded, the molding pressure reaches about 100 atm. When the mold is clamped, stress may act to reduce this step. As a result, a crack occurs in the capacitor or solder, and problems such as breakage of the joint between the capacitor and the lead frame, deterioration of the capacitor, and failure may occur.

本実施形態1によれば、導体部材80の剛性がコンデンサ30よりも低いことにより、特に水平方向に応力が作用すると、導体部材80のL字状部81が優先的に変形するため、コンデンサ30への応力集中が緩和される。また、外部電極32,33が上下に対向するようにコンデンサ30を配置することにより、比較例に比べて、垂直方向に作用する応力に対してもコンデンサ30の強度を向上させることができる。   According to the first embodiment, since the rigidity of the conductor member 80 is lower than that of the capacitor 30, the L-shaped portion 81 of the conductor member 80 is preferentially deformed when stress is applied particularly in the horizontal direction. The stress concentration on is relaxed. Further, by disposing the capacitor 30 so that the external electrodes 32 and 33 face each other vertically, the strength of the capacitor 30 can be improved against stress acting in the vertical direction as compared with the comparative example.

このようにして、コンデンサ30とリードフレーム10との接合部の破断、コンデンサ30の劣化、故障などが防止される。また、パワー半導体装置100の中間構造体の搬送時の故障等を防止して歩留まりを向上させることができる。さらに、パワー半導体装置100をモールド成型する際にコンデンサまたは半田におけるクラックの発生が抑制され、さらに歩留まりを向上させることができる。
これらの効果は、導体部材80の剛性がコンデンサ30よりも低いだけでなく導電性接合材71〜73よりも低いことにより、より顕著に得ることができる。
In this way, breakage of the joint between the capacitor 30 and the lead frame 10, deterioration of the capacitor 30, failure, and the like are prevented. In addition, it is possible to prevent a failure or the like during transfer of the intermediate structure of the power semiconductor device 100 and improve the yield. Furthermore, when the power semiconductor device 100 is molded, the generation of cracks in the capacitor or solder is suppressed, and the yield can be further improved.
These effects can be obtained more remarkably by not only the rigidity of the conductor member 80 being lower than that of the capacitor 30 but also being lower than that of the conductive bonding materials 71 to 73.

また、コンデンサ30の実装面積は、コンデンサ30の下側外部電極32の接合面積と、導体部材80の被接合部84の接合面積の和であるところ、本実施形態1のように被接合部84の面積を下側外部電極32の面積より小さくすることにより、比較例に比べてコンデンサ30の実装面積を低下させることができ、ひいてはパワー半導体装置100を水平方向に小型化できる。   In addition, the mounting area of the capacitor 30 is the sum of the bonding area of the lower external electrode 32 of the capacitor 30 and the bonding area of the bonded portion 84 of the conductor member 80, and the bonded portion 84 as in the first embodiment. By making this area smaller than the area of the lower external electrode 32, the mounting area of the capacitor 30 can be reduced as compared with the comparative example, and the power semiconductor device 100 can be downsized in the horizontal direction.

また、比較例において高い実装密度を得るために、リードフレームの端子間隔を小さくした場合には、半田がコンデンサの外部電極を這い上がって外部電極間が短絡し、歩留りが悪化するおそれがある。
本実施形態1では、パワー端子11,12の間隔を小さくした場合でも、これらの間を三次元的に橋渡しする導体部材80が設けられていることにより、半田の這い上がりによる外部電極32,33の間の短絡が防止される。
Further, in the comparative example, when the lead frame terminal interval is reduced in order to obtain a high mounting density, the solder scoops up the external electrodes of the capacitor, and the external electrodes may be short-circuited, which may deteriorate the yield.
In the first embodiment, even when the distance between the power terminals 11 and 12 is reduced, the external electrodes 32 and 33 due to solder rising are provided by providing the conductor member 80 that bridges the power terminals 3 and 3 in a three-dimensional manner. A short circuit between is prevented.

なお、比較例でパワー半導体素子をワイドギャップ半導体材料で形成した場合、素子の耐電圧性、許容電流密度が高くなるため、使用の態様によっては雰囲気温度がより高くなり、コンデンサに応力集中が生じるおそれがある。したがって、パワー半導体装置において放熱面積を大きくする必要が生じ、その小型化が困難になる可能性がある。
一方、本実施形態1では、上記の通り導体部材80を設けたことにより応力集中が緩和されるため、ワイドギャップ半導体材料を使用したパワー半導体素子21〜23を実装した場合であっても装置100の小型化が可能となる。
In the comparative example, when the power semiconductor element is formed of a wide gap semiconductor material, the withstand voltage and allowable current density of the element are increased, so that the ambient temperature becomes higher depending on the use mode, and stress concentration occurs in the capacitor. There is a fear. Therefore, it is necessary to increase the heat dissipation area in the power semiconductor device, and it may be difficult to reduce the size.
On the other hand, in the first embodiment, since the stress concentration is reduced by providing the conductor member 80 as described above, the apparatus 100 even when the power semiconductor elements 21 to 23 using the wide gap semiconductor material are mounted. Can be reduced in size.

実施の形態2.
図3は、本発明の実施の形態2に係るパワー半導体装置を示す、図2に対応する断面図である。
実施形態2は、導体部材80の被接合部84が接合されるパワー端子112の構造が実施形態1(パワー端子12)と異なる。具体的には、パワー端子112は、導体部材80を受ける凹部112aを有する。凹部112aは、底面112bと側壁112cとで構成される。被接合部84は、凹部112aの底面112bの上に接合される。
Embodiment 2. FIG.
FIG. 3 is a cross-sectional view corresponding to FIG. 2, showing a power semiconductor device according to Embodiment 2 of the present invention.
The second embodiment is different from the first embodiment (power terminal 12) in the structure of the power terminal 112 to which the joined portion 84 of the conductor member 80 is joined. Specifically, the power terminal 112 has a recess 112 a that receives the conductor member 80. The recess 112a includes a bottom surface 112b and a side wall 112c. The bonded portion 84 is bonded onto the bottom surface 112b of the recess 112a.

本実施形態2によれば、導電性接合材73を用いて導体部材80をパワー端子12に接合する際に、導体部材80の水平方向の位置ずれを凹部112aにより制御できる利点がある。また、導体部材80をコンデンサ30の上側外部電極33とパワー端子12とに接合する際に、図2の紙面奥側、手前側方向(図中のyz面内)での傾きを制御できる利点がある。さらに、モールド成型後には、凹部112a内に絶縁体50が充填され、被接合部84が絶縁体50に覆われて固定されるので、導体部材80の固定強度を高めることができる。   According to the second embodiment, when the conductor member 80 is bonded to the power terminal 12 using the conductive bonding material 73, there is an advantage that the horizontal position shift of the conductor member 80 can be controlled by the recess 112a. Further, when the conductor member 80 is joined to the upper external electrode 33 and the power terminal 12 of the capacitor 30, there is an advantage that the inclination in the rear side and front side direction (in the yz plane in the drawing) of FIG. is there. Furthermore, after molding, the insulator 50 is filled in the recess 112a, and the bonded portion 84 is covered and fixed by the insulator 50, so that the fixing strength of the conductor member 80 can be increased.

図4は、実施形態2の第1変形例に係るパワー半導体装置の導体部材の一部を示す斜視図である。
この第1変形例は、導体部材180の被接合部184の構造が図3に示したもの(導体部材80の被接合部84)と異なる。具体的には、図3では、被接合部84が、第2板部83に対して水平方向片側(+x方向)にのみ突出してL字を形成しているところ、第1変形例では、被接合部184は第2板部183に対して水平方向両側に突出してT字を形成している。なお、第1変形例で、パワー端子112の形状は図3と同じであってよい。この第1変形例によれば、実施形態2により得られる効果を高めることができる。
FIG. 4 is a perspective view showing a part of a conductor member of a power semiconductor device according to a first modification of the second embodiment.
In the first modification, the structure of the bonded portion 184 of the conductor member 180 is different from that shown in FIG. 3 (the bonded portion 84 of the conductor member 80). Specifically, in FIG. 3, the bonded portion 84 protrudes only in one horizontal direction (+ x direction) with respect to the second plate portion 83 to form an L shape. The joint portion 184 protrudes on both sides in the horizontal direction with respect to the second plate portion 183 to form a T shape. In the first modification, the shape of the power terminal 112 may be the same as that in FIG. According to the first modification, the effect obtained by the second embodiment can be enhanced.

図5は、実施形態2の第2変形例に係るパワー半導体装置の導体部材の一部を示す(a)斜視図と(b)断面図である。
この第2変形例は、導体部材280の被接合部284およびパワー端子212の構造が、図3に示したもの(導体部材80の被接合部84およびパワー端子112)と異なる。具体的には、被接合部284は、第1変形例と同様に第2板部283に対して水平方向両側に突出してT字を形成する突出部285と、突出部285の水平方向(x方向)両端部から垂直方向に延びる二股部286とを有する。次に、パワー端子212は、導体部材280の二股部286を受ける凹部212a,212bを有する。この第1変形例によれば、実施形態2により得られる効果を高めることができる。
5A is a perspective view and FIG. 5B is a cross-sectional view illustrating a part of a conductor member of a power semiconductor device according to a second modification of the second embodiment.
In the second modification, the structures of the joined portion 284 and the power terminal 212 of the conductor member 280 are different from those shown in FIG. 3 (the joined portion 84 of the conductor member 80 and the power terminal 112). Specifically, as in the first modification, the bonded portion 284 includes a protruding portion 285 that protrudes on both sides in the horizontal direction with respect to the second plate portion 283 to form a T-shape, and a horizontal direction (x Direction) and a bifurcated portion 286 extending vertically from both ends. Next, the power terminal 212 has recesses 212 a and 212 b that receive the bifurcated portion 286 of the conductor member 280. According to the first modification, the effect obtained by the second embodiment can be enhanced.

実施の形態3.
図6は、本発明の実施の形態3に係るパワー半導体装置の一部を示す斜視図である。
実施形態3は、パワー端子11の上に2つ以上のコンデンサが実装され、当該コンデンサが並列接続される構成に適用されるものである。2つ以上のコンデンサの静電容量は、同じであってもよいし異なっていてもよい。
Embodiment 3 FIG.
FIG. 6 is a perspective view showing a part of the power semiconductor device according to the third embodiment of the present invention.
The third embodiment is applied to a configuration in which two or more capacitors are mounted on the power terminal 11 and the capacitors are connected in parallel. The capacitance of two or more capacitors may be the same or different.

図6では、例として2つのコンデンサ331,332(実施形態1のコンデンサ30に対応する)が設けられている。導体部材380(実施形態1の導体部材80に対応する)は、実施形態1,2と同様に、L字状部381と被接合部384とを有する。導体部材380はさらに、コンデンサ331,332を並列接続する板状の接続端子部385を有する。接続端子部385は、第1水平方向(図中のx方向)に沿って延びるL字状部381の端部に接続され、かつ、第1水平方向に垂直な第2水平方向(y方向)に沿って延びている。接続端子部385は、図示しない導電性接合材を用いてコンデンサ331,332の上側の外部電極に接合されている。   In FIG. 6, two capacitors 331 and 332 (corresponding to the capacitor 30 of the first embodiment) are provided as an example. The conductor member 380 (corresponding to the conductor member 80 of the first embodiment) has an L-shaped portion 381 and a joined portion 384 as in the first and second embodiments. The conductor member 380 further includes a plate-like connection terminal portion 385 that connects the capacitors 331 and 332 in parallel. The connection terminal portion 385 is connected to the end portion of the L-shaped portion 381 extending along the first horizontal direction (x direction in the drawing), and is in the second horizontal direction (y direction) perpendicular to the first horizontal direction. It extends along. The connection terminal portion 385 is bonded to the external electrode on the upper side of the capacitors 331 and 332 using a conductive bonding material (not shown).

本実施形態3によれば、パワー端子11の上に2つ以上のコンデンサを実装する構成において、実施形態1で説明した利点を得ることができる。   According to the third embodiment, in the configuration in which two or more capacitors are mounted on the power terminal 11, the advantages described in the first embodiment can be obtained.

以上、実施形態1〜3を挙げて本発明を説明したが、本発明はこれらの実施形態に限定されない。また、実施形態には、種々の変形、改良が加えられてよい。また、各実施形態に記載された特徴は、自由に組み合わせられてよい。   Although the present invention has been described with reference to the first to third embodiments, the present invention is not limited to these embodiments. Various modifications and improvements may be added to the embodiment. The features described in each embodiment may be freely combined.

例えば、上記実施形態では、リードフレーム10の端子11,12の間に積層セラミックコンデンサを接続したが、これに限定されず、端子11,12の間にチップ型電子部品を接合により設ける構成であれば本発明を適用できる。   For example, in the above-described embodiment, a multilayer ceramic capacitor is connected between the terminals 11 and 12 of the lead frame 10, but the present invention is not limited to this, and a configuration in which a chip-type electronic component is provided between the terminals 11 and 12 by bonding. The present invention can be applied.

また、上記実施形態では、コンデンサ30の下側外部電極32とパワー端子11、上側外部電極33と導体部材80、および導体部材80とパワー端子12をそれぞれ導電性接合材71〜73を用いて接合したが、超音波接合され、または溶接された場合でも、上記実施形態の効果を得ることができる。   In the above embodiment, the lower external electrode 32 and the power terminal 11, the upper external electrode 33 and the conductor member 80, and the conductor member 80 and the power terminal 12 are bonded using the conductive bonding materials 71 to 73, respectively. However, the effect of the above embodiment can be obtained even when ultrasonic bonding or welding is performed.

10 リードフレーム、 11〜15 パワー端子、 16〜18 信号端子、 21〜23 パワー半導体素子、 30 積層セラミックコンデンサ、 32,33 外部電極、 50 絶縁体、 61〜66 配線部材、 71〜73 導電性接合材、 80 導体部材、 81 L字状部、 84 被接合部、 100 パワー半導体装置 DESCRIPTION OF SYMBOLS 10 Lead frame, 11-15 Power terminal, 16-18 Signal terminal, 21-23 Power semiconductor element, 30 Multilayer ceramic capacitor, 32, 33 External electrode, 50 Insulator, 61-66 Wiring member, 71-73 Conductive joining Material, 80 conductor member, 81 L-shaped part, 84 joined part, 100 power semiconductor device

Claims (7)

互いに分離した第1電極および第2電極を含むリードフレームと、
前記リードフレームの上に実装されたパワー半導体素子と、
前記第1電極の上に配置され、両端に外部電極が設けられたチップ型電子部品と、
前記リードフレームの一部、前記パワー半導体素子および前記チップ型電子部品を封止する絶縁体とを備え、
前記チップ型電子部品の一方の外部電極は、前記第1電極に接合され、
前記チップ型電子部品の他方の外部電極は、L字状部を有する導体部材を介して前記第2電極に接合され、
前記導体部材は、前記チップ型電子部品よりも剛性が低いことを特徴とする
パワー半導体装置。
A lead frame including a first electrode and a second electrode separated from each other;
A power semiconductor element mounted on the lead frame;
A chip-type electronic component disposed on the first electrode and provided with external electrodes at both ends;
A part of the lead frame, the power semiconductor element and an insulator for sealing the chip-type electronic component;
One external electrode of the chip-type electronic component is bonded to the first electrode,
The other external electrode of the chip-type electronic component is joined to the second electrode via a conductor member having an L-shaped part,
The power semiconductor device, wherein the conductor member has lower rigidity than the chip-type electronic component.
前記第2電極は、前記導体部材を受ける凹部を有することを特徴とする、
請求項1に記載のパワー半導体装置。
The second electrode has a recess for receiving the conductor member,
The power semiconductor device according to claim 1.
前記チップ型電子部品を2つ以上備え、
前記導体部材は、前記2つ以上のチップ型電子部品を並列接続する接続端子部を有することを特徴とする、
請求項1または2に記載のパワー半導体装置。
Two or more chip-type electronic components are provided,
The conductor member has a connection terminal portion for connecting the two or more chip-type electronic components in parallel.
The power semiconductor device according to claim 1 or 2.
前記チップ型電子部品の一方の外部電極と前記第1電極、前記チップ型電子部品の他方の外部電極と前記導体部材、および前記導体部材と前記第2電極はそれぞれ、前記導体部材よりも剛性の高い導電性接合材を用いて接合され、超音波接合され、または溶接されて接合されたことを特徴とする、
請求項1から3のいずれか1項に記載のパワー半導体装置。
One external electrode and the first electrode of the chip-type electronic component, the other external electrode of the chip-type electronic component and the conductor member, and the conductor member and the second electrode are each more rigid than the conductor member. Bonded using high conductive bonding material, ultrasonic bonded or welded,
The power semiconductor device according to claim 1.
前記導体部材は、前記L字状部の一端から水平方向に所定距離D延びて前記第2電極に接合される被接合部を有し、
前記導体部材の高さHは、前記所定距離Dに対して2倍以上5倍以下の大きさを有することを特徴とする、
請求項1から4のいずれか1項に記載のパワー半導体装置。
The conductor member has a joined portion that extends in a horizontal direction D from one end of the L-shaped portion and is joined to the second electrode;
The height H of the conductor member has a size of 2 to 5 times the predetermined distance D,
The power semiconductor device according to claim 1.
前記導体部材は、一枚の導体板であることを特徴とする、
請求項1から5のいずれか1項に記載のパワー半導体装置。
The conductor member is a single conductor plate,
The power semiconductor device according to claim 1.
前記チップ型電子部品は、積層セラミックコンデンサであることを特徴とする、
請求項1から6のいずれか1項に記載のパワー半導体装置。
The chip-type electronic component is a multilayer ceramic capacitor,
The power semiconductor device according to claim 1.
JP2015107717A 2015-05-27 2015-05-27 Power semiconductor device Pending JP2016225365A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11855525B2 (en) 2020-05-18 2023-12-26 Hyundai Motor Company Connection structure of snubber circuit within semiconductor device and power module structure using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11855525B2 (en) 2020-05-18 2023-12-26 Hyundai Motor Company Connection structure of snubber circuit within semiconductor device and power module structure using same

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