JP2016220423A - Power supply device and power supply control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an excessive current (through current) from flowing to a primary-side switching element under a light load.SOLUTION: A power supply device comprises a DC/DC converter. The DC/DC converter comprises: a full bridge circuit; a transformer including a primary-side coil to which the full bridge circuit is connected, and a secondary-side coil which is insulated from the primary-side coil; a synchronous rectifier circuit which is connected to the secondary-side coil; and a control part which controls a first switching element and a second switching element that are connected to a first end of the primary-side coil by a predetermined fixed duty, controls a third switching element and a fourth switching element that are connected to a second end of the primary-side coil by pulse width modulation, and turns on a fifth switching element and a sixth switching element that the synchronous rectifier circuit includes, for at least a predetermined period just before the third switching element and the fourth switching element are turned off.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply device and a power supply control method.

  In recent years, a power supply device including a DC / DC converter that synchronously rectifies the secondary side of a transformer is known for high efficiency (see Patent Document 1).

JP-A-9-149635

  By the way, the power supply apparatus described above includes a full-bridge DC / DC converter (hereinafter referred to as a full-bridge converter), and operates a primary-side switching element in a ZVS (Zero Voltage Switching) manner. However, in the power supply device described above, an excessive current (through current) may flow through the primary-side switching element without performing the ZVS operation at a light load.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power supply apparatus and a power supply that can prevent an excessive current (through current) from flowing through the switching element on the primary side at a light load. It is to provide a control method.

  In order to solve the above problem, an aspect of the present invention is a power supply device including a DC / DC converter, wherein the DC / DC converter includes a first switching element and a second switching element connected in series. A full-bridge circuit in which a third switching element and a fourth switching element are connected in series, and the four switching elements are bridge-connected, and a primary coil to which the full-bridge circuit is connected directly or indirectly; A transformer having a primary side coil and an insulated secondary side coil, a fifth switching element, and a sixth switching element, wherein the two switching elements are connected to the secondary side coil. A synchronous rectifier circuit, a full bridge circuit, and a controller that controls on / off of a switching element included in the synchronous rectifier circuit. The control unit controls the first switching element and the second switching element connected to the first end of the primary coil with a predetermined fixed duty, and controls the first switching element and the second switching element to the second end of the primary coil. The third switching element and the fourth switching element to be connected are controlled by pulse width modulation, and the fifth switching element or the fourth switching element is at least for a predetermined period immediately before the third switching element or the fourth switching element is turned off. The power supply device is characterized in that the switching element and the sixth switching element are turned on.

  According to one embodiment of the present invention, in the above power supply device, the control unit can determine that the period in which the fifth switching element is off is part of the period in which the fourth switching element is on. The fifth switching element is turned off so as to include a period, and the fifth switching element is turned on before the predetermined period during which the fourth switching element is turned off. The sixth switching element is turned off and the third switching element is turned off so that the off-state period includes a part of the period in which the third switching element is on. The sixth switching element is turned on before a predetermined period.

  Further, according to one embodiment of the present invention, in the above power supply device, the control unit may turn on the fifth switching element and the sixth switching element for the predetermined period at least at a light load. Features.

  Further, according to one aspect of the present invention, in the power supply device described above, the control unit may be configured so that the fourth switching element is turned off after a predetermined period of time from the timing at which the fifth switching element is turned on. The control signal of the third switching element is delayed so that the third switching element is turned off with a delay of the predetermined period from the timing when the sixth switching element is turned on. A delay adjustment unit is provided.

  In addition, according to one embodiment of the present invention, in the power supply device described above, it is determined that a current that pulls out a charge charged in a parasitic capacitance of the switching element included in the full bridge circuit is generated in the predetermined period. It is characterized by that.

  Another embodiment of the present invention is a power supply control method for a power supply device including a DC / DC converter, wherein the DC / DC converter includes a first switching element and a second switching element connected in series, 3 switching elements and a fourth switching element are connected in series, and the four switching elements are bridge-connected, a primary side coil to which the full bridge circuit is connected directly or indirectly, A synchronization having a transformer having a primary side coil and an insulated secondary side coil, a fifth switching element, and a sixth switching element, wherein the two switching elements are connected to the secondary side coil. A control unit that controls ON / OFF of a switching element included in the rectifier circuit, the full bridge circuit, and the synchronous rectifier circuit; The control unit controls the first switching element and the second switching element connected to the first end of the primary side coil with a predetermined fixed duty and is connected to the second end of the primary side coil. The third switching element and the fourth switching element to be controlled are controlled by pulse width modulation, and the fifth switching element is at least for a predetermined period before the third switching element or the fourth switching element is turned off. The power supply control method is characterized in that an element and the sixth switching element are turned on.

  According to the present invention, it is possible to increase the regenerative current to the primary side by short-circuiting the secondary side for a predetermined period, and the charge charged in the parasitic capacitance of the primary side switching element even at light load Can be discharged and a ZVS operation can be performed. Therefore, it is possible to prevent an excessive current from flowing through the switching element at a light load.

It is a block diagram which shows an example of the power supply device by this embodiment. It is a time chart which shows an example of control of the DC / DC converter by this embodiment. It is a block diagram which shows an example of the control part by this embodiment. It is a time chart which shows an example of control by the control part shown in FIG. It is a time chart which shows the operation | movement at the time of light load of the conventional power supply device. It is a time chart which shows an example of the operation | movement at the time of the light load of the power supply device by this embodiment. It is a block diagram which shows the delay adjustment part of another example by this embodiment. It is a block diagram which shows an example of the power supply device of the three-phase control by this embodiment.

Hereinafter, a power supply device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating an example of a power supply device 1 according to the present embodiment.

  As shown in the figure, the power supply device 1 includes a DC / DC converter 10. The DC / DC converter 10 includes a voltage detection unit 12, a control unit 13, a full bridge circuit 20, a driver unit 40, a smoothing capacitor (Ci, Co), a transformer TL1, and a resonance capacitor C5. A reactor L1, a diode (D5, D6), a synchronous rectifier circuit 30, and a choke coil L2 are provided.

The smoothing capacitor Ci is connected between the input power supply line VI (first power supply line) and the power supply line GND1 (second power supply line), and smoothes the input voltage.
The full bridge circuit 20 includes switching elements Q1 to Q4, parasitic capacitances C1 to C4, and body diodes D1 to D4. That is, the full bridge circuit 20 includes a switching element Q1, a switching element Q2, a switching element Q3, and a switching element Q4, and is configured by bridging the four switching elements Q1 to Q4. Specifically, the full bridge circuit 20, for example, connects the switching element Q1 and the switching element Q2 in series, connects the switching element Q3 and the switching element Q4 in series, and bridge-connects the four switching elements Q1 to Q4. Configured.

  The switching element Q1 (an example of the first switching element) has a drain terminal connected to the power supply line VI, a source terminal connected to the node N1, and a gate terminal connected to the signal line of the drive signal G1. That is, the switching element Q1 is connected between the power supply line VI and a first end of a primary side coil TL11 described later via a resonance capacitor C5. Further, the switching element Q1 has a parasitic capacitance C1 and a body diode D1 between the drain terminal and the source terminal.

  The switching element Q2 (an example of the second switching element) has a drain terminal connected to the node N1, a source terminal connected to the power supply line GND1, and a gate terminal connected to the signal line of the drive signal G2. That is, the switching element Q2 is connected between the power supply line GND1 and a first end of a primary side coil TL11 described later. Moreover, the switching element Q2 is connected between the 1st end of the primary side coil TL11 mentioned later via the resonant capacitor C5. Further, the switching element Q2 has a parasitic capacitance C2 and a body diode D2 between the drain terminal and the source terminal.

  Switching element Q3 (an example of a third switching element) has a drain terminal connected to power supply line VI, a source terminal connected to node N2, and a gate terminal connected to a signal line for drive signal G3. That is, the switching element Q3 is connected between the power supply line VI and a second end (node N3) of a primary side coil TL11 described later via the series reactor L1. Further, the switching element Q3 has a parasitic capacitance C3 and a body diode D3 between the drain terminal and the source terminal.

The switching element Q4 (an example of the fourth switching element) has a drain terminal connected to the node N2, a source terminal connected to the power supply line GND1, and a gate terminal connected to the signal line of the drive signal G4. That is, the switching element Q4 is connected between the power supply line GND1 and a second end (node N3) of a primary side coil TL11 described later via the series reactor L1. Further, the switching element Q4 has a parasitic capacitance C4 and a body diode D4 between the drain terminal and the source terminal.
The drive signals G1 to G4 are control signals for controlling the switching elements Q1 to Q4.

  The transformer TL1 has a primary side coil TL11 and a secondary side coil (TL12, TL13) with a center tap, and converts the power supplied to the primary side coil TL11 to convert the secondary side coil (TL12, TL13). Output to. The transformer TL1 includes, for example, a primary coil TL11 to which the full bridge circuit 20 is directly or indirectly connected, and secondary coils (TL12, TL13) insulated from the primary coil TL11.

  The primary coil TL11 is connected to the full bridge circuit 20. For example, the primary side coil TL11 has a first end connected to the switching element Q1 and the switching element Q2 via the resonance capacitor C5. In other words, the first end of the primary coil TL11 is connected to the node N1 via the resonance capacitor C5. The second end of the primary side coil TL11 is connected to the node N3, and is connected to the switching element Q3 and the switching element Q4 via the series reactor L1. That is, the second end of the primary side coil TL11 is connected to the node N2 via the series reactor L1.

In the present embodiment, as an example, the primary coil TL11 is described as being indirectly connected to the full bridge circuit 20 via the resonance capacitor C5, but directly without using the resonance capacitor C5. It may be connected to the full bridge circuit 20.
The series reactor L1 is connected in series with the primary side coil TL11, and realizes ZVS (Zero Voltage Switching) operation of the switching elements Q1 to Q4 by resonance with the parasitic capacitances C1 to C4 and the wiring capacitance.

  The secondary side coils (TL12, TL13) are insulated from the primary side coil TL11. The first end of the secondary side coil TL13 is connected to the node N4, and the second end is connected to the first end of the secondary side coil TL12. The second end of the secondary coil TL12 is connected to the node N5. The secondary side coils (TL12, TL13) have a center tap (second end of the secondary side coil TL13 and first end of the secondary side coil TL12), and the center tap is connected to the node N6. . The center tap is connected to the choke coil L2. Further, the secondary side coils (TL12, TL13) are connected to a synchronous rectification circuit 30 described later.

The diode D5 has an anode terminal connected to the node N3 that is the first end of the primary coil TL11, and a cathode terminal connected to the power supply line VI. The diode D5 functions as a clamp diode.
The diode D6 has an anode terminal connected to the power supply line GND1 and a cathode terminal connected to the node N3 that is the first end of the primary coil TL11. The diode D5 functions as a clamp diode.

  The synchronous rectifier circuit 30 includes switching elements (Q5, Q6), parasitic capacitances (C6, C7), and body diodes (D7, D8). That is, the synchronous rectifier circuit 30 includes a switching element Q5 and a switching element Q6, and the two switching elements (Q5, Q6) are connected to the secondary side coils (TL12, TL13).

  The switching element Q5 (an example of a fifth switching element) has a drain terminal connected to the node N4 that is the first end of the secondary coil TL13, a source terminal connected to the output power line GND2, and a gate terminal connected to the signal of the drive signal G5. Each is connected to a line. That is, the switching element Q5 is connected between the power supply line GND2 and the first end (node N4) of the secondary coil TL13. Further, the switching element Q5 has a parasitic capacitance C6 and a body diode D7 between the drain terminal and the source terminal.

The switching element Q6 (an example of a sixth switching element) has a drain terminal connected to the node N5 that is the second end of the secondary coil TL12, a source terminal connected to the output power line GND2, and a gate terminal connected to the signal of the drive signal G6. Each is connected to a line. That is, the switching element Q6 is connected between the power supply line GND2 and the second end (node N5) of the secondary coil TL12. Further, the switching element Q6 has a parasitic capacitance C7 and a body diode D8 between the drain terminal and the source terminal.
The drive signal G5 is a control signal for controlling the switching element Q5, and the drive signal G6 is a control signal for controlling the switching element Q6.

  The choke coil L2 has a first end connected to a node N6 connected to the center tap of the secondary side coils (TL12, TL13), and a second end connected to the output power line VO. The choke coil L2 is used for smoothing the DC power output from the DC / DC converter 10 together with a smoothing capacitor Co described later.

The smoothing capacitor Co is connected between the output power supply line VO and the power supply line GND2, and smoothes the output voltage.
Here, the load RL indicates a load that consumes DC power output from the DC / DC converter 10.
The voltage detection unit 12 performs level conversion to compare the output voltage of the DC / DC converter 10 with the reference voltage Vref, and outputs a signal Vo to the control unit 13.

  The control unit 13 is a processor including, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), and the like, and turns on / off the switching elements Q1 to Q6 included in the full bridge circuit 20 and the synchronous rectification circuit 30. Control. That is, the control unit 13 turns on the switching element Q1, the switching element Q2, the switching element Q3, and the switching element Q4 included in the full bridge circuit 20, and the switching element Q5 and the switching element Q6 included in the synchronous rectifier circuit 30. The state (conducting state) and the OFF (off) state (non-conducting state) are controlled.

For example, the control unit 13 controls the switching element Q1 and the switching element Q2 connected to the first end of the primary coil TL11 with a predetermined duty (predetermined fixed duty) and controls the switching element Q1 of the primary coil TL11. The switching elements Q3 and Q4 connected to the two ends are controlled by PWM (pulse width modulation). Based on the reference voltage Vref and the signal Vo that is a feedback voltage signal output from the voltage detection unit 12, the control unit 13 changes the ON-state pulse widths of the switching element Q3 and the switching element Q4.
Further, for example, the control unit 13 performs control to turn on the switching elements Q5 and Q6 for at least a predetermined period (for example, a period Δt described later) immediately before the switching element Q3 or the switching element Q4 is turned off. Here, the control unit 13 turns on the switching element Q5 and the switching element Q6 for a predetermined period (period Δt) at least during a light load.

  Specifically, the control unit 13 sets the switching element Q5 so that the period of the switching element Q5 in the OFF state (off state) includes a part of the period in which the switching element Q4 is in the ON state (on state). Is turned off (turned off), and the switching element Q5 is turned on (turned on) before a predetermined period (period Δt) when the switching element Q4 is turned off. In addition, the control unit 13 sets the switching element Q6 to the OFF state (turns off) so that the period in which the switching element Q6 is in the OFF state includes a part of the period in which the switching element Q3 is in the ON state. The switching element Q6 is turned on (turned on) before the predetermined period (period Δt) when the switching element Q3 is turned off.

  As described above, the control unit 13 turns on both the switching element Q5 and the switching element Q6 for a predetermined period immediately before turning off the switching element Q3 or the switching element Q4, and the secondary coil (TL12, TL13). Both ends (node N4 and node N5) are short-circuited. The controller 13 temporarily increases the regenerative current flowing through the primary coil TL11 by short-circuiting both ends (node N4 and node N5) of the secondary coil (TL12, TL13). Here, the predetermined period (period Δt) is determined such that a current that pulls out the charges charged in the parasitic capacitors C1 to C4 of the switching elements Q1 to Q4 included in the full bridge circuit 20 is generated.

The driver unit 40 outputs signals for controlling the switching element Q1, the switching element Q2, the switching element Q3, the switching element Q4, the switching element Q5, and the switching element Q6 output from the control unit 13 for driving each switching element. It converts into a voltage and supplies it to the gate terminal of each switching element. That is, the driver unit 40 outputs the drive signals G1 to G6 based on the control signal generated by the control unit 13. Details of the drive signals G1 to G6 generated by the control unit 13 and the driver unit 40 will be described later with reference to FIG.
The driver unit 40 includes, for example, drivers 41 to 46. In addition, since the DC / DC converter 10 of this embodiment is insulated with the transformer TL1, it is necessary to insulate with the control part 13 or the driver part 40.

The driver 41 supplies a drive signal G1 for driving the switching element Q1 to the gate signal of the switching element Q1 based on the control signal of the switching element Q1 output from the control unit 13.
The driver 42 supplies a drive signal G2 for driving the switching element Q2 to the gate signal of the switching element Q2 based on the control signal of the switching element Q2 output from the control unit 13.
The driver 43 supplies a drive signal G3 for driving the switching element Q3 to the gate signal of the switching element Q3 based on the control signal of the switching element Q3 output from the control unit 13.

The driver 44 supplies a drive signal G4 for driving the switching element Q4 to the gate signal of the switching element Q4 based on the control signal of the switching element Q4 output from the control unit 13.
The driver 45 supplies a drive signal G5 for driving the switching element Q5 to the gate signal of the switching element Q5 based on the control signal for the switching element Q5 output from the control unit 13.
The driver 46 supplies a drive signal G6 for driving the switching element Q6 to the gate signal of the switching element Q6 based on the control signal for the switching element Q6 output from the control unit 13.

Here, with reference to FIG. 2, the control (drive signals G1 to G6) of the DC / DC converter 10 according to the present embodiment will be described.
FIG. 2 is a time chart showing an example of control of the DC / DC converter 10 according to the present embodiment.
In this figure, each of the waveforms W1 to W6 indicates the voltage waveform of the drive signals G1 to G6 in order from the top. In this figure, the horizontal axis indicates time, and the vertical axis indicates the logical level.

  At time T1, the control unit 13 first sets the drive signal G1 of the switching element Q1 and the drive signal G4 of the switching element Q4 to the H (High) state, and sets the drive signal G5 of the switching element Q5 to L (Low: Low). ) State. At time T1, the control unit 13 sets the drive signal G2 of the switching element Q2 and the drive signal G3 of the switching element Q3 in the L state in advance, and sets the drive signal G6 of the switching element Q6 in the H state in advance.

Thereby, the switching element Q1, the switching element Q4, and the switching element Q6 are turned on, and the switching element Q2, the switching element Q3, and the switching element Q5 are turned off. As a result, a current flows from the power supply line VI through the path of the switching element Q1, the resonance capacitor C5, the primary side coil TL11, the series reactor L1, and the switching element Q4. As a result, electric power is generated from the primary coil TL11 to the secondary coil TL12. The synchronous rectifier circuit 30 connected to the secondary coil TL12 rectifies this power through the switching element Q6, and supplies the smoothed DC voltage to the power line via the choke coil L2 and the smoothing capacitor Co. Output to VO.
Further, the control unit 13 determines the pulse width of the drive signal G4 (H-state period DT2) so that the output signal Vo detected by the voltage detection unit 12 and the reference voltage Vref match, and the switching element Q4 Maintain the ON state. Further, the control unit 13 maintains the ON state of the switching element Q1 so that the ON state period (turn-on period) of the switching element Q1 becomes a predetermined duty (predetermined fixed duty).

  Next, at time T2, the control unit 13 sets the drive signal G5 to the H state and turns on the switching element Q5. Here, the control unit 13 sets the drive signal G5 to the H state before the period Δt immediately before setting the drive signal G4 to the L state. During this period Δt, both the switching element Q5 and the switching element Q6 are turned on, and both ends (node N4 and node N5) of the secondary coil (TL12, TL13) are short-circuited. As a result, the regenerative current flowing through the primary coil TL11 temporarily increases.

  Next, at time T3, the control unit 13 sets the drive signal G4 to the L state and sets the switching element Q4 to the OFF state. The period DT2 in which the switching element Q4 is ON varies depending on the output signal Vo and the current consumption of the load RL. That is, the control unit 13 controls the ON state period DT2 of the switching element Q4 by PWM (pulse width modulation).

  At time T4, the ON state period of the switching element Q1 reaches a predetermined duty, and the control unit 13 sets the drive signal G1 to the L state and turns the switching element Q1 to the OFF state. Here, the predetermined duty is, for example, a ratio (for example, 40%) of the ON state period DT1 in the period TT1, and is a predetermined conduction period (period DT1) per period (period TT1). It is a time ratio indicating a ratio (DT1 / TT1 × 100).

Next, at time T5, the control unit 13 first sets the drive signal G2 of the switching element Q2 and the drive signal G3 of the switching element Q3 to the H state, and sets the drive signal G6 of the switching element Q6 to the L state.
Thereby, the switching element Q2, the switching element Q3, and the switching element Q5 are turned on, and the switching element Q1, the switching element Q4, and the switching element Q6 are turned off. As a result, a current flows from the power line VI through the switching element Q3, the series reactor L1, the primary coil TL11, the resonance capacitor C5, and the switching element Q2. As a result, electric power is generated from the primary coil TL11 to the secondary coil TL12. The synchronous rectifier circuit 30 connected to the secondary coil TL13 rectifies this power via the switching element Q5, and supplies the smoothed DC voltage to the power line via the choke coil L2 and the smoothing capacitor Co. Output to VO.

  Further, the control unit 13 determines the pulse width (H-state period DT4) of the drive signal G3 so that the output signal Vo detected by the voltage detection unit 12 and the reference voltage Vref match, and the switching element Q3 Maintain the ON state. Further, the control unit 13 maintains the ON state of the switching element Q2 so that the ON state period (turn-on period) of the switching element Q2 becomes a predetermined duty (predetermined fixed duty).

  Next, at time T6, the control unit 13 sets the drive signal G6 to the H state and turns on the switching element Q6. Here, the control unit 13 sets the drive signal G6 to the H state before the period Δt immediately before setting the drive signal G3 to the L state. During this period Δt, both the switching element Q5 and the switching element Q6 are turned on, and both ends (node N4 and node N5) of the secondary coil (TL12, TL13) are short-circuited. As a result, the regenerative current flowing through the primary coil TL11 temporarily increases.

Next, at time T7, the control unit 13 sets the drive signal G3 to the L state and turns the switching element Q3 to the OFF state. The period DT4 of the ON state of the switching element Q3 varies depending on the output signal Vo and the current consumption of the load RL. That is, the control unit 13 controls the period DT2 of the ON state of the switching element Q3 by PWM (pulse width modulation).
Further, at time T8, the ON period of the switching element Q2 reaches a predetermined duty, and the control unit 13 sets the drive signal G2 to the L state and turns the switching element Q2 to the OFF state.

  The subsequent processing from time T9 to time T17 is the same as the processing from time T1 to time T9 described above, and therefore description thereof is omitted here.

Next, the configuration and operation of the control unit 13 according to the present embodiment will be described with reference to the drawings.
FIG. 3 is a block diagram illustrating an example of the control unit 13 according to the present embodiment.
In the present embodiment, an example will be described in which the control unit 13 includes the delay adjustment unit 50 and the delay adjustment unit 50 adjusts the signal delay of the drive signals G1 to G6.

As shown in FIG. 3, the control unit 13 includes a control signal generation unit 130, inverter circuits (131, 132), and a delay adjustment unit 50.
The control signal generation unit 130 generates various control signals for controlling the drive signals G1 to G6. For example, the control signal generation unit 130 generates a carrier signal having a predetermined frequency serving as a reference inside, and generates various control signals S1 to S4 based on the carrier signal.

For example, the control signal generation unit 130 generates a signal S1 for generating the drive signal G1 and a signal S2 for generating the drive signal G2. Here, the signal S1 and the signal S2 are signals having a predetermined duty.
For example, the control signal generation unit 130 generates a signal S3 for generating the drive signal G3 and the drive signal G6, and a signal S4 for generating the drive signal G4 and the drive signal G5. The signals S3 and S4 are signals whose pulse width is controlled by PWM. For example, the control signal generation unit 130 generates a signal S3 and a signal S4 in which the PWM pulse width is changed based on the reference voltage Vref and the signal Vo that is a feedback voltage signal. For example, the control signal generation unit 130 changes the pulse widths of the signal S3 and the signal S4 based on PID (Proportional-Integral-Derivative) control. Here, when the load RL is heavy (large), the control signal generator 130 increases the pulse widths of the signals S3 and S4, and when the load RL is light (small) (light load), the signal S3 , And the pulse width of the signal S4 is shortened.

The inverter circuit 131 is, for example, a logic inversion circuit, and outputs a signal S5 obtained by logically inverting the signal S4 to the driver 45 using the signal S4 as an input signal. The driver 45 outputs a drive signal G5 based on the signal S5.
The inverter circuit 132 is, for example, a logic inversion circuit, and outputs a signal S6 obtained by logically inverting the signal S3 to the driver 46 using the signal S3 as an input signal. The driver 46 outputs a drive signal G6 based on the signal S6.

The delay adjusting unit 50 delays the drive signal G4 of the switching element Q4 so that the switching element Q4 is turned off with a delay of a period Δt from the timing when the switching element Q5 is turned on. That is, the delay adjustment unit 50 generates a signal S42 obtained by delaying the signal S4 by the period Δt, and outputs the signal S42 to the driver 44. The driver 44 outputs a drive signal G4 based on the signal S42.
Further, the delay adjusting unit 50 delays the drive signal G3 of the switching element Q3 so that the switching element Q3 is turned OFF with a delay of the period Δt from the timing when the switching element Q6 is turned ON. That is, the delay adjustment unit 50 generates a signal S32 obtained by delaying the signal S3 by the period Δt, and outputs the signal S32 to the driver 43. The driver 43 outputs a drive signal G3 based on the signal S32.

Further, the delay adjusting unit 50 delays the drive signal G1 so that the timing at which the switching element Q1 is turned on is delayed by a period Δt as in the case of the drive signal G4. That is, the delay adjustment unit 50 generates a signal S12 obtained by delaying the signal S1 by the period Δt, and outputs the signal S12 to the driver 41. The driver 41 outputs a drive signal G1 based on the signal S12.
Further, the delay adjusting unit 50 delays the drive signal G2 so that the timing at which the switching element Q2 is turned on is delayed by a period Δt, similarly to the drive signal G3. That is, the delay adjustment unit 50 generates a signal S22 obtained by delaying the signal S2 by the period Δt, and outputs the signal S22 to the driver 42. The driver 42 outputs a drive signal G2 based on the signal S22.

  The delay adjustment unit 50 includes a buffer circuit (511, 514, 521, 524, 531, 534, 541, 544), a resistor (512, 522, 532, 542), and a capacitor (513, 523, 533, 543). ).

The buffer circuit 511 has an input terminal connected to the signal line of the signal S1 and an output terminal connected to the first end of the resistor 512, and outputs a signal in phase with the input S1.
The resistor 512 has a first end connected to the output terminal of the buffer circuit 511 and a second end connected to the node N7. Capacitor 513 has a first end connected to node N7 and a second end connected to power supply line GND1. The resistor 512 and the capacitor 513 constitute an RC circuit.
The buffer circuit 514 has an input terminal connected to the node N7 and an output terminal connected to the input terminal of the driver 41, and outputs a signal S12.
As described above, the buffer circuits (511, 514), the resistor 512, and the capacitor 513 constitute a delay circuit that outputs the signal S12 obtained by delaying the signal S1 by the period Δt. Here, the period Δt, which is a delay value, is determined by the time constant of the resistor 512, the resistance value, and the capacitance value of the capacitor 513.

The buffer circuit 521 has an input terminal connected to the signal line of the signal S2 and an output terminal connected to the first end of the resistor 522, and outputs a signal in phase with the input S2.
The resistor 522 has a first end connected to the output terminal of the buffer circuit 521 and a second end connected to the node N8. Capacitor 523 has a first end connected to node N8 and a second end connected to power supply line GND1. Note that the resistor 522 and the capacitor 523 constitute an RC circuit.
The buffer circuit 524 has an input terminal connected to the node N8 and an output terminal connected to the input terminal of the driver 42, and outputs a signal S22.
Thus, the buffer circuits (521, 524), the resistor 522, and the capacitor 523 constitute a delay circuit that outputs the signal S22 obtained by delaying the signal S2 by the period Δt.

The buffer circuit 531 has an input terminal connected to the signal line of the signal S3 and an output terminal connected to the first end of the resistor 532, and outputs a signal in phase with the input S3.
The resistor 532 has a first end connected to the output terminal of the buffer circuit 531 and a second end connected to the node N9. Capacitor 533 has a first end connected to node N9 and a second end connected to power supply line GND1. Note that the resistor 532 and the capacitor 533 constitute an RC circuit.
Buffer circuit 534 has its input terminal connected to node N9 and its output terminal connected to the input terminal of driver 43, and outputs signal S32.
As described above, the buffer circuits (531, 534), the resistor 532, and the capacitor 533 constitute a delay circuit that outputs the signal S32 obtained by delaying the signal S3 by the period Δt.

The buffer circuit 541 has an input terminal connected to the signal line of the signal S4 and an output terminal connected to the first end of the resistor 542, and outputs a signal in phase with the input S4.
The resistor 542 has a first end connected to the output terminal of the buffer circuit 541 and a second end connected to the node N10. Capacitor 543 has a first end connected to node N10 and a second end connected to power supply line GND1. Note that the resistor 542 and the capacitor 543 constitute an RC circuit.
The buffer circuit 544 has an input terminal connected to the node N10 and an output terminal connected to the input terminal of the driver 44, and outputs a signal S42.
Thus, the buffer circuits (541, 544), the resistor 542, and the capacitor 543 constitute a delay circuit that outputs the signal S42 obtained by delaying the signal S4 by the period Δt.

Next, the operation of the control unit 13 described above will be described with reference to FIG.
FIG. 4 is a time chart showing an example of control by the control unit 13 shown in FIG.
In this figure, each signal of the waveforms W11 to W22 indicates signals S1 to S6 and drive signals G1 to G6 in order from the top. The waveforms of the drive signals G1 to G4 are the same as the signals S12, S22, S32, and S42 in order from the top.
In this figure, the horizontal axis indicates time, and the vertical axis indicates the logical level.

  First, in the initial state, the control signal generation unit 130 of the control unit 13 sets the signals S1 to S4 to the L state, and the driver unit 40 sets the drive signals G1 to G4 to the L state, the drive signal G5 and the drive signal G6. Assume that it is in the H state.

  Next, at time T21, the control signal generator 130 sets the signal S1 and the signal S4 to the H state (see the waveform W11 and the waveform W14). Inverter circuit 131 sets signal S5 to the L state based on signal S4 (see waveform W15). As a result, the driver 45 sets the drive signal G5 to the L state based on the signal S5.

  Next, at time T22, the delay adjusting unit 50 sets the signal S12 and the signal S42 delayed by the period Δt based on the signal S1 and the signal S4 to the H state (see the waveform W17 and the waveform W20). Here, the buffer circuits (511, 514), the resistor 512, and the capacitor 513 delay the signal S1 by a period Δt and set the signal S12 to the H state. In addition, the buffer circuits (541, 544), the resistor 542, and the capacitor 543 delay the signal S4 by a period Δt and set the signal S42 to the H state. As a result, the driver 41 sets the drive signal G1 to the H state based on the signal S12, and the driver 44 sets the drive signal G4 to the H state based on the signal S42.

  Next, at time T23, the control signal generation unit 130 sets the signal S4 to the L state by PWM (see waveform W14). Thereby, inverter circuit 131 sets signal S5 to the H state based on signal S4 (see waveform W15). As a result, the driver 45 sets the drive signal G5 to the H state based on the signal S5.

Next, at time T24, the delay adjustment unit 50 sets the signal S42 delayed by the period Δt based on the signal S4 to the L state (see waveform W20). Here, the buffer circuits (541, 544), the resistor 542, and the capacitor 543 delay the signal S4 by a period Δt and set the signal S42 to the L state. As a result, the driver 44 sets the drive signal G4 to the L state based on the signal S42.
In this way, the control unit 13 sets the drive signal G5 and the drive signal G6 to the H state for the period Δt before setting the drive signal G4 to the L state (turning off the switching element Q4). As a result, the switching element Q4, the switching element Q5, and the switching element Q6 are all turned on during the period Δt from time T23 to time T24.

Next, at time T25, the control signal generation unit 130 sets the signal S1 to the L state with a fixed duty (see the waveform W11).
Next, at time T26, the delay adjustment unit 50 sets the signal S12 delayed by the period Δt based on the signal S1 to the L state (see waveform W17). Here, the buffer circuits (511, 514), the resistor 512, and the capacitor 513 delay the signal S1 by a period Δt and set the signal S12 to the L state. As a result, the driver 41 sets the drive signal G1 to the L state based on the signal S12.

  Next, at time T27, the control signal generation unit 130 sets the signal S2 and the signal S3 to the H state (see the waveform W12 and the waveform W13). Inverter circuit 132 sets signal S6 to the L state based on signal S3 (see waveform W16). As a result, the driver 46 sets the drive signal G6 to the L state based on the signal S6.

  Next, at time T28, the delay adjusting unit 50 sets the signal S22 and the signal S32 delayed by the period Δt based on the signal S2 and the signal S3 to the H state (see the waveform W18 and the waveform W19). Here, the buffer circuits (521, 524), the resistor 522, and the capacitor 523 delay the signal S2 by a period Δt and set the signal S22 to the H state. In addition, the buffer circuits (531, 534), the resistor 532, and the capacitor 533 delay the signal S3 by a period Δt and set the signal S32 to the H state. As a result, the driver 42 sets the drive signal G2 to the H state based on the signal S22, and the driver 43 sets the drive signal G3 to the H state based on the signal S43.

  Next, at time T29, the control signal generation unit 130 sets the signal S3 to the L state by PWM (see waveform W13). Thus, inverter circuit 132 sets signal S6 to the H state based on signal S3 (see waveform W16). As a result, the driver 46 sets the drive signal G6 to the H state based on the signal S6.

Next, at time T30, the delay adjustment unit 50 sets the signal S32 delayed by the period Δt based on the signal S3 to the L state (see waveform W19). Here, the buffer circuits (531, 534), the resistor 532, and the capacitor 533 delay the signal S3 by a period Δt and set the signal S32 to the L state. As a result, the driver 43 sets the drive signal G3 to the L state based on the signal S32.
In this way, the control unit 13 sets the drive signal G5 and the drive signal G6 to the H state during the period Δt before setting the drive signal G3 to the L state (turning off the switching element Q3). As a result, the switching element Q3, the switching element Q5, and the switching element Q6 are all turned on during the period Δt from time T29 to time T30.

Next, at time T31, the control signal generation unit 130 sets the signal S2 to the L state with a fixed duty (see waveform W12).
Next, at time T32, the delay adjustment unit 50 sets the signal S22 delayed by the period Δt based on the signal S2 to the L state (see waveform W18). Here, the buffer circuits (521, 524), the resistor 522, and the capacitor 523 delay the signal S2 by a period Δt and set the signal S22 to the L state. As a result, the driver 42 sets the drive signal G2 to the L state based on the signal S22.

  As described above, the control unit 13 includes the delay adjustment unit 50 including the RC circuit, and the delay adjustment unit 50 generates the delay signal, thereby generating the drive signals G1 to G6 as illustrated in FIG.

Next, with reference to FIG. 5 and FIG. 6, the operation at the time of light load of the power supply device 1 according to the present embodiment will be described.
Here, first, for comparison, the operation of a conventional power supply device at a light load will be described with reference to FIG.

FIG. 5 is a time chart showing the operation of the conventional power supply device at a light load.
In this figure, each signal of the waveforms W31 to W38 indicates the drive signals G1 to G6, the drain-source voltage Vds of the switching element Q2, and the drain-source current Ids of the switching element Q2 in order from the top. Yes. The waveform V37 of the voltage Vds and the waveform W38 of the current Ids are simulation waveforms.
In this figure, the horizontal axis indicates time, and the vertical axis indicates drive signals G1 to G6 indicate logic levels, voltage Vds indicates voltage, and current Ids indicates current. In the initial state, the drive signal G1, the drive signal G4, and the drive signal G6 are in the H state, and the drive signals G2 to G4 are in the L state.

  As shown in FIG. 5, in the conventional power supply device, the drive signal G1 is set to the L state at time T41, the drive signal G2 and the drive signal G3 are set to the H state at time T42, and the drive signal G6 is set to L. Put into a state. Further, at time T43, the drive signal G3 is set to the L state by PWM, and at time T44, the drive signal G6 is set to the H state. At time T45, the drive signal G2 is set to the L state. At time T46, the drive signal G1 and the drive signal G4 are set to the H state, and the drive signal G5 is set to the L state.

  In the conventional power supply apparatus that performs such control, the ZVS operation is not performed and the switching element Q2 and the switching are performed at the time of light load, as indicated by the waveform W37 from time T41 to time T42 and from time T45 to time T46. Element Q3 (switching element Q1 and switching element Q4) is turned on. Therefore, at time T42 and time T46, as shown by the waveform W38, a through current that is an excessive current flows to the switching element Q2. This is because the load is light and, for example, the current I1 flowing through the switching element Q2 is small. Therefore, the ZVS operation may not be performed without pulling out the charges charged in the parasitic capacitors C1 to C4 of the switching elements Q1 to Q4. The main cause. Note that when the switching elements Q1 to Q4 are, for example, super junction FETs (field effect transistors), the lower the voltage Vds, the greater the parasitic capacitance tends to increase. The flowing problem appears prominently.

On the other hand, in the power supply device 1 according to the present embodiment, no through current is generated as shown in FIG.
FIG. 6 is a time chart showing an example of the operation of the power supply device 1 according to the present embodiment at a light load.
In this figure, the signals of the waveforms W41 to W48 indicate the drive signals G1 to G6, the drain-source voltage Vds of the switching element Q2, and the drain-source current Ids of the switching element Q2 in order from the top. Yes. Note that the waveform V47 of the voltage Vds and the waveform W48 of the current Ids are simulation waveforms.
In this figure, the horizontal axis indicates time, and the vertical axis indicates drive signals G1 to G6 indicate logic levels, voltage Vds indicates voltage, and current Ids indicates current. In the initial state, the drive signal G1, the drive signal G4, and the drive signal G6 are in the H state, and the drive signals G2 to G4 are in the L state.

  As shown in FIG. 6, the power supply device 1 according to the present embodiment sets the drive signal G1 to the L state at time T51, sets the drive signal G2 and the drive signal G3 to the H state at time T52, and sets the drive signal G6 to the drive signal G6. Set to L state. At time T53, the power supply device 1 sets the drive signal G6 to the H state, and at time T54, sets the drive signal G3 to the L state by PWM.

  Here, during a period Δt from time T53 to time T54, the power supply device 1 sets the drive signal G5 and the drive signal G6 to the H state, and short-circuits both ends (node N4 and node N5) of the secondary side coils (TL12 and TL13). Let As a result, the regenerative current increases, and the current I2 flows through the current Ids of the switching element Q2 as shown by the waveform W48. This current I2 is larger than current I1 in the case of the conventional power supply device shown in FIG. Further, the period Δt is determined so as to draw out the charges charged in the parasitic capacitors C1 to C4 of the switching elements Q1 to Q4 by the current I2.

  At time T55, the power supply device 1 sets the drive signal G2 to the L state. At time T56, the drive signal G1 and the drive signal G4 are set to the H state, and the drive signal G5 is set to the L state. Here, since the charges charged in the parasitic capacitances C1 to C4 of the switching elements Q1 to Q4 are extracted and the ZVS operation becomes possible, in the power supply device 1, the through current does not flow to the switching element Q2 at time T56. . Similarly, at time T52, since the ZVS operation is possible, in the power supply device 1, the through current does not flow to the switching element Q2.

  The operation shown in FIG. 6 is the same for the other switching elements (Q1, Q3, Q4). Thus, the power supply device 1 causes an excessive current (through through) to the switching elements Q1 to Q4 at a light load. Current) can be prevented from flowing.

  As described above, the power supply device 1 according to the present embodiment includes the DC / DC converter 10, and the DC / DC converter 10 includes the full bridge circuit 20, the transformer TL1, the synchronous rectifier circuit 30, and the full bridge circuit. 20 and the control part 13 which controls on / off of the switching elements Q1-Q6 which the synchronous rectifier circuit 30 has. The full bridge circuit 20 includes a switching element Q1 (first switching element) and a switching element Q2 (second switching element) connected in series, and a switching element Q3 (third switching element) and a switching element Q4 (fourth switching element). Are connected in series, and the four switching elements are bridge-connected. The transformer TL1 includes a primary coil TL11 to which the full bridge circuit 20 is connected directly or indirectly, and secondary coils (TL12, TL13) insulated from the primary coil TL11. The synchronous rectifier circuit 30 includes a switching element Q5 (fifth switching element) and a switching element Q6 (sixth switching element), and the two switching elements are connected to the secondary side coils (TL12, TL13). It is the structure which was made. The control unit 13 controls the switching element Q1 and the switching element Q2 connected to the first end of the primary side coil TL11 with a predetermined fixed duty and the switching connected to the second end of the primary side coil TL11. The element Q3 and the switching element Q4 are controlled by pulse width modulation. Further, the control unit 13 turns on the switching element Q5 and the switching element Q6 at least for a predetermined period (for example, the period Δt) immediately before the switching element Q3 or the switching element Q4 is turned off.

  Thereby, the power supply device 1 according to the present embodiment turns on both the switching element Q5 and the switching element Q6 for the predetermined period, thereby causing both ends (nodes N4 and TL13) of the secondary side coils (TL12, TL13) to turn on. By short-circuiting the node N5), the regenerative current flowing in the primary coil TL11 is temporarily increased. Therefore, the power supply device 1 according to the present embodiment can discharge the charges charged in the parasitic capacitors C1 to C4 of the switching elements Q1 to Q4 on the primary side even at a light load, thereby enabling a ZVS operation. Therefore, the power supply device 1 according to the present embodiment can prevent an excessive current (through current) from flowing through the switching elements Q1 to Q4 at a light load.

In this embodiment, the control unit 13 determines that the switching element Q5 is in the OFF state period (for example, the period from time T1 to time T2 in FIG. 2) and the switching element Q4 is in the ON state (for example, FIG. 2). The switching element Q5 is turned off so as to include a part of the period DT2), and the switching element Q5 is turned on before a predetermined period (period Δt) when the switching element Q4 is turned off. That is, the control unit 13 turns off the switching element Q4 after a predetermined period (period Δt) after turning on the switching element Q5. Further, the control unit 13 determines that the period during which the switching element Q6 is in the OFF state (for example, the period from time T5 to time T6 in FIG. 2) is the period during which the switching element Q3 is in the ON state (for example, the period DT4 in FIG. 2). The switching element Q6 is turned off so as to include a part of the period, and the switching element Q6 is turned on before a predetermined period (period Δt) when the switching element Q3 is turned off. That is, the control unit 13 turns off the switching element Q3 after a predetermined period (period Δt) after turning on the switching element Q6.
Thereby, the power supply device 1 according to the present embodiment can turn on both the switching element Q5 and the switching element Q6 for a predetermined period (period Δt) by a simple method.

In the present embodiment, the control unit 13 turns on the switching element Q5 and the switching element Q6 for a predetermined period (period Δt) at least during light load.
As a result, the power supply device 1 according to the present embodiment can reliably perform the ZVS operation at the time of light load, and prevents an excessive current (through current) from flowing through the switching elements Q1 to Q4 at the time of light load. be able to.
In the present embodiment, the control unit 13 performs the same control at a light load and at a normal load when the load is larger than that at the light load. In other words, the power supply device 1 according to the present embodiment can prevent an excessive current (through current) from flowing through the switching elements Q1 to Q4 at light load without changing control between light load and normal load. Can be prevented.

In the present embodiment, the control unit 13 includes a delay adjustment unit 50. The delay adjustment unit 50 delays the control signal (driving signal G4) of the switching element Q4 so that the switching element Q4 is turned off after a predetermined period (period Δt) from the timing when the switching element Q5 is turned on. Further, the delay adjusting unit 50 delays the control signal (drive signal G3) of the switching element Q3 so that the switching element Q3 is turned off after a predetermined period (period Δt) from the timing when the switching element Q6 is turned on.
Thereby, the power supply device 1 according to the present embodiment can prevent an excessive current (through current) from flowing through the switching elements Q1 to Q4 at a light load by a simple configuration including the delay adjusting unit 50. it can.

In the present embodiment, in a predetermined period (period Δt), a current (regenerative current) that pulls out the charges charged in the parasitic capacitors C1 to C4 of the switching elements Q1 to Q4 included in the full bridge circuit 20 is generated. It has been established.
Thereby, the power supply device 1 according to the present embodiment can appropriately discharge the charges charged in the parasitic capacitances C1 to C4 of the switching elements Q1 to Q4 on the primary side at the time of light load, thereby enabling the ZVS operation. Become.

The power control method according to the present embodiment is a power control method for the power supply device 1 including the DC / DC converter 10. In this power supply control method, the control unit 13 controls the switching element Q1 and the switching element Q2 connected to the first end of the primary side coil TL11 with a predetermined fixed duty, and at the second end of the primary side coil TL11. The connected switching element Q3 and switching element Q4 are controlled by PWM (pulse width modulation). Then, the control unit 13 turns on the switching element Q5 and the switching element Q6 for at least a predetermined period (for example, the period Δt) before the switching element Q3 or the switching element Q4 is turned off.
Thereby, the power supply control method according to the present embodiment can discharge the charges charged in the parasitic capacitances C1 to C4 of the switching elements Q1 to Q4 on the primary side even at a light load, thereby enabling a ZVS operation. Therefore, the power supply control method according to the present embodiment can prevent an excessive current (through current) from flowing through the switching elements Q1 to Q4 at light load.

The present invention is not limited to the above embodiments, and can be modified without departing from the spirit of the present invention.
For example, in the above embodiment, the control unit 13 has described an example in which the same control is performed at a light load and at a normal load, but different control is performed by switching between a light load and a normal load. You may do it. In this case, for example, in FIG. 3, the drive signals G1 to G4 are output based on the signals S12 to S42 at a light load, and based on the signals S1 to S4 before being delayed by the delay adjustment unit 50 at the normal load. It may be switched and controlled to output the drive signals G1 to G4.
As described above, the control unit 13 switches and performs different control between the light load and the normal load, so that the power supply device 1 increases the conversion efficiency at the normal load, and the switching element at the light load. It is possible to prevent an excessive current (through current) from flowing through Q1 to Q4.

In the above embodiment, the delay adjustment unit 50 illustrated in FIG. 3 has been described as an example. However, the present invention is not limited to this. For example, the control unit 13 may include a delay adjustment unit 50a as shown in FIG.
FIG. 7 is a block diagram illustrating another example of the delay adjustment unit 50a according to the present embodiment.
7, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted. In the example shown in this figure, the delay adjustment unit 50a includes a buffer circuit (511, 514, 521, 524, 531, 534, 541, 544), a resistor (512, 522, 532, 542), and a capacitor (513, 523, 533, 543) and OR circuits (515, 525, 535, 545).

The OR circuit 515 is a logical sum circuit, and outputs a signal S12 obtained by logically summing the signal S1 and the output signal of the buffer circuit 514. The OR circuit 515 outputs a signal S12 having a rising timing similar to that of the signal S1 and delayed by a period Δt from the signal S1 only at the falling timing.
The OR circuit 525 is a logical sum circuit, and outputs a signal S22 obtained by logically summing the signal S2 and the output signal of the buffer circuit 524. The OR circuit 525 outputs a signal S22 that has a rising timing similar to that of the signal S2 and is delayed by a period Δt from the signal S2 only at the falling timing.

The OR circuit 535 is a logical sum circuit, and outputs a signal S32 obtained by logically summing the signal S3 and the output signal of the buffer circuit 534. The OR circuit 535 outputs a signal S32 that has a rising timing similar to that of the signal S3 and is delayed by a period Δt from the signal S3 only at the falling timing.
The OR circuit 545 is a logical sum circuit, and outputs a signal S42 obtained by logically summing the signal S4 and the output signal of the buffer circuit 544. The OR circuit 545 outputs a signal S42 that has a rising timing similar to that of the signal S4 and is delayed by a period Δt from the signal S4 only at the falling timing.
As described above, the control unit 13 includes the delay adjustment unit 50a, so that the control shown in FIG. 2 described above can be executed.
In the example illustrated in FIG. 7 described above, the delay adjusting unit 50a has described the example in which the falling timings of the signal S1 and the signal S2 are delayed by the period Δt, but the present invention is not limited to this. For example, the delay adjustment unit 50a may output the signal S1 and the signal S2 directly to the driver unit 40 and delay only the falling timing of the signal S3 and the signal S4 by the period Δt. Also in this case, the control unit 13 can execute the same control as the control shown in FIG. 2 described above.

  In the above embodiment, the control unit 13 controls the switching element Q3 and the switching element Q4 by PWM. However, the control unit 13 controls the switching element Q3 and the switching element Q4 by PWM in the current control mode. Also good. Further, the power supply device according to the present invention may be, for example, a three-phase control power supply device 1a as shown in FIG.

FIG. 8 is a block diagram illustrating an example of a three-phase control power supply device 1a according to the present embodiment.
The power supply device 1a shown in this figure outputs a predetermined DC voltage from a three-phase AC power supply (R, S, T). The power supply device 1 includes PFC (Power Factor Correction) units 2-1 to 2-3 and DC / DC converters 10-1 to 10-3.
The PFC unit 2-1 is a U-phase PFC circuit, the PFC unit 2-2 is a V-phase PFC circuit, and the PFC unit 2-3 is a W-phase PFC circuit. In this figure, the PFC units 2-1 to 2-3 have the same configuration, and are, for example, power factor correction circuits. The PFC units 2-1 to 2-3 remove high-frequency current components, convert the input AC power into DC power, and output the DC power.

The DC / DC converters 10-1 to 10-3 have the same configuration as the DC / DC converter 10 described above. The DC / DC converter 10-1 converts the DC power converted from the U phase supplied from the PFC unit 2-1 into a predetermined DC voltage and outputs it. Further, the DC / DC converter 10-2 converts the DC power converted from the V phase supplied from the PFC unit 2-2 into a predetermined DC voltage and outputs it. Further, the DC / DC converter 10-3 converts the DC power converted from the W phase supplied from the PFC unit 2-3 into a predetermined DC voltage and outputs it.
The power supply device 1a includes the PFC units 2-1 to 2-3 and the DC / DC converters 10-1 to 10-3, thereby realizing a power supply device with high conversion efficiency. It is possible to prevent an excessive current (through current) from flowing through the switching elements Q1 to Q4. Furthermore, by applying PWM in the current control mode to the DC / DC converters 10-1 to 10-3, the power supply device 1a can balance the currents of the respective phases, so that the power conversion efficiency can be further improved. it can.

  Moreover, in said embodiment, although the DC / DC converter 10 demonstrated the structure provided with the series reactor L1, the resonant capacitor C5, and the diode (D5, D6) as an example, it is not limited to this. For example, the DC / DC converter 10 may be configured not to include some or all of the series reactor L1, the resonant capacitor C5, and the diodes (D5, D6).

Moreover, although the transformer TL1 has been described with the example including the secondary coil (TL12, TL13) with the center tap, the transformer TL1 may not have the center tap.
Further, although the example in which the synchronous rectifier circuit 30 is a double-wave rectifier circuit has been described, the present invention is not limited to this and may be a full-wave rectifier circuit such as a full bridge.
In the above embodiment, the control unit 13 controls the switching element Q1 and the switching element Q2 with a fixed duty of 40%. However, the control unit 13 is not limited to this and is controlled with another duty. You may make it do.

Further, in the above embodiment, the example in which the control signal generation unit 130 performs control by PWM based on PID control has been described, but the present invention is not limited to this, and is controlled by PWM by another control method. It may be.
In the above embodiment, the delay adjustment unit 50 (50a) is not limited to the circuit configuration shown in FIG. 3 (FIG. 7), and may be realized by other circuit configurations.

  In the above embodiment, the processing of each unit of the control unit 13 may be realized by dedicated hardware such as an IC (Integrated Circuit) or may be realized by software processing.

  The power supply device 1 (1a) described above has a computer system therein. The process of the control unit 13 described above is stored in a computer-readable recording medium in the form of a program, and the above process is performed by the computer reading and executing this program. Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

DESCRIPTION OF SYMBOLS 1, 1a Power supply device 2, 2-1, 2-2, 2-3 PFC part 10, 10-1, 10-2, 10-3 DC / DC converter 12 Voltage detection part 13 Control part 20 Full bridge circuit 30 Synchronization Rectifier circuit 40 Driver unit 41, 42, 43, 44, 45, 46 Driver 50, 50a Delay adjustment unit 130 Control signal generation unit 131, 132 Inverter circuit 511, 514, 521, 524, 531, 534, 541, 544 Buffer circuit 512, 522, 532, 542 Resistance 513, 523, 533, 543 Capacitor 515, 525, 535, 545 OR circuit C1, C2, C3, C4, C6, C7 Parasitic capacitance C5 Resonance capacitor Ci, Co Smoothing capacitor D1, D2, D3, D4, D7, D8 Body diode D5, D6 Diode L1 Series Reactor L2 Choke coil Q1, Q2, Q3, Q4, Q5, Q6 Switching element TL1 Transformer TL11 Primary coil TL12, TL13 Secondary coil RL Load

Claims (6)

A power supply device comprising a DC / DC converter,
The DC / DC converter is
A full-bridge circuit in which a first switching element and a second switching element are connected in series, a third switching element and a fourth switching element are connected in series, and the four switching elements are bridge-connected;
A transformer having a primary side coil to which the full bridge circuit is directly or indirectly connected, and a secondary side coil insulated from the primary side coil;
A synchronous rectifier circuit having a fifth switching element and a sixth switching element, the two switching elements being connected to the secondary coil;
A control unit that controls on / off of a switching element included in the full bridge circuit and the synchronous rectifier circuit;
The controller is
The first switching element and the second switching element connected to the first end of the primary side coil are controlled by a predetermined fixed duty, and the first switching element connected to the second end of the primary side coil is controlled. 3 switching elements and the fourth switching element are controlled by pulse width modulation,
The power supply device, wherein the fifth switching element and the sixth switching element are turned on for at least a predetermined period immediately before the third switching element or the fourth switching element is turned off. The controller is
The fifth switching element is turned off so that the period of the fifth switching element in the off state includes a part of the period in which the fourth switching element is in the on state. Before the predetermined period when the switching element is turned off, the fifth switching element is turned on,
The sixth switching element is turned off so that the period in which the sixth switching element is in the off state includes a part of the period in which the third switching element is in the on state. The power supply device according to claim 1, wherein the sixth switching element is turned on before the predetermined period when the switching element is turned off. 3. The power supply device according to claim 1, wherein the control unit turns on the fifth switching element and the sixth switching element for the predetermined period at least at a light load. 4. . The controller is
The control signal of the fourth switching element is delayed and the sixth switching element is turned on so that the fourth switching element is turned off after a predetermined period of time from the timing when the fifth switching element is turned on. The delay adjustment part which delays the control signal of a 3rd switching element so that a 3rd switching element may turn off after the said predetermined period from timing may be provided. The Claim 1 characterized by the above-mentioned. The power supply device according to one item. 5. The method according to claim 1, wherein the predetermined period is determined such that a current that pulls out a charge charged in a parasitic capacitance of the switching element included in the full bridge circuit is generated. The power supply device according to one item. A power supply control method for a power supply device including a DC / DC converter,
The DC / DC converter is
A full-bridge circuit in which a first switching element and a second switching element are connected in series, a third switching element and a fourth switching element are connected in series, and the four switching elements are bridge-connected;
A transformer having a primary side coil to which the full bridge circuit is directly or indirectly connected, and a secondary side coil insulated from the primary side coil;
A synchronous rectifier circuit having a fifth switching element and a sixth switching element, the two switching elements being connected to the secondary coil;
A control unit that controls on / off of a switching element included in the full bridge circuit and the synchronous rectifier circuit;
The control unit is
The first switching element and the second switching element connected to the first end of the primary side coil are controlled by a predetermined fixed duty, and the first switching element connected to the second end of the primary side coil is controlled. 3 switching elements and the fourth switching element are controlled by pulse width modulation,
The power supply control method, wherein the fifth switching element and the sixth switching element are turned on for at least a predetermined period before the third switching element or the fourth switching element is turned off.

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