JP2016213389A - Nitride semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device in which a current collapse phenomenon is inhibited; and provide a manufacturing method of the nitride semiconductor device.SOLUTION: A manufacturing method of a nitride semiconductor device 1 comprises: a process of depositing a surface layer 22 of an i-type nitride semiconductor on a nitride semiconductor laminate 16 having hetero junction; a process of depositing an etching stopper layer 24 on the surface layer 22; a process of depositing a p-type nitride semiconductor layer 26 on the etching stopper layer 24; a process of etching a part of the p-type nitride semiconductor layer 26 to expose the etching stopper layer 24; a process of forming a gate electrode 36 on the p-type nitride semiconductor layer 26; and a process of forming a drain electrode 32 on the nitride semiconductor laminate 16 at one of positions facing each other across the p-type nitride semiconductor layer 26, and forming a source electrode 34 on the other.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a nitride semiconductor device and a method for manufacturing the same.

  A nitride semiconductor device including a nitride semiconductor multilayer body having a heterojunction has been developed. This nitride semiconductor device uses a two-dimensional electron gas layer formed near the heterojunction surface as a channel. In this nitride semiconductor device, a gate electrode is provided between the drain electrode and the source electrode, and the amount of current flowing between the drain electrode and the source electrode is controlled in accordance with the potential of the gate electrode.

  As disclosed in Non-Patent Document 1 and Non-Patent Document 2, in this type of nitride semiconductor device, a technique for interposing a p-type nitride semiconductor layer between a gate electrode and a nitride semiconductor stacked body has been developed. Yes. When the p-type nitride semiconductor layer is provided, when the gate electrode is grounded, the depletion layer extending from the p-type nitride semiconductor layer becomes an electron in the two-dimensional electron gas layer below the p-type nitride semiconductor layer. Can be depleted. On the other hand, when a positive potential is applied to the gate electrode, the depletion layer shrinks, a two-dimensional electron gas layer is formed below the p-type nitride semiconductor layer, and the drain electrode and the source electrode pass through the two-dimensional electron gas layer. And conduct. Thus, the nitride semiconductor device provided with the p-type nitride semiconductor layer can operate normally off.

  Further, in this type of nitride semiconductor device, the occurrence of a current collapse phenomenon in which the on-state drain current decreases during switching is a problem. The current collapse phenomenon is considered to be caused by the accumulation of electric charges at the surface level of the nitride semiconductor multilayer body or at the interface level between the nitride semiconductor multilayer body and the passivation film. Patent Document 1 discloses a technique for forming a surface layer of an i-type or n-type nitride semiconductor on a nitride semiconductor multilayer body in order to suppress a current collapse phenomenon. Since the surface layer is provided on the nitride semiconductor multilayer body, the surface state or interface state of the nitride semiconductor multilayer body is reduced, charge accumulation is suppressed, and current collapse phenomenon is suppressed.

Injun Hwang et.al., ISPSD (2012), p.41 Y. Uemoto et.al., IEEE Transaction on Electron Devices, Vol.54 (2007), p.3393

JP 2014-72258 A

  The film thickness of the surface layer formed on the nitride semiconductor stacked body needs to be thin in order to avoid a current path for gate leakage current. For this reason, the method for manufacturing a nitride semiconductor device disclosed in Patent Document 1 includes a step of forming a p-type nitride semiconductor layer on a nitride semiconductor stack, and a titanium layer on the p-type nitride semiconductor layer other than the gate formation region. A step of reacting the p-type nitride semiconductor layer and the titanium layer by heat treatment to form titanium nitride, and a step of removing the titanium nitride by wet etching. In this manufacturing method, an unreacted p-type nitride semiconductor layer is formed in a region other than the gate formation region by adjusting the heat treatment time when the titanium layer and the p-type nitride semiconductor layer are reacted to form titanium nitride. Remain. The unreacted p-type nitride semiconductor layer becomes i-type or n-type by sucking up nitrogen when titanium nitride is formed. Through these steps, a thick p-type nitride semiconductor layer is formed in the gate formation region, and a thin surface layer is formed in regions other than the gate formation region.

  However, it is difficult to form a thin surface layer with high accuracy by adjusting the heat treatment time. The present specification provides a nitride semiconductor device in which a current collapse phenomenon is suppressed and a method for manufacturing the nitride semiconductor device.

  A method for manufacturing a nitride semiconductor device disclosed in the present specification includes a step of forming a surface layer of an i-type or n-type nitride semiconductor on a nitride semiconductor stacked body having a heterojunction, and an etching stopper on the surface layer. Forming a layer, forming a p-type nitride semiconductor layer on the etching stopper layer, etching a part of the p-type nitride semiconductor layer to expose the etching stopper layer, p-type nitride semiconductor Forming a gate electrode on the layer, and forming a drain electrode on one side of the nitride semiconductor laminate facing the p-type nitride semiconductor layer and forming a source electrode on the other side The process of carrying out is provided.

  According to the above manufacturing method, since the etching stopper layer is interposed between the surface layer and the p-type nitride semiconductor layer, the p-type nitride semiconductor layer can be removed while leaving the surface layer. Therefore, according to the above manufacturing method, a nitride semiconductor device in which the interface state between the nitride semiconductor multilayer body and the surface layer is small and the current collapse phenomenon is suppressed can be manufactured.

  The nitride semiconductor device disclosed in this specification includes a nitride semiconductor stacked body having a heterojunction, a surface layer of an i-type or nitride semiconductor, a drain electrode, a source electrode, a p-type nitride semiconductor layer, a gate electrode, and an etching stopper. With layers. The surface layer is provided on the nitride semiconductor layer. The drain electrode is provided on the nitride semiconductor multilayer body. The source electrode is provided on the nitride semiconductor stacked body and is arranged away from the drain electrode. The p-type nitride semiconductor layer is provided on the nitride semiconductor stacked body, and is disposed between the drain electrode and the source electrode and away from both the drain electrode and the source electrode. The gate electrode is provided on the p-type nitride semiconductor layer. The etching stopper layer is provided between the surface layer and the p-type nitride semiconductor layer.

The principal part sectional drawing of the nitride semiconductor device of an Example is typically shown. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of relevant parts in the process of manufacturing the nitride semiconductor device shown in FIG. 1. The principal part sectional drawing of the nitride semiconductor device of a modification is shown typically.

  The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  A method for manufacturing a nitride semiconductor device disclosed in the present specification includes a step of forming a surface layer of an i-type or n-type nitride semiconductor on a nitride semiconductor stacked body having a heterojunction, and an etching stopper on the surface layer. Forming a layer, forming a p-type nitride semiconductor layer on the etching stopper layer, etching a part of the p-type nitride semiconductor layer to expose the etching stopper layer, p-type nitride semiconductor Forming a gate electrode on the layer, and forming a drain electrode on one side of the nitride semiconductor laminate facing the p-type nitride semiconductor layer and forming a source electrode on the other side The process to perform may be provided. The step of forming the gate electrode may be performed before or after the step of forming the drain electrode and the source electrode. The drain electrode and the source electrode may be formed at the same time or may be formed in separate steps. The drain electrode and the source electrode may be formed so as to be in contact with the upper surface of the nitride semiconductor multilayer body, or may be formed on the nitride semiconductor multilayer body via a surface layer. The method for manufacturing a nitride semiconductor device disclosed in the present specification may further include a step of removing at least an upper layer portion of the exposed etching stopper layer by wet etching. When the etching stopper layer is removed by wet etching, processing damage applied to the surface layer can be suppressed.

  The nitride semiconductor device disclosed in this specification includes a nitride semiconductor stacked body having a heterojunction, a surface layer of an i-type or nitride semiconductor, a drain electrode, a source electrode, a p-type nitride semiconductor layer, a gate electrode, and an etching stopper. A layer may be provided. The surface layer is provided on the nitride semiconductor layer. The drain electrode is provided on the nitride semiconductor multilayer body. The source electrode is provided on the nitride semiconductor stacked body and is arranged away from the drain electrode. The drain electrode and the source electrode may be formed so as to be in contact with the upper surface of the nitride semiconductor multilayer body, or may be formed on the nitride semiconductor multilayer body via a surface layer. The p-type nitride semiconductor layer is provided on the surface layer, and is disposed between the drain electrode and the source electrode and away from both the drain electrode and the source electrode. The gate electrode is provided on the p-type nitride semiconductor layer. The etching stopper layer is provided between the surface layer and the p-type nitride semiconductor layer.

  In the nitride semiconductor device and the manufacturing method thereof disclosed in this specification, the etching stopper layer may be a nitride semiconductor having a composition different from any of the composition of the surface layer and the p-type nitride semiconductor layer. In this case, the p-type nitride semiconductor layer can be selectively removed when the p-type nitride semiconductor layer is etched. Furthermore, when the etching stopper layer is wet-etched, the etching stopper layer can be selectively removed to leave a surface layer with less processing damage.

For example, the etching stopper layer may be InAlN or AlN. The etching stopper layer of this material can be etched using an alkaline aqueous solution such as an aqueous ammonium hydroxide solution (NH ₄ OH) or an aqueous tetramethylammonium hydroxide solution (TMAH).

In the nitride semiconductor device and the manufacturing method thereof disclosed in this specification, the nitride semiconductor multilayer body may have an electron transit layer and a barrier layer. Semiconductor material of the electron transit _{layer, In Xa Al Ya Ga 1-} Xa-Ya N (0 ≦ Xa ≦ 1,0 ≦ Ya ≦ 1,0 ≦ Xa + Ya ≦ 1) a and the semiconductor material of the barrier layer, _{an In Xb} Al _Yb Ga _1-Xb—Yb N (0 ≦ Xb ≦ 1, 0 ≦ Yb ≦ 1, 0 ≦ Xb + Yb ≦ 1), and the band gap of In _Xb Al _Yb Ga _1-Xb—Yb N is In _Xa Al _Ya It is desirable that it is larger than the band gap of Ga _{1 -Xa-Yan} . the semiconductor material of p-type nitride semiconductor layer _is an _{In Xc Al Yc Ga 1-Xc} -Yc N (0 ≦ Xc ≦ 1,0 ≦ Yc ≦ 1,0 ≦ Xc + Yc ≦ 1). The composition of the p-type nitride semiconductor layer may be the same as the composition of the barrier layer. The semiconductor material of the surface layer _{is In Xd Al Yd Ga 1-Xd} -Yd N (0 ≦ Xd ≦ 1,0 ≦ Yd ≦ 1,0 ≦ Xd + Yd ≦ 1).

  As shown in FIG. 1, the nitride semiconductor device 1 is of a type called HFET (Heterostructure Field Effect Transistor) or HEMT (High Electron Mobility Transistor), and includes a substrate 12, a buffer layer 14, and a nitride semiconductor multilayer body. 16, a surface layer 22, an etching stopper layer 24, a p-type nitride semiconductor layer 26, a passivation film 28, a drain electrode 32, a source electrode 34, and a gate electrode 36.

  As the material of the substrate 12, a material capable of crystal growth of a nitride semiconductor-based semiconductor material is used. For example, gallium nitride, sapphire, silicon carbide, or silicon is used as the material of the substrate 12.

  The buffer layer 14 is provided in contact with the upper surface of the substrate 12. For example, non-doped gallium nitride (i-GaN), non-doped aluminum nitride (i-AlN), and non-doped aluminum gallium nitride (i-AlGaN) are used as the material of the buffer layer 14. The buffer layer 14 is laminated on the substrate 12 at a low temperature by using metal organic chemical vapor deposition (MOCVD).

  The nitride semiconductor multilayer body 16 includes an electron transit layer 15 and a barrier layer 17. The electron transit layer 15 is provided in contact with the upper surface of the buffer layer 14. For example, non-doped gallium nitride (i-GaN) is used as the material of the electron transit layer 15. The electron transit layer 15 is stacked on the buffer layer 14 using a metal organic chemical vapor deposition method. The barrier layer 17 is provided in contact with the upper surface of the electron transit layer 15. For example, non-doped aluminum gallium nitride (i-AlGaN) is used as the material of the barrier layer 17. The composition ratio of aluminum in the barrier layer 17 is about 5 to 30%, and the thickness is preferably about 5 to 30 nm. The barrier layer 17 is laminated on the electron transit layer 15 using metal organic vapor phase epitaxy. The band gap of the barrier layer 17 is larger than the band gap of the electron transit layer 15. Therefore, a two-dimensional electron gas layer is formed on the heterojunction surface between the electron transit layer 15 and the barrier layer 17.

The surface layer 22 is provided in contact with the upper surface of the barrier layer 17 and is disposed between the drain electrode 32 and the source electrode 34. For example, non-doped gallium nitride (i-GaN) is used as the material of the surface layer 22. The thickness of the surface layer 22 is desirably about 2 to 5 nm. In one example, the thickness of the surface layer 22 is about 2 nm. The material of the surface layer 22 may be gallium nitride (n-GaN) doped with silicon. In this case, the silicon dopant concentration of the surface layer 22 is desirably 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ in one example. The surface layer 22 is laminated on the barrier layer 17 using metal organic vapor phase epitaxy.

  The etching stopper layer 24 is provided in contact with the upper surface of the surface layer 22, and is disposed between the drain electrode 32 and the source electrode 34 and away from both the drain electrode 32 and the source electrode 34. Etching stopper layer 24 is provided between surface layer 22 and p-type nitride semiconductor layer 26. As the material of the etching stopper layer 24, a material having an etching rate smaller than the etching rate of the p-type nitride semiconductor layer 26 in dry etching is used. Further, as the material of the etching stopper layer 24, a material that has an etching rate higher than that of the surface layer 22 in wet etching is used. For example, AlN (aluminum nitride) is used as the material of the etching stopper layer 24. The thickness of the etching stopper layer 24 is preferably about 1 to 5 nm. In one example, the thickness of the etching stopper layer 24 is about 1 nm. The etching stopper layer 24 is laminated on the surface layer 22 using metal organic vapor phase epitaxy.

The p-type nitride semiconductor layer 26 is provided in contact with the upper surface of the etching stopper layer 24 and is disposed between the drain electrode 32 and the source electrode 34 and away from both the drain electrode 32 and the source electrode 34. Yes. As an example of the material of the p-type nitride semiconductor layer 26, aluminum gallium nitride (p-AlGaN) doped with magnesium is used. In one example, the dopant concentration of magnesium in the p-type nitride semiconductor layer 26 is 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The composition of the p-type nitride semiconductor layer 26 is the same as that of the barrier layer 17. The thickness of the p-type nitride semiconductor layer 26 is desirably about 30 to 100 nm. In one example, the aluminum composition ratio of the p-type nitride semiconductor layer 26 is about 18% and the thickness is about 30 nm. The p-type nitride semiconductor layer 26 is laminated on the upper surface of the barrier layer 17 using metal organic vapor phase epitaxy.

  Each of the drain electrode 32 and the source electrode 34 is provided in contact with the upper surface of the barrier layer 17 through the openings 22 a and 22 b of the surface layer 22. The drain electrode 32 and the source electrode 34 are arranged at positions facing each other with the p-type nitride semiconductor layer 26 interposed therebetween. The drain electrode 32 is preferably made of a material capable of making ohmic contact with a nitride semiconductor material. As an example of the material of the drain electrode 32, a laminated electrode of titanium and aluminum is used. It is desirable that the source electrode 34 be made of a material that can make ohmic contact with the nitride semiconductor material. As a material of the source electrode 34, for example, a laminated electrode of titanium and aluminum is used. Accordingly, each of the drain electrode 32 and the source electrode 34 is configured to be in ohmic contact with the two-dimensional electron gas layer formed on the heterojunction surface between the electron transit layer 15 and the barrier layer 17. Each of the drain electrode 32 and the source electrode 34 is laminated on the upper surface of the barrier layer 17 using an electron beam evaporation technique. In this example, since each of the drain electrode 32 and the source electrode 34 passes through the openings 22a and 22b of the surface layer 22 and is in contact with the upper surface of the barrier layer 17, the contact resistance is low. Instead of this example, each of the drain electrode 32 and the source electrode 34 may be formed on the barrier layer 17 via the surface layer 22.

  The gate electrode 36 is provided in contact with the upper surface of the p-type nitride semiconductor layer 26. The material of the gate electrode 36 is preferably a material that can make ohmic contact with a nitride semiconductor material. As an example of the material of the gate electrode 36, a laminated electrode of nickel and gold is used. Thereby, the gate electrode 36 is configured to be in ohmic contact with the p-type nitride semiconductor layer 26. The gate electrode 36 is stacked on the upper surface of the p-type nitride semiconductor layer 26 using an electron beam evaporation technique. The material of the gate electrode 36 may be a material that can make a Schottky contact with a nitride semiconductor material.

The passivation film 28 is provided in contact with the upper surface of the surface layer 22. The passivation film 28 covers regions other than these electrodes so that the drain electrode 32, the source electrode 34, and the gate electrode 36 are exposed. For example, silicon oxide (SiO ₂ ) is used as the material of the passivation film 28. The passivation film 28 is coated on the upper surface of the surface layer 22 using a plasma CVD technique. The material of the passivation film 28 is silicon nitride (SiN) formed using a plasma CVD technique, aluminum oxide (Al ₂ O ₃ ) formed using an atomic layer stacking method, sputtering, or MOCVD. It may be aluminum nitride (AlN) formed using technology.

  Next, the operation of the nitride semiconductor device 1 will be described. The nitride semiconductor device 1 is used with a positive potential applied to the drain electrode 32 and a ground potential applied to the source electrode 34. When the gate electrode 36 is grounded, a depletion layer extending from the p-type nitride semiconductor layer 26 is two-dimensional near the heterojunction surface of the electron transit layer 15 and the barrier layer 17 below the p-type nitride semiconductor layer 26. The electrons in the electron gas layer are depleted. For this reason, the current path between the drain electrode 32 and the source electrode 34 is cut off at the heterojunction surface where the p-type nitride semiconductor layer 26 faces, and the nitride semiconductor device 1 is turned off.

  When a positive potential is applied to the gate electrode 36, the depletion layer extending from the p-type nitride semiconductor layer 26 is reduced, and the electron transit layer 15 and the barrier layer 17 are also below the p-type nitride semiconductor layer 26. A two-dimensional electron gas layer is generated in the vicinity of the heterojunction surface. Electrons injected from the source electrode 34 flow to the drain electrode 32 through the two-dimensional electron gas layer, and the nitride semiconductor device 1 is turned on. Thus, nitride semiconductor device 1 operates normally off.

  In the nitride semiconductor device 1, the surface layer 22 is provided between the gate electrode 36 and the drain electrode 32. The surface layer 22 is provided in contact with the upper surface of the barrier layer 17 and is interposed between the barrier layer 17 and the passivation film 28. For this reason, there are few interface states between the barrier layer 17 and the surface layer 22 compared with the interface state when the barrier layer 17 and the passivation film 28 contact | connect directly. Furthermore, as will be described later in the manufacturing method, the surface layer 22 is formed in a high quality state with few crystal defects. For this reason, the interface state between the surface layer 22 and the passivation film 28 is also small. For this reason, accumulation of electric charges at these interface states is suppressed, and the current collapse phenomenon is suppressed. In order to suppress current collapse, it is desirable that the semiconductor material of the surface layer 22 is GaN. On the other hand, when the semiconductor material of the surface layer 22 contains aluminum or indium, especially when the aluminum contained in the surface layer 22 is more than the aluminum contained in the barrier layer 17, the electron transit layer 15 and the barrier are provided below the surface layer 22. The electron density of the two-dimensional electron gas layer between the layers 17 increases, and the on-resistance decreases. The semiconductor material of the surface layer 22 can be adjusted according to desired characteristics.

  In the nitride semiconductor device 1, the surface layer 22 and the etching stopper layer 24 are interposed between the p-type nitride semiconductor layer 26 and the barrier layer 17. For example, when the surface layer 22 and the etching stopper layer 24 are not provided, a parasitic diode composed of the p-type nitride semiconductor layer 26 and the barrier layer 17 exists. As a result, the nitride semiconductor device 1 When a positive potential is applied to the gate electrode 36 when is turned on, this parasitic diode is forward biased. However, in the nitride semiconductor device 1, the surface layer 22 and the etching stopper layer 24 are interposed between the p-type nitride semiconductor layer 26 and the barrier layer 17. Since the electrical resistance values of the surface layer 22 and the etching stopper layer 24 are large, the gate leakage current through the parasitic diode is suppressed, and the increase in power consumption is suppressed.

  Next, a method for manufacturing the nitride semiconductor device 1 will be described. First, as shown in FIG. 2, the buffer layer 14, the electron transit layer 15, and the barrier layer 17 are stacked on the substrate 12. The buffer layer 14, the electron transit layer 15, and the barrier layer 17 are sequentially grown on the substrate 12 using a metal organic vapor phase epitaxy method.

  Next, as shown in FIG. 3, the surface layer 22 is crystal-grown on the upper surface of the barrier layer 17 using metal organic vapor phase epitaxy.

  Next, as shown in FIG. 4, an etching stopper layer 24 is crystal-grown on the upper surface of the surface layer 22 using metal organic vapor phase epitaxy.

  Next, as shown in FIG. 5, a p-type nitride semiconductor layer 26 is crystal-grown on the upper surface of the etching stopper layer 24 using metal organic vapor phase epitaxy.

Next, as shown in FIG. 6, a part of the p-type nitride semiconductor layer 26 is removed using the dry etching technique to expose the etching stopper layer 24. The main component of the etching gas used in dry etching is chlorine gas (Cl ₂ ). As described above, the semiconductor material of the p-type nitride semiconductor layer 26 is aluminum gallium nitride (AlGaN), and the semiconductor material of the etching stopper layer 24 is aluminum nitride (AlN). For this reason, the etching selection ratio of the p-type nitride semiconductor layer 26 to the etching stopper layer 24 is large, and only the p-type nitride semiconductor layer 26 is selectively removed.

Next, as shown in FIG. 7, using the wet etching technique, the exposed etching stopper layer 24 is removed, and the surface layer 22 is exposed. An etching solution used in the wet etching is an aqueous ammonium hydroxide solution (NH ₄ OH). As described above, the semiconductor material of the etching stopper layer 24 is aluminum nitride (AlN), and the semiconductor material of the surface layer 22 is gallium nitride (GaN). For this reason, the etching selection ratio of the etching stopper layer 24 to the surface layer 22 is large, and the etching stopper layer 24 is selectively removed. Further, since the etching stopper layer 24 is removed using the wet etching technique, the upper layer portion of the surface layer 22 is less damaged by processing.

  Next, as shown in FIG. 8, openings 22a and 22b are formed in a part of the surface layer 22 by using a dry etching technique. The upper surface of the barrier layer 17 is exposed at the openings 22 a and 22 b of the surface layer 22.

  Next, as shown in FIG. 9, the drain electrode 32 and the source electrode 34 are formed on the upper surface of the barrier layer 17 exposed in the openings 22 a and 22 b of the surface layer 22 by using an electron beam evaporation technique. Next, a gate electrode 36 is formed on the upper surface of the p-type nitride semiconductor layer 26 using an electron beam evaporation technique. Finally, when the passivation film 28 is formed, the nitride semiconductor device 1 shown in FIG. 1 is completed.

  The manufacturing method is characterized in that an etching stopper layer 24 is interposed between the surface layer 22 and the p-type nitride semiconductor layer 26. Thereby, when the p-type nitride semiconductor layer 26 is processed using the dry etching technique, the etching can be stopped with high accuracy by the etching stopper layer 24. For example, when the etching stopper layer 24 is not provided, there is a concern that the barrier layer 17 is etched beyond the surface layer 22 due to a manufacturing error, and processing damage remains on the surface of the barrier layer 17. On the other hand, such a situation can be avoided in the manufacturing method. Therefore, the interface state between the barrier layer 17 and the surface layer 22 is small, charge accumulation is suppressed, and the current collapse phenomenon is suppressed. Furthermore, since the manufacturing method uses the wet etching technique to remove the etching stopper layer 24, processing damage on the surface layer 22 can be suppressed even at this time. Accordingly, the interface state between the surface layer 22 and the passivation film 28 is small, charge accumulation is suppressed, and current collapse phenomenon is suppressed.

  FIG. 10 shows a modified nitride semiconductor device 2. In the nitride semiconductor device 2, the thickness of the etching stopper layer 24 between the p-type nitride semiconductor layer 26 and the drain electrode 32 and between the p-type nitride semiconductor layer 26 and the source electrode 34 is thin. The nitride semiconductor device 2 is manufactured by removing only the upper layer portion of the etching stopper layer 24 in the wet etching in the manufacturing process of FIG. Since the processing damage when the p-type nitride semiconductor layer 26 is dry-etched is present only in the upper layer portion of the etching stopper layer 24, even if only the upper layer portion is removed by wet etching, the current collapse phenomenon occurs. The effect of suppressing is obtained.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: nitride semiconductor device, 12: substrate, 14: buffer layer, 15: electron transit layer, 16: nitride semiconductor laminate, 17: barrier layer, 22: surface layer, 24: etching stopper layer, 26: p-type Nitride semiconductor layer 28: Passivation film 32: Drain electrode 34: Source electrode 36: Gate electrode

Claims (7)

A method for manufacturing a nitride semiconductor device, comprising:
Forming a surface layer of an i-type or n-type nitride semiconductor on a nitride semiconductor multilayer body having a heterojunction;
Forming an etching stopper layer on the surface layer;
Forming a p-type nitride semiconductor layer on the etching stopper layer;
Etching a part of the p-type nitride semiconductor layer to expose the etching stopper layer;
Forming a gate electrode on the p-type nitride semiconductor layer;
And a step of forming a drain electrode on one side of the nitride semiconductor multilayer body facing each other with the p-type nitride semiconductor layer interposed therebetween, and forming a source electrode on the other side.   The manufacturing method according to claim 1, further comprising a step of removing at least an upper layer portion of the exposed etching stopper layer by wet etching.   The manufacturing method according to claim 2, wherein the etching stopper layer is a nitride semiconductor having a composition different from any of the compositions of the surface layer and the p-type nitride semiconductor layer.   The manufacturing method according to claim 3, wherein the etching stopper layer is InAlN or AlN. A nitride semiconductor device comprising:
A nitride semiconductor laminate having a heterojunction; and
A surface layer of an i-type or n-type nitride semiconductor provided on the nitride semiconductor laminate;
A drain electrode provided on the nitride semiconductor laminate;
A source electrode provided on the nitride semiconductor multilayer body and disposed away from the drain electrode;
A p-type nitride semiconductor layer provided on the surface layer and disposed between the drain electrode and the source electrode and away from both the drain electrode and the source electrode;
A gate electrode provided on the p-type nitride semiconductor layer;
A nitride semiconductor device comprising: an etching stopper layer provided between the surface layer and the p-type nitride semiconductor layer.   The nitride semiconductor device according to claim 5, wherein the etching stopper layer is a nitride semiconductor having a composition different from any of the compositions of the surface layer and the p-type nitride semiconductor layer.   The nitride semiconductor device according to claim 6, wherein the etching stopper layer is InAlN or AlN.

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