JP2016204187A5 - - Google Patents

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Publication number
JP2016204187A5
JP2016204187A5 JP2015085606A JP2015085606A JP2016204187A5 JP 2016204187 A5 JP2016204187 A5 JP 2016204187A5 JP 2015085606 A JP2015085606 A JP 2015085606A JP 2015085606 A JP2015085606 A JP 2015085606A JP 2016204187 A5 JP2016204187 A5 JP 2016204187A5
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Prior art keywords
polishing
abrasive grains
epitaxial wafer
manufacturing
slurry containing
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JP2015085606A
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Japanese (ja)
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JP2016204187A (en
JP6234957B2 (en
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Priority to JP2015085606A priority Critical patent/JP6234957B2/en
Priority claimed from JP2015085606A external-priority patent/JP6234957B2/en
Priority to PCT/JP2016/001183 priority patent/WO2016170721A1/en
Priority to TW105106854A priority patent/TW201708632A/en
Publication of JP2016204187A publication Critical patent/JP2016204187A/en
Publication of JP2016204187A5 publication Critical patent/JP2016204187A5/ja
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Claims (5)

エピタキシャルウェーハの製造方法であって、
研磨布が貼付された上下定盤と、該上下定盤間でシリコンウェーハを保持するキャリアとを具備する両面研磨装置を用い、第1の砥粒を含むスラリーを供給しながら、前記シリコンウェーハの両面を研磨する1次研磨を行う工程と、
前記両面研磨装置を用い、前記第1の砥粒より平均粒径の小さい第2の砥粒を含むスラリーを供給しながら、前記1次研磨を行った後のシリコンウェーハの両面を研磨する2次研磨を行う工程と、
前記2次研磨を行った後のシリコンウェーハ表面に片面CMP研磨を行うことなくエピタキシャル層を成長させる工程と
を有し、
前記1次研磨と前記2次研磨を同一の両面研磨装置を用いて行うことを特徴とするエピタキシャルウェーハの製造方法。
An epitaxial wafer manufacturing method comprising:
Using a double-side polishing apparatus comprising an upper and lower surface plate with a polishing cloth and a carrier for holding the silicon wafer between the upper and lower surface plates, while supplying slurry containing the first abrasive grains, A step of performing primary polishing for polishing both surfaces;
Secondary polishing the both sides of the silicon wafer after the primary polishing while supplying slurry containing second abrasive grains having an average particle size smaller than the first abrasive grains using the double-side polishing apparatus Polishing, and
Possess a step of growing an epitaxial layer without a single side CMP polishing the silicon wafer surface after the secondary polishing,
An epitaxial wafer manufacturing method , wherein the primary polishing and the secondary polishing are performed using the same double-side polishing apparatus .
前記1次研磨を行う工程において、前記第1の砥粒を含むスラリーとして、平均粒径50nm〜100nmのシリカ砥粒を含むアルカリ性水溶液を用い、
前記2次研磨を行う工程において、前記第2の砥粒を含むスラリーとして、平均粒径20nm〜40nmのシリカ砥粒を含むアルカリ性水溶液を用いることを特徴とする請求項1に記載のエピタキシャルウェーハの製造方法。
In the step of performing the primary polishing, as the slurry containing the first abrasive grains, an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 50 nm to 100 nm is used,
2. The epitaxial wafer according to claim 1, wherein an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 20 nm to 40 nm is used as the slurry containing the second abrasive grains in the step of performing the secondary polishing. Production method.
前記2次研磨を行う工程において、前記2次研磨の取り代を1μm以下とすることを特徴とする請求項1又は請求項2に記載のエピタキシャルウェーハの製造方法。   3. The method for manufacturing an epitaxial wafer according to claim 1, wherein, in the step of performing the secondary polishing, an allowance for the secondary polishing is set to 1 μm or less. 4. 前記研磨布をショアA硬度85〜95の発泡ポリウレタンからなる研磨布とし、前記キャリアを表面のビッカース硬さが300以上のキャリアとすることを特徴とする請求項1から請求項3のいずれか1項に記載のエピタキシャルウェーハの製造方法。   4. The polishing cloth according to claim 1, wherein the polishing cloth is a polishing cloth made of polyurethane foam having a Shore A hardness of 85 to 95, and the carrier is a carrier having a surface Vickers hardness of 300 or more. The manufacturing method of the epitaxial wafer of claim | item. 前記2次研磨後のシリコンウェーハの面品質を、100nm以下のLPDの個数が測定可能な面品質とすることを特徴とする請求項1から請求項4のいずれか1項に記載のエピタキシャルウェーハの製造方法。   5. The epitaxial wafer according to claim 1, wherein the surface quality of the silicon wafer after the secondary polishing is a surface quality that allows the number of LPDs of 100 nm or less to be measured. Production method.
JP2015085606A 2015-04-20 2015-04-20 Epitaxial wafer manufacturing method Active JP6234957B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015085606A JP6234957B2 (en) 2015-04-20 2015-04-20 Epitaxial wafer manufacturing method
PCT/JP2016/001183 WO2016170721A1 (en) 2015-04-20 2016-03-04 Method for manufacturing epitaxial wafer
TW105106854A TW201708632A (en) 2015-04-20 2016-03-07 Method for manufacturing epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015085606A JP6234957B2 (en) 2015-04-20 2015-04-20 Epitaxial wafer manufacturing method

Publications (3)

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JP2016204187A JP2016204187A (en) 2016-12-08
JP2016204187A5 true JP2016204187A5 (en) 2017-03-02
JP6234957B2 JP6234957B2 (en) 2017-11-22

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Family Applications (1)

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JP2015085606A Active JP6234957B2 (en) 2015-04-20 2015-04-20 Epitaxial wafer manufacturing method

Country Status (3)

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JP (1) JP6234957B2 (en)
TW (1) TW201708632A (en)
WO (1) WO2016170721A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6635088B2 (en) * 2017-04-24 2020-01-22 信越半導体株式会社 Polishing method of silicon wafer
DE102017210423A1 (en) 2017-06-21 2018-12-27 Siltronic Ag Method, control system and plant for processing a semiconductor wafer and semiconductor wafer
CN111316399B (en) * 2017-08-31 2023-12-26 胜高股份有限公司 Method for manufacturing semiconductor wafer
US11621171B2 (en) 2018-09-25 2023-04-04 Nissan Chemical Corporation Method for polishing silicon wafer with reduced wear on carrier, and polishing liquid used therein

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004195571A (en) * 2002-12-17 2004-07-15 Noritake Co Ltd Work carrier for double-sided polishing machine and its manufacturing method
JP2010021487A (en) * 2008-07-14 2010-01-28 Sumco Corp Semiconductor wafer and manufacturing method thereof
JP5401683B2 (en) * 2008-08-01 2014-01-29 株式会社Sumco Double-sided mirror semiconductor wafer and method for manufacturing the same
JP5644401B2 (en) * 2010-11-15 2014-12-24 株式会社Sumco Epitaxial wafer manufacturing method and epitaxial wafer
JP5768554B2 (en) * 2011-07-21 2015-08-26 旭硝子株式会社 Manufacturing method of glass substrate for magnetic recording medium and glass substrate for magnetic recording medium
US20140319411A1 (en) * 2011-11-16 2014-10-30 Nissan Chemical Industries, Ltd. Semiconductor wafer polishing liquid composition

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