JP2016204187A - Method of manufacturing epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an epitaxial wafer in which a less-defect epitaxial wafer having good fitness can be stably manufactured.SOLUTION: There is provided a method of manufacturing an epitaxial wafer, the method comprising the steps of: using a both-side polishing apparatus comprising upper and lower surface plates where abrasive cloth is stuck, and a carrier holding a silicon wafer between the upper and lower surface plates, and performing primary polishing for polishing both sides of the silicon wafer while supplying slurry including first abrasive grains; using the both-side polishing apparatus and performing secondary polishing for polishing both sides of the silicon wafer having been subjected to the primary polishing while supplying slurry including second abrasive grains having smaller mean particle size than the first abrasive grains; and growing an epitaxial layer on a top surface of the silicon wafer having been subjected to the secondary polishing without one-side CMP polishing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an epitaxial wafer manufacturing method.

  In general, an epitaxial wafer is manufactured through double-side polishing (DSP) to single-side CMP (Chemical Mechanical Polishing) polishing (see FIG. 10). In contrast to this situation, Patent Documents 1 and 2 disclose a process for growing an epitaxial layer without performing single-side CMP polishing on a wafer after double-side polishing from the viewpoint of cost reduction. In particular, in Patent Document 1, primary polishing and secondary polishing are performed as double-side polishing, and processing damage is reduced by using an abrasive-free slurry (an alkaline aqueous solution not containing abrasive grains) in the secondary polishing (see FIG. 11).

JP 2011-42536 A JP2013-17596A

  FIG. 8 is a graph showing changes in SFQRmax before and after single-side CMP polishing. FIG. 9 is a graph showing changes in ESFQRmax before and after single-side CMP polishing. 8 and 9, the average value before single-side CMP polishing is normalized as 1.

  Here, SFQR (Site Front least squares Range) is a surface-based site flatness index, and is evaluated for each site. SFQR is defined as a range of positive and negative deviations from a reference plane when a cell having an arbitrary size is determined on the wafer surface and a plane obtained by the least square method is used as the reference plane. . The value of SFQRmax represents the maximum value of SFQR in each site on a given wafer.

  Further, ESFQR (Edge Site Front squares Range) corresponds to the SFQR at the edge (outer peripheral part) and is a flatness index indicating the flatness of the outer peripheral part. The value of ESFQRmax represents the maximum value of ESFQR in each site on a given wafer.

  Single-side CMP polishing is a process for reducing defects in the wafer, but in addition to high cost, flatness is deteriorated (see FIGS. 8 and 9). Therefore, from the viewpoint of flatness, it is required to send the process directly from double-side polishing to epitaxial growth. What is required at this time is to improve and manage the surface quality on the premise that the flatness at the end of double-side polishing is maintained.

  Here, the problem of surface quality after double-side polishing will be described with reference to Patent Document 1. Surface quality can be broadly divided into defects and surface roughness. In Patent Document 1, an abrasive-free slurry is employed to reduce defects. However, since the abrasive-free slurry has a strong chemical action, the surface roughness of the wafer is not sufficiently lowered. If the surface is rough, the detection sensitivity decreases in the inspection for measuring the number of defects. Then, although a defect is not detected before epitaxial growth, the event that a defect appears after epitaxial growth occurs. This cannot stabilize defects after epitaxial growth.

  The present invention has been made in view of the above problems, and an object thereof is to provide an epitaxial wafer manufacturing method capable of stably manufacturing an epitaxial wafer having few defects and good flatness.

In order to achieve the above object, the present invention provides an epitaxial wafer manufacturing method,
Using a double-side polishing apparatus comprising an upper and lower surface plate with a polishing cloth and a carrier for holding the silicon wafer between the upper and lower surface plates, while supplying slurry containing the first abrasive grains, A step of performing primary polishing for polishing both surfaces;
Secondary polishing the both sides of the silicon wafer after the primary polishing while supplying slurry containing second abrasive grains having an average particle size smaller than the first abrasive grains using the double-side polishing apparatus Polishing, and
And a step of growing an epitaxial layer on the silicon wafer surface after the secondary polishing without performing single-side CMP polishing.

  With such an epitaxial wafer manufacturing method, an epitaxial wafer with few defects and good flatness can be stably manufactured.

Moreover, in the step of performing the primary polishing, an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 50 nm to 100 nm is used as the slurry containing the first abrasive grains,
In the step of performing the secondary polishing, it is preferable to use an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 20 nm to 40 nm as the slurry containing the second abrasive grains.

  By using such a slurry, the surface roughness of the silicon wafer after the secondary polishing can be further reduced. Thereby, an epitaxial wafer with few defects can be manufactured more stably.

  Further, in the step of performing the secondary polishing, it is preferable that the machining allowance of the secondary polishing is 1 μm or less.

  By performing the secondary polishing in this way, the flatness of the silicon wafer after the secondary polishing can be improved, and the polishing is not performed more than necessary. Thereby, an epitaxial wafer with better flatness can be manufactured at low cost.

  Preferably, the polishing cloth is a polishing cloth made of polyurethane foam having a Shore A hardness of 85 to 95, and the carrier is a carrier having a surface Vickers hardness of 300 or more.

  By using such a polishing cloth, an epitaxial wafer with better flatness can be produced. Further, by using such a carrier, dust generation from the carrier can be prevented.

  Moreover, it is preferable that the surface quality of the silicon wafer after the secondary polishing is a surface quality that allows the number of LPDs of 100 nm or less to be measured.

  By setting such surface quality, when performing inspection for measuring the number of defects at the end of double-side polishing, the detection sensitivity in the inspection can be further improved. Thereby, an epitaxial wafer with few defects can be manufactured more stably.

  In the present invention, when performing double-side polishing, the same double-side polishing apparatus is used, and the surface is finished in multiple stages using only the slurry, so that the flatness of the silicon wafer after the secondary polishing is more than when single-side CMP is performed. The surface roughness and defects can be improved as compared with the case where the abrasive-free polishing is performed in the secondary polishing. This surface roughness improvement makes it possible to measure and manage an LPD (Light Point Defect) of 100 nm or less. Thereby, an epitaxial wafer with few defects and good flatness can be stably manufactured.

It is a flowchart which shows an example of the procedure of the manufacturing method of the epitaxial wafer of this invention. It is the schematic which shows an example of the double-side polish apparatus which can be used with the manufacturing method of the epitaxial wafer of this invention. It is an internal structure figure of the double-side polish apparatus in case there is one carrier. It is the schematic which shows an example of the vapor phase growth apparatus which can be used with the manufacturing method of the epitaxial wafer of this invention. It is a graph which shows the SFQR deterioration amount in an Example and the comparative example 1. It is the figure which piled up the LPD map after double-side polish in the Example, and the LPD map after epitaxial growth. It is the figure which piled up the LPD map after double-sided polishing in the comparative example 2, and the LPD map after epitaxial growth. It is a graph which shows the change of SFQRmax before and behind single-side CMP polishing. It is a graph which shows the change of ESFQRmax before and behind single-side CMP polishing. It is a flowchart which shows an example of the procedure of the manufacturing method of the conventional epitaxial wafer. 5 is a flowchart showing a procedure of an epitaxial wafer manufacturing method disclosed in Patent Document 1.

  Hereinafter, the present invention will be described in more detail.

  As described above, there is a need for an epitaxial wafer manufacturing method that can stably manufacture an epitaxial wafer with few defects and good flatness.

  The present inventors have intensively studied to achieve the above object. As a result, primary polishing using the slurry containing the first abrasive grains and secondary polishing using the slurry containing the second abrasive grains having an average particle size smaller than the first abrasive grains are performed using the same double-side polishing apparatus. Then, the inventors have found that an epitaxial wafer manufacturing method in which an epitaxial layer is grown without performing single-side CMP polishing on the surface of a silicon wafer can solve the above problems, and the present invention has been completed.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, but the present invention is not limited thereto.

  First, a double-side polishing apparatus that can be used in the epitaxial wafer manufacturing method of the present invention will be described with reference to FIGS. FIG. 2 is a schematic view showing an example of a double-side polishing apparatus that can be used in the epitaxial wafer manufacturing method of the present invention. FIG. 3 is an internal structure diagram of the double-side polishing apparatus when there is one carrier.

  As shown in FIG. 2, the double-side polishing apparatus 1 includes an upper surface plate 5, a lower surface plate 6, and a carrier 2 for holding the wafer W. The upper surface plate 5 and the lower surface plate 6 are provided so as to face each other up and down, and a polishing cloth (polishing pad) 4 is attached to each of the surface plates 5 and 6. As shown in FIG. 3, a sun gear 7 is provided at the center of the double-side polishing apparatus 1, and an internal gear 8 is provided at the periphery. The wafer W is held in the holding hole 3 of the carrier 2 and is sandwiched between the upper surface plate 5 and the lower surface plate 6. 2 illustrates a double-side polishing apparatus including a plurality of carriers, and FIG. 3 illustrates a case where there is one carrier.

  The teeth of the sun gear 7 and the internal gear 8 are meshed with the outer peripheral teeth of the carrier 2. Thereby, as the upper surface plate 5 and the lower surface plate 6 are rotated by a drive source (not shown), the carrier 2 revolves around the sun gear 7 while rotating. At this time, both surfaces of the wafer W held in the holding hole 3 of the carrier 2 are simultaneously polished by the upper and lower polishing cloths 4. At the time of polishing the wafer W, polishing slurry is supplied to the polishing surface of the wafer W from a nozzle (not shown) through a plurality of through holes provided in the upper surface plate 5.

  In FIG. 3, the carrier 2 holds one wafer W, but a plurality of wafers may be held in the carrier using a carrier having a plurality of holding holes. Moreover, you may use the double-side polish apparatus provided with the some carrier 2 like FIG.

  Next, a vapor phase growth apparatus that can be used in the epitaxial wafer manufacturing method of the present invention will be described with reference to FIG. FIG. 4 is a schematic view showing an example of a vapor phase growth apparatus that can be used in the epitaxial wafer manufacturing method of the present invention.

  The vapor phase growth apparatus 21 includes a chamber 22 for performing vapor phase growth therein, a gas introduction pipe 23 that communicates with the chamber 22, introduces various gases G such as a reaction gas into the chamber 22, and the chamber 22. A gas exhaust pipe 24 that exhausts gas from the chamber 22 and a susceptor 25 that is disposed in the chamber 22 and on which the wafer W is placed are provided.

  In addition, the vapor phase growth apparatus 21 appropriately includes a susceptor rotation mechanism 26 for rotating the susceptor 25, a heating unit 27 for heating the wafer W, and the like. The chamber 22 is usually composed of a plurality of members. For example, it comprises a chamber upper member 28 and a chamber lower member 29 made of transparent quartz. The gas inlet 23 is provided with a gas inlet 30, and the gas outlet 24 is provided with a gas outlet 31. The susceptor 25 is supported by a main column 33 having a shaft 32 and a sub column 34. The susceptor 25 has a counterbore 35 on which the wafer W is placed.

  Next, the manufacturing method of the epitaxial wafer of this invention is demonstrated. The epitaxial wafer manufacturing method of the present invention comprises a double-side polishing apparatus comprising upper and lower surface plates 5 and 6 to which a polishing cloth 4 is attached, and a carrier 2 that holds a silicon wafer W between the upper and lower surface plates 5 and 6. The step of performing primary polishing for polishing both surfaces of the silicon wafer W while supplying the slurry containing the first abrasive grains, and using the double-side polishing apparatus, the average grain size of the first abrasive grains is larger than that of the first abrasive grains. A step of performing secondary polishing for polishing both surfaces of the silicon wafer W after performing the primary polishing while supplying a slurry containing small second abrasive grains, and a silicon wafer after performing the secondary polishing And a step of growing an epitaxial layer on the W surface without performing single-side CMP polishing.

  The present invention is characterized in that primary polishing and secondary polishing are performed using the same double-side polishing apparatus. As a result, the secondary polishing can be applied to the bare silicon surface exposed by the primary polishing, and the roughness can be quickly reduced with a minimum amount of secondary polishing.

  Thus, in the present invention, the slurry containing the first abrasive grains is used in the primary polishing, and the slurry containing the second abrasive grains having an average particle size smaller than the first abrasive grains is used in the secondary polishing. The surface roughness of the silicon wafer after the next polishing can be reduced. Thereby, when performing the test | inspection which measures the number of defects at the time of completion | finish of double-sided polishing, it is possible to improve the detection sensitivity in the test. As a result, it is possible to avoid a situation in which defects that could not be detected at the end of double-side polishing appear after epitaxial growth. Therefore, the epitaxial wafer manufacturing method of the present invention can stably manufacture an epitaxial wafer with few defects.

  In addition, according to the epitaxial wafer manufacturing method of the present invention, after performing double-side polishing, an epitaxial layer can be grown without performing single-side CMP polishing that deteriorates flatness, so that an epitaxial wafer with good flatness can be stabilized. Can be manufactured.

  FIG. 1 is a flowchart showing an example of the procedure of an epitaxial wafer manufacturing method according to the present invention. Hereafter, each process of the flowchart of FIG. 1 is explained in full detail. First, as shown in FIG. 1, a pre-process is performed as needed. Examples of the pre-process include chamfering, lapping, and etching performed on the wafer after slicing the ingot to obtain a wafer.

  Although the diameter of the silicon wafer used by this invention is not specifically limited, For example, it can be 150-300 mm.

  Next, primary polishing is performed using a double-side polishing apparatus as shown in FIG. In primary polishing, a slurry containing first abrasive grains is used. As the double-side polishing apparatus, the 4-way double-side polishing apparatus having the upper surface plate, the lower surface plate, the sun gear, and the internal gear drive units shown in FIGS.

  As the polishing cloth 4, it is preferable to use a foamed polyurethane having a Shore A hardness of 85 to 95. If the Shore A hardness is 95 or less, the wafer is hardly damaged. If the Shore A hardness is 85 or more, flatness is unlikely to deteriorate.

  Moreover, as the carrier 2, it is preferable to use a carrier having a surface Vickers hardness of 300 or more (for example, a metal base material carrier). For example, as the carrier 2, a substrate made of a metal with high hardness such as stainless steel can be used. Further, a hard coating such as DLC (diamond-like carbon) may be applied to the surface of the carrier. By increasing the hardness of the carrier surface, wear can be reduced, and dust generation from the carrier can be prevented. A resin-made insert material can be attached to the inner peripheral portion of the holding hole 3 of the carrier 2.

  As the slurry containing the first abrasive grains, an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 50 nm to 100 nm is preferably used. For example, an alkaline aqueous solution having an average particle size of 50 nm to 100 nm, an abrasive concentration of 1 to 5 wt%, and a pH of 10 to 11 can be used. By using such a slurry, the surface roughness of the silicon wafer can be further reduced.

  In addition, the average particle diameter in this invention is an average primary particle diameter computed from the specific surface area measured by BET method.

Although the processing load in primary polishing is not specifically limited, For example, it can be set as 100-200 gf / cm < ² >.

  Next, using the same apparatus as the double-side polishing apparatus used in the primary polishing as shown in FIG. 1, while supplying a slurry containing second abrasive grains having an average grain size smaller than that of the first abrasive grains, Secondary polishing is performed to polish both surfaces of the silicon wafer W after polishing. By using the same apparatus in the primary polishing and the secondary polishing and making the slurry into two stages, the surface roughness of the wafer can be reduced at a low cost.

  As the slurry containing the second abrasive grains, an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 20 nm to 40 nm is preferably used. For example, an alkaline aqueous solution having an average particle size of 20 nm to 40 nm, an abrasive concentration of 0.2 to 1.0 wt%, and a pH of 9 to 10 can be used. A water-soluble polymer such as hydroxyethyl cellulose (HEC) may be added to the slurry containing the second abrasive grains. By using such a slurry, the surface roughness of the silicon wafer after the secondary polishing can be further reduced. Thereby, an epitaxial wafer with few defects can be manufactured more stably.

  In the step of performing secondary polishing, it is preferable that the machining allowance for secondary polishing is 1 μm or less. The machining allowance for secondary polishing is more preferably 500 nm or less. By performing the secondary polishing in this way, the flatness achieved by the primary polishing can be maintained, so that the flatness of the silicon wafer after the secondary polishing can be improved. Thereby, an epitaxial wafer with better flatness can be manufactured. Further, since the machining allowance is not increased more than necessary, the polishing can be performed in a short time, and the cost can be reduced.

Although the processing load in secondary polishing is not specifically limited, For example, it can be set as 50-100 gf / cm < ² >.

  By performing primary polishing and secondary polishing as described above, it is possible to reduce the surface roughness and the number of defects, particularly the surface roughness of the wafer. Thereby, a silicon wafer having a surface quality on which an epitaxial layer can be stacked can be obtained. Furthermore, in the present invention, as will be described later, since the epitaxial layer is grown on the silicon wafer surface without performing single-side CMP polishing, flatness after double-side polishing can be maintained.

  Moreover, it is preferable that the surface quality of the silicon wafer after the secondary polishing is a surface quality that allows the number of LPDs of 100 nm or less to be measured. By setting such surface quality, when performing inspection for measuring the number of defects at the end of double-side polishing, the detection sensitivity in the inspection can be further improved. Thereby, an epitaxial wafer with few defects can be manufactured more stably.

  When measuring the flatness (SFQRmax, etc.) of the wafer after double-side polishing, for example, WaferSight manufactured by KLA Tencor can be used. At this time, SFQRmax can be calculated with a cell size of M49 mode of 26 × 8 mm (2 mm EE (outer periphery exclusion region)).

  When measuring the surface quality (defects and surface roughness) after double-side polishing and after the formation of an epitaxial layer described later, Surfscan SP3 manufactured by KLA can be used.

  Next, as shown in FIG. 1, an epitaxial layer is grown on the silicon wafer surface after the secondary polishing without performing single-side CMP polishing. As the vapor phase growth apparatus, the single-phase vapor phase growth apparatus shown in FIG. 4 (for example, a single-phase vapor phase growth apparatus for a wafer having a diameter of 300 mm) can be used. Note that the silicon wafer may be cleaned before the epitaxial layer is grown. In this case, the cleaning conditions are not particularly limited. For example, general RCA cleaning or cleaning using functional water containing ozone, hydrofluoric acid, or the like can be performed.

  The epitaxial growth step is not particularly limited as long as it is a generally used method, but the temperature is raised to about 1000 ° C. to 1300 ° C. in a hydrogen atmosphere, and then a raw material gas such as TCS (trichlorosilane) is introduced for a predetermined time. It is preferable to grow an epitaxial layer. The growth temperature and growth time at this time can be appropriately determined in consideration of the thickness of the desired epitaxial layer.

In the epitaxial growth step, monosilane, monochlorosilane, dichlorosilane, carbon tetrachloride, or the like can be used as a source gas in addition to trichlorosilane. In addition to the source gas, a dopant gas such as diborane (B ₂ H ₆ ) or phosphine (PH ₃ ) can be used together with the hydrogen gas.

  After vapor phase growth of the epitaxial layer in this way, the supply of the source gas and the dopant gas is stopped, and the temperature in the reaction vessel is lowered while maintaining the hydrogen atmosphere.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to the following Example.

(Example)
First, as a double-side polishing apparatus, DSP-20B manufactured by Fujikoshi Machine Industry was used, and double-side polishing (primary polishing and secondary polishing) was performed on a total of five wafers using the same double-side polishing apparatus. As a wafer to be polished, a P-type silicon single crystal wafer having a diameter of 300 mm was used. A foamed polyurethane pad having a Shore A hardness of 91 was used as the polishing cloth. The carrier was made of titanium as a substrate, and the surface was subjected to DLC treatment to increase the hardness of the surface. As a result, the Hv (Vickers hardness) of the carrier was 1200. As the insert material, FRP (fiber reinforced plastic) in which glass fiber was impregnated with epoxy resin was used.

  As the slurry containing the first abrasive grains, a KOH-based aqueous solution containing silica abrasive grains having an average grain diameter of 74 nm, an abrasive grain concentration of 2.4 wt%, and a pH of 10.5 was used. The slurry containing the second abrasive grains contains silica abrasive grains having an average particle diameter of 35 nm, an abrasive concentration of 0.45 wt%, and an ammonia-based aqueous solution having a pH of 10.0. The one added with ~ 300,000 HEC was used.

Processing load in the primary polishing processing load at 150gf / ^cm 2, 2-polishing was set to 70 gf / cm ^2. The processing time was set so that the machining allowance in primary polishing was 10 μm or more, and the machining allowance in secondary polishing was 500 nm.

  The rotational speed of each drive unit was set to upper platen-13.4 rpm, lower platen 35 rpm, sun gear 25 rpm, and internal gear 7 rpm. The dressing of the polishing cloth was performed by sliding the dress plate on which the diamond abrasive grains were electrodeposited to the upper and lower polishing cloths while flowing pure water at a predetermined pressure.

Next, the wafer after double-side polishing was washed. SC-1 washing was performed under the conditions NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 15.

  Next, an epitaxial layer was grown on the cleaned wafer. As the epitaxial growth furnace, the vapor phase growth apparatus shown in FIG. 4 was used. In the epitaxial growth, TCS was used as a source gas. The growth temperature was 1100 ° C. and the film thickness was 3 μm.

(Comparative Example 1)
Chemical mechanical polishing by single-side CMP polishing was performed as secondary polishing on a total of five wafers that had been subjected to primary polishing using the same double-side polishing apparatus as in the example. As the polishing cloth, a suede type cloth was used. The same slurry as that used in the secondary polishing in the examples was used. The processing time was set so that the machining allowance in single-side CMP polishing was 500 nm. The cleaning and epitaxial growth conditions were the same as in the examples.

(Comparative Example 2)
Double-side polishing (primary polishing and secondary polishing) was performed on a total of five wafers using the same double-side polishing apparatus (pad / carrier, etc.) as in the example. As a wafer to be polished, a P-type silicon single crystal wafer having a diameter of 300 mm was used as in the example.

  The same slurry as the example was used as the slurry containing the first abrasive grains. An abrasive-free slurry containing no abrasive grains was used as the slurry containing the second abrasive grains. Specifically, a solution obtained by adding HEC having a molecular weight of 200 to 300,000 to an amine-based aqueous solution having a pH of 11.0 was used.

Processing load in the primary polishing processing load at 100gf / ^cm 2, 2-polishing was set to 150 gf / cm ^2. The processing time was set so that the machining allowance in the primary polishing was 0.5 to 1.0 μm, and the machining allowance in the secondary polishing was 10 μm or more, so that the total machining allowance was almost the same as in the example. The rotation speed and dressing conditions were the same as in the example. The cleaning and epitaxial growth conditions were the same as in the examples.

[Flatness and surface quality]
The flatness of the wafer in Examples and Comparative Examples was measured using WaferSight manufactured by KLA Tencor. SFQRmax was calculated with a cell size of M49 mode of 26 × 8 mm (2 mm EE). The surface quality (LPD and surface roughness) in Examples and Comparative Examples was measured using Surfscan SP3 manufactured by KLA. The results are shown below.

  Hereinafter, all are average values of five wafers. All measurements are performed after washing. The flatness was measured on the wafer after primary polishing and before secondary polishing (in the case of Comparative Example 1, single-side CMP polishing, the same applies hereinafter) and on the wafer after secondary polishing and before epitaxial growth. The surface roughness was measured on the wafer after secondary polishing and before epitaxial growth. The LPD measurement was performed on the wafer after secondary polishing and before epitaxial growth and on the wafer after epitaxial growth.

  First, flatness will be described. Here, SFQR deterioration amount = (final SFQRmax−Y) / Y. In the formula, Y represents SFQRmax after primary polishing and before secondary polishing, and final SFQRmax represents SFQRmax after epitaxial polishing and before epitaxial growth.

  FIG. 5 is a graph showing the SFQR deterioration amount in Example and Comparative Example 1. As shown in FIG. 5, the SFQR deterioration amount of the example was 0.15, and the SFQR deterioration amount of Comparative Example 1 was less than 0.53. In Comparative Example 1, it is considered that the SFQR results deteriorated because single-side CMP polishing was performed. On the other hand, in the examples, the single-side CMP polishing is not performed, and the machining allowance in the secondary polishing is set to 1 μm or less (500 nm). Therefore, it is considered that the SFQR result is improved. Thereby, it is considered that the flatness of the wafer after epitaxial growth is also improved.

  Next, surface quality (LPD and surface roughness) will be described. The surface roughness of 1 × 1 μm was 0.215 nm in Comparative Example 2, whereas it was 0.118 nm in the Example. In Comparative Example 2, since the non-abrasive slurry was used at the time of secondary polishing, it was considered that the chemical action was strong and the surface roughness of the wafer was not sufficiently lowered. On the other hand, in the example using the abrasive slurry during the secondary polishing, the surface roughness was sufficiently lowered. Thereby, it became possible to measure the number of LPDs of 100 nm or less after double-side polishing.

  When the number of LPDs of 120 nm or more in the wafer after the secondary polishing and before epitaxial growth was compared, the number of LPDs in Comparative Example 2 was 69.7, whereas the number of LPDs in the example was 5.5. It was. That is, the number of LPDs was also improving.

  Next, the coincidence ratio between the LPD map after double-side polishing and the LPD map after epitaxial growth will be described. FIG. 6 is a diagram in which the LPD map after double-side polishing and the LPD map after epitaxial growth are overlapped in the example. FIG. 7 is a diagram in which the LPD map after double-side polishing and the LPD map after epitaxial growth are overlaid in Comparative Example 2. In FIG. 6, “before” indicates the position of LPD (70 nm or more) before epitaxial growth, and “after” indicates the position of LPD (45 nm or more) after epitaxial growth. In FIG. 7, “front” indicates the position of LPD (120 nm or more) before epitaxial growth, and “after” indicates the position of LPD (45 nm or more) after epitaxial growth.

  In Comparative Example 2, LPD up to 120 nm could be measured after double-side polishing, and the coincidence ratio with the measurement of LPD (45 nm or more) after epitaxial growth was 65% (see FIG. 7). That is, there were many LPDs that could not be detected at the time after double-side polishing (see arrows in FIG. 7). In contrast, in the example, LPD up to 70 nm or more can be measured after double-side polishing, and the coincidence ratio after epitaxial growth improved to 92% (see FIG. 6).

  In addition, the number of LPDs of 45 nm or more after epitaxial growth in the example was four. On the other hand, the number of LPDs after epitaxial growth in Comparative Example 1 was 3. From this result, it can be said that the number of LPDs of the epitaxial wafer obtained in Example and the number of LPDs of the epitaxial wafer obtained in Comparative Example 1 are substantially equal. From this, it can be seen that according to the present invention, the number of defects can be reduced to the same level as when single-side CMP polishing is performed while maintaining flatness.

  From the above results, it became clear that the epitaxial wafer manufacturing method of the present invention can stably manufacture an epitaxial wafer with few defects and good flatness.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Double-side polish apparatus, 2 ... Carrier, 3 ... Holding hole, 4 ... Polishing cloth, 5 ... Upper surface plate,
6 ... lower surface plate, 7 ... sun gear, 8 ... internal gear, 21 ... vapor phase growth apparatus,
22 ... Chamber, 23 ... Gas introduction pipe, 24 ... Gas discharge pipe, 25 ... Susceptor,
26 ... Susceptor rotation mechanism, 27 ... Heating means, 28 ... Chamber upper member,
29 ... Chamber lower member, 30 ... Gas inlet, 31 ... Gas outlet,
32 ... Shaft 33 ... Main strut 34 ... Sub strut 35 ... Counterbore W ... Wafer G ... Gas.

The epitaxial growth process, in addition to trichlorosilane as a raw material gas, it is possible to use monosilane, monochlorosilane, dichlorosilane, or tetrachloride silicofluoride-containing. In addition to the source gas, a dopant gas such as diborane (B ₂ H ₆ ) or phosphine (PH ₃ ) can be used together with the hydrogen gas.

Claims (5)

An epitaxial wafer manufacturing method comprising:
Using a double-side polishing apparatus comprising an upper and lower surface plate with a polishing cloth and a carrier for holding the silicon wafer between the upper and lower surface plates, while supplying slurry containing the first abrasive grains, A step of performing primary polishing for polishing both surfaces;
Secondary polishing the both sides of the silicon wafer after the primary polishing while supplying slurry containing second abrasive grains having an average particle size smaller than the first abrasive grains using the double-side polishing apparatus Polishing, and
And a step of growing an epitaxial layer on the silicon wafer surface after the secondary polishing without performing single-side CMP polishing. In the step of performing the primary polishing, as the slurry containing the first abrasive grains, an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 50 nm to 100 nm is used,
2. The epitaxial wafer according to claim 1, wherein an alkaline aqueous solution containing silica abrasive grains having an average particle diameter of 20 nm to 40 nm is used as the slurry containing the second abrasive grains in the step of performing the secondary polishing. Production method.   3. The method for manufacturing an epitaxial wafer according to claim 1, wherein, in the step of performing the secondary polishing, an allowance for the secondary polishing is set to 1 μm or less. 4.   4. The polishing cloth according to claim 1, wherein the polishing cloth is a polishing cloth made of polyurethane foam having a Shore A hardness of 85 to 95, and the carrier is a carrier having a surface Vickers hardness of 300 or more. The manufacturing method of the epitaxial wafer of claim | item.   5. The epitaxial wafer according to claim 1, wherein the surface quality of the silicon wafer after the secondary polishing is a surface quality that allows the number of LPDs of 100 nm or less to be measured. Production method.