JP2016195241A5 - - Google Patents

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Publication number
JP2016195241A5
JP2016195241A5 JP2016027459A JP2016027459A JP2016195241A5 JP 2016195241 A5 JP2016195241 A5 JP 2016195241A5 JP 2016027459 A JP2016027459 A JP 2016027459A JP 2016027459 A JP2016027459 A JP 2016027459A JP 2016195241 A5 JP2016195241 A5 JP 2016195241A5
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JP
Japan
Prior art keywords
breakdown voltage
slightly
examples
value width
higher tendency
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JP2016027459A
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English (en)
Japanese (ja)
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JP6239017B2 (ja
JP2016195241A (ja
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Priority to US15/084,119 priority Critical patent/US9530846B2/en
Publication of JP2016195241A publication Critical patent/JP2016195241A/ja
Publication of JP2016195241A5 publication Critical patent/JP2016195241A5/ja
Application granted granted Critical
Publication of JP6239017B2 publication Critical patent/JP6239017B2/ja
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JP2016027459A 2015-03-31 2016-02-16 窒化物半導体基板 Active JP6239017B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/084,119 US9530846B2 (en) 2015-03-31 2016-03-29 Nitride semiconductor substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015072914 2015-03-31
JP2015072914 2015-03-31

Publications (3)

Publication Number Publication Date
JP2016195241A JP2016195241A (ja) 2016-11-17
JP2016195241A5 true JP2016195241A5 (enrdf_load_stackoverflow) 2017-03-02
JP6239017B2 JP6239017B2 (ja) 2017-11-29

Family

ID=57323037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016027459A Active JP6239017B2 (ja) 2015-03-31 2016-02-16 窒化物半導体基板

Country Status (1)

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JP (1) JP6239017B2 (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6925117B2 (ja) 2016-11-18 2021-08-25 エア・ウォーター株式会社 化合物半導体基板の製造方法および化合物半導体基板
JP2019125737A (ja) * 2018-01-18 2019-07-25 株式会社サイオクス 窒化物半導体エピタキシャル基板
JP7100871B6 (ja) * 2018-03-02 2022-08-17 国立大学法人東海国立大学機構 Iii族窒化物半導体素子の製造方法
US11515408B2 (en) 2020-03-02 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Rough buffer layer for group III-V devices on silicon

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5456783B2 (ja) * 2009-08-07 2014-04-02 日本碍子株式会社 半導体素子用エピタキシャル基板、半導体素子用エピタキシャル基板の製造方法、および半導体素子
JP2012015304A (ja) * 2010-06-30 2012-01-19 Sumitomo Electric Ind Ltd 半導体装置
JP5891650B2 (ja) * 2011-08-18 2016-03-23 富士通株式会社 化合物半導体装置及びその製造方法
JP5465295B2 (ja) * 2012-08-31 2014-04-09 富士通株式会社 化合物半導体装置、およびその製造方法
JP6055325B2 (ja) * 2013-01-30 2016-12-27 シャープ株式会社 窒化物半導体結晶の製造方法
JP6108609B2 (ja) * 2013-04-25 2017-04-05 クアーズテック株式会社 窒化物半導体基板
JP5787417B2 (ja) * 2013-05-14 2015-09-30 コバレントマテリアル株式会社 窒化物半導体基板
JP6261523B2 (ja) * 2015-01-08 2018-01-17 信越半導体株式会社 電子デバイス用エピタキシャル基板の製造方法、並びに電子デバイスの製造方法

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