JP2016181729A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SGT manufacturing method which reduces parasitic capacitance between gate wiring and a substrate and which is a gate last process; and provide an SGT structure.SOLUTION: A semiconductor device manufacturing method comprises: a step of forming a fin-shaped silicon layer on a silicon substrate and forming a first insulation film around the fin-shaped silicon layer and forming a columnar silicon layer above the fin-shaped silicon layer; a step of implanting an impurity on the columnar silicon layer and on the fin-shaped silicon layer and under the columnar silicon layer to form diffusion layers; a step of forming a gate insulation film, a polysilicon gate electrode and polysilicon gate wiring; a step of forming a silicide on the diffusion layer on the fin-shaped silicon layer; a step of depositing an interlayer insulation film and exposing the polysilicon gate electrode and the polysilicon gate wiring, and etching the polysilicon gate electrode and the polysilicon gate wiring, and subsequently depositing metal to form a metal gate electrode and metal gate wiring; and a step of forming contacts.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Semiconductor integrated circuits, in particular, integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. As the miniaturization of MOS transistors progresses, there is a problem that it is difficult to suppress the leakage current, and the area occupied by the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds a columnar semiconductor layer has been proposed (for example, Patent Documents). 1, Patent Document 2, Patent Document 3).

  By using metal instead of polysilicon for the gate electrode, depletion can be suppressed and the resistance of the gate electrode can be reduced. However, the post-process after forming the metal gate must always be a manufacturing process that considers metal contamination by the metal gate.

    Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process. In SGT, since the upper part of the columnar silicon layer is higher than the gate, it is necessary to devise for using the metal gate last process.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Accordingly, an object of the present invention is to reduce the parasitic capacitance between the gate wiring and the substrate, and to provide an SGT manufacturing method which is a gate last process and an SGT structure as a result.

A method for manufacturing a semiconductor device of the present invention includes:
Forming a fin-like silicon layer on the silicon substrate, forming a first insulating film around the fin-like silicon layer;
A first step of forming a columnar silicon layer on top of the fin-like silicon layer;
The columnar silicon layer has the same diameter as the fin-shaped silicon layer,
After the first step,
A second step of injecting impurities into the upper part of the columnar silicon layer, the upper part of the fin-like silicon layer, and the lower part of the columnar silicon layer to form a diffusion layer;
After the second step,
A third step of creating a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring;
The gate insulating film covers the periphery and top of the columnar silicon layer, the polysilicon gate electrode covers the gate insulating film, and the upper surface of the polysilicon after the formation of the polysilicon gate electrode and the polysilicon gate wiring is the columnar silicon. A position higher than the gate insulating film on the diffusion layer above the layer;
After the third step,
A fourth step of forming silicide on the diffusion layer above the fin-like silicon layer;
After the fourth step,
An interlayer insulating film is deposited, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are etched, a metal is deposited, a metal gate electrode and a metal gate wiring, A fifth step of forming
A metal gate wiring extending in a direction perpendicular to the fin-like silicon layer connected to the metal gate electrode,
After the fifth step,
A sixth step of forming contacts;
The diffusion layer above the columnar silicon layer and the contact are directly connected,
It is characterized by having.

Forming a first resist for forming a fin-like silicon layer on the silicon substrate;
Etching a silicon substrate to form the fin-like silicon layer, removing the first resist,
A first insulating film is deposited around the fin-shaped silicon layer, the first insulating film is etched back, an upper portion of the fin-shaped silicon layer is exposed, and the first insulating film is perpendicular to the fin-shaped silicon layer. 2 is formed, the fin-like silicon layer is etched, and the second resist is removed, so that the portion where the fin-like silicon layer and the second resist are orthogonally becomes the columnar silicon layer. The columnar silicon layer is formed as described above.

A fin-like silicon layer formed on the silicon substrate; a first insulating film formed around the fin-like silicon layer; and a columnar silicon layer formed on the fin-like silicon layer. In the structure,
A second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched, remains in a sidewall shape, an impurity is implanted, and the columnar shape is formed. A diffusion layer is formed on the silicon layer and the fin-like silicon layer, the first nitride film and the second oxide film are removed, and heat treatment is performed.

A fin-like silicon layer formed on the silicon substrate; a first insulating film formed around the fin-like silicon layer; a columnar silicon layer formed on the fin-like silicon layer;
A diffusion layer formed in an upper portion of the fin-like silicon layer and a lower portion of the columnar silicon layer;
A diffusion layer formed on top of the columnar silicon layer;
In the structure having
Forming a gate insulating film, depositing polysilicon, and planarizing the polysilicon so that the upper surface of the polysilicon is higher than the gate insulating film on the diffusion layer above the columnar silicon layer Depositing a second nitride film, forming a third resist for forming a polysilicon gate electrode and a polysilicon gate wiring, etching the second nitride film, etching the polysilicon, A polysilicon gate electrode and the polysilicon gate wiring are formed, the gate insulating film is etched, and the third resist is removed.

  Also, a third nitride film is deposited, the third nitride film is etched, remains in a sidewall shape, a metal is deposited, and silicide is formed above the diffusion layer above the fin-like silicon layer. It is characterized by.

  In addition, a fourth nitride film is deposited, an interlayer insulating film is deposited and planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, and the polysilicon Metal is embedded in the portion where the silicon gate electrode and the polysilicon gate wiring were present, the metal is etched, the gate insulating film on the diffusion layer above the columnar silicon layer is exposed, and a metal gate electrode and a metal gate wiring are formed. It is characterized by that.

The semiconductor device of the present invention is
A fin-like silicon layer formed on a silicon substrate;
A first insulating film formed around the fin-like silicon layer;
A columnar silicon layer formed on the fin-like silicon layer;
The columnar silicon layer has the same diameter as the fin-shaped silicon layer,
A diffusion layer formed in an upper portion of the fin-like silicon layer and a lower portion of the columnar silicon layer;
A diffusion layer formed on top of the columnar silicon layer;
Silicide formed on top of the diffusion layer above the fin-like silicon layer;
A gate insulating film formed around the columnar silicon layer;
A metal gate electrode formed around the gate insulating film;
A metal gate wiring extending in a direction orthogonal to the fin-like silicon layer connected to the metal gate electrode;
A contact formed on a diffusion layer formed on the top of the columnar silicon layer,
The diffusion layer formed on the columnar silicon layer and the contact are directly connected.

According to the present invention, the parasitic capacitance between the gate wiring and the substrate can be reduced, and the SGT manufacturing method as the gate last process and the SGT structure as a result can be provided.
Since the fin-like silicon layer, the first insulating film, and the columnar silicon layer are formed on the basis of a conventional method for manufacturing a FINFET, they can be easily formed.
In addition, conventionally, silicide is formed on the columnar silicon layer, but since the deposition temperature of polysilicon is higher than the temperature for forming silicide, the silicide must be formed after forming the polysilicon gate.
If silicide is to be formed on the top of the silicon pillar, after forming the polysilicon gate, a hole is formed in the upper portion of the polysilicon gate electrode, a sidewall of the insulating film is formed on the sidewall of the hole, silicide is then formed, and the hole is formed. Therefore, the diffusion layer is formed before forming the polysilicon gate electrode and the polysilicon gate wiring, the columnar silicon layer is covered with the polysilicon gate electrode, and the silicide is finned. The gate is made of polysilicon by forming it only on the upper part of the silicon layer, and then the interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and the metal is deposited. Since the conventional metal gate last manufacturing method can be used, the metal gate SGT can be easily formed. It can be formed.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a manufacturing method in which a fin-like silicon layer is formed on a silicon substrate, a first insulating film is formed around the fin-like silicon layer, and a columnar silicon layer is formed on the fin-like silicon layer will be described. As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. An oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition may be used as the first insulating film.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed. The process up to here is the same as the method for manufacturing the fin-like silicon layer of Patent Document 2.

  As shown in FIG. 7, a second resist 105 is formed so as to be orthogonal to the fin-like silicon layer 103. A portion where the fin-like silicon layer 103 and the resist 105 are orthogonal to each other is a portion that becomes a columnar silicon layer. Since a line-shaped resist can be used, the possibility that the resist falls after patterning is low, and the process is stable.

  As shown in FIG. 8, the fin-like silicon layer 103 is etched. A portion where the fin-like silicon layer 103 and the second resist 105 are orthogonally becomes the columnar silicon layer 106. Therefore, the diameter of the columnar silicon layer 106 is the same as the width of the fin-like silicon layer. A columnar silicon layer 106 is formed on the fin-shaped silicon layer 103, and a first insulating film 104 is formed around the fin-shaped silicon layer 103.

  As shown in FIG. 9, the second resist 105 is removed.

  Next, a manufacturing method for forming a diffusion layer by implanting impurities into the upper part of the columnar silicon layer, the upper part of the fin-like silicon layer, and the lower part of the columnar silicon layer in order to obtain the gate last will be described. As shown in FIG. 10, the 2nd oxide film 107 is deposited and the 1st nitride film 108 is formed. Later, since the upper part of the columnar silicon layer is covered with the gate insulating film and the polysilicon gate electrode, a diffusion layer is formed on the upper part of the columnar silicon layer before being covered.

  As shown in FIG. 11, the first nitride film 108 is etched to remain in a sidewall shape.

  As shown in FIG. 12, impurities such as arsenic, phosphorus, and boron are implanted to form a diffusion layer 110 on the columnar silicon layer and diffusion layers 109 and 111 on the fin-like silicon layer 103.

  As shown in FIG. 13, the first nitride film 108 and the second oxide film 107 are removed.

  Heat treatment is performed as shown in FIG. The diffusion layers 109 and 111 above the fin-like silicon layer 103 come into contact with each other to become a diffusion layer 112. As described above, in order to obtain the gate last, impurities are implanted into the upper part of the columnar silicon layer, the upper part of the fin-like silicon layer, and the lower part of the columnar silicon layer to form the diffusion layers 110 and 112.

  Next, a manufacturing method for forming a polysilicon gate electrode and a polysilicon gate wiring with polysilicon in order to obtain a gate last will be described. Since the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after depositing an interlayer insulating film for gate last, it is necessary to prevent the upper portion of the columnar silicon layer from being exposed by chemical mechanical polishing. .

As shown in FIG. 15, a gate insulating film 113 is formed, and polysilicon 114 is deposited and planarized. The upper surface of the planarized polysilicon is higher than the gate insulating film 113 on the diffusion layer 110 above the columnar silicon layer 106. As a result, when the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after depositing an interlayer insulating film to form gate last, the upper part of the columnar silicon layer is not exposed by chemical mechanical polishing.
A second nitride film 115 is deposited. The second nitride film 115 is a film that inhibits the formation of silicide on the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed on the fin-like silicon layer.

  As shown in FIG. 16, the 3rd resist 116 for forming a polysilicon gate electrode and a polysilicon gate wiring is formed. It is desirable that a portion to be a gate wiring is orthogonal to the fin-like silicon layer 103. This is because the parasitic capacitance between the gate wiring and the substrate is reduced.

  As shown in FIG. 17, the second nitride film 115 is etched.

  As shown in FIG. 18, the polysilicon 114 is etched to form a polysilicon gate electrode 114a and a polysilicon gate wiring 114b.

  As shown in FIG. 19, the gate insulating film 113 is etched.

As shown in FIG. 20, the third resist 116 is removed.
In order to obtain the gate last as described above, a manufacturing method for forming a polysilicon gate electrode and a polysilicon gate wiring with polysilicon has been shown. The upper surface of the polysilicon after forming the polysilicon gate electrode 114a and the polysilicon gate wiring 114b is higher than the gate insulating film 113 on the diffusion layer 110 above the columnar silicon layer 106.

Next, a manufacturing method for forming silicide on the fin-like silicon layer will be described. A feature is that no silicide is formed in the diffusion layer 110 above the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b and above the columnar silicon layer 106. If silicide is formed in the diffusion layer 110 on the columnar silicon layer 106, the number of manufacturing steps increases.
As shown in FIG. 21, a third nitride film 117 is deposited.

  As shown in FIG. 22, the third nitride film 117 is etched and left in a sidewall shape.

As shown in FIG. 23, a metal such as nickel or cobalt is deposited, and a silicide 118 is formed on the diffusion layer 112 above the fin-like silicon layer 103. At this time, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are covered with the third nitride film 117 and the second nitride film 115, and the diffusion layer 110 on the columnar silicon layer 106 is connected to the gate insulating film 113 and the polysilicon film. Since it is covered with the silicon gate electrode 114a and the polysilicon gate wiring 114b, no silicide is formed.
Thus, a manufacturing method for forming silicide on the fin-like silicon layer has been shown.

Next, after depositing an interlayer insulating film, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing, and after etching the polysilicon gate electrode and the polysilicon gate wiring, a gate last manufacturing method for depositing metal Show.
As shown in FIG. 24, a fourth nitride film 140 is deposited to protect the silicide 118.

  As shown in FIG. 25, an interlayer insulating film 119 is deposited and planarized by chemical mechanical polishing.

  As shown in FIG. 26, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are exposed by chemical mechanical polishing.

  As shown in FIG. 27, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are etched. Wet etching is desirable.

  As shown in FIG. 28, the metal 120 is deposited and planarized, and the metal 120 is buried in the portion where the polysilicon gate electrode 114a and the polysilicon gate wiring 114b were present. It is preferred to use atomic layer deposition.

  As shown in FIG. 29, the metal 120 is etched to expose the gate insulating film 113 on the diffusion layer 106 above the columnar silicon layer 106. A metal gate electrode 120a and a metal gate wiring 120b are formed. A method of manufacturing a gate last in which an interlayer insulating film is deposited, a polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and a metal is deposited is shown.

  Next, a manufacturing method for forming contacts will be described. Since no silicide is formed in the diffusion layer 110 above the columnar silicon layer 106, the contact and the diffusion layer 110 above the columnar silicon layer 106 are directly connected. As shown in FIG. 30, an interlayer insulating film 121 is deposited and planarized.

  As shown in FIG. 31, the 4th resist 122 for forming a contact hole is formed in the columnar silicon layer 106 upper part.

  As shown in FIG. 32, the interlayer insulating film 121 is etched to form a contact hole 123.

  As shown in FIG. 33, the 4th resist 122 is removed.

  As shown in FIG. 34, the 5th resist 124 for forming a contact hole on the metal gate wiring 120b and the fin-like silicon layer 103 is formed.

  As shown in FIG. 35, the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126.

  As shown in FIG. 36, the fifth resist 124 is removed.

  As shown in FIG. 37, the nitride film 140 and the gate insulating film 113 are etched to expose the silicide 118 and the diffusion layer 110.

  As shown in FIG. 38, metal is deposited to form contacts 143, 127, and 128. Thus, a manufacturing method for forming a contact has been shown. Since no silicide is formed in the diffusion layer 110 above the columnar silicon layer 106, the contact 127 and the diffusion layer 110 above the columnar silicon layer 106 are directly connected.

Next, a manufacturing method for forming the metal wiring layer will be described.
As shown in FIG. 39, metal 129 is deposited.

  As shown in FIG. 40, sixth resists 130, 131, and 132 for forming metal wiring are formed.

  As shown in FIG. 41, the metal 129 is etched to form metal wirings 133, 134, and 135.

As shown in FIG. 42, the sixth resists 130, 131, and 132 are removed.
Thus, a manufacturing method for forming a metal wiring layer has been shown.

The result of the manufacturing method is shown in FIG.
A fin-like silicon layer 103 formed on the substrate 101;
A first insulating film 104 formed around the fin-like silicon layer 103;
A columnar silicon layer 106 formed on the fin-shaped silicon layer 103;
The diameter of the columnar silicon layer 106 is the same as the width of the fin-like silicon layer 103, and
A diffusion layer 112 formed above the fin-like silicon layer 103 and below the columnar silicon layer 106;
A diffusion layer 110 formed on top of the columnar silicon layer 106;
A silicide 118 formed on the diffusion layer 112 above the fin-like silicon layer 103;
A gate insulating film 113 formed around the columnar silicon layer 106;
A metal gate electrode 120a formed around the gate insulating film;
A metal gate wiring 120b extending in a direction perpendicular to the fin-like silicon layer 103 connected to the metal gate electrode 120a;
A contact 127 formed on the diffusion layer 110;
The diffusion layer 110 and the contact 127 are directly connected.

  As described above, the parasitic capacitance between the gate wiring and the substrate can be reduced, and the SGT manufacturing method as the gate last process and the resulting SGT structure can be provided.

DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Resist 103 Fin-like silicon layer 104 1st insulating film 105 Resist 106 Columnar silicon layer 107 Oxide film 108 Film 109 which inhibits impurity implantation Diffusion layer 110 Diffusion layer 111 Diffusion layer 112 Diffusion layer 113 Gate insulation film 114 Poly Silicon 114a Polysilicon gate electrode 114b Polysilicon gate wiring 115 Nitride film 116 Resist 117 Nitride film 118 Silicide 119 Interlayer insulating film 120 Metal 121 Interlayer insulating film 122 Resist 123 Contact hole 124 Resist 125 Contact hole 126 Contact hole 127 Contact 128 Contact 129 Metal 130 resist 131 resist 132 resist 133 metal wiring 134 metal wiring 135 metal wiring 140 nitride film 143 contact

Claims (1)

  Etching a silicon substrate, forming a fin-like silicon layer, and after forming the fin-like silicon layer, depositing a first insulating film around the fin-like silicon layer, etching back the first insulating film, An upper portion of the fin-shaped silicon layer is exposed, a second resist is formed so as to be orthogonal to the fin-shaped silicon layer, and the fin-shaped silicon layer is etched, whereby the fin-shaped silicon layer and the second silicon layer are etched. A method of manufacturing a semiconductor device, wherein the columnar silicon layer is formed so that a portion orthogonal to the resist becomes a columnar silicon layer.

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