JP2016174455A - Drive circuit for switching element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a novel drive circuit for switching elements that is capable of suppressing switching loss.SOLUTION: A drive circuit monotonously increases a command discharge current of a gate of a switching element and sets it during a main discharge period (t2-t3). The drive circuit switches a switching element to an off state by controlling a gate discharge current to a preset command discharge current. Additionally, the drive circuit monotonously decreases a command charge current of the gate of the switching element and sets it during a main charge period. The drive circuit then switches the switching element to an on state by controlling a gate charge current to the preset command charge current.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a switching element drive circuit for switching an operation state of the switching element by moving a charge at an open / close control terminal of the switching element when a switching command of an operation state of the switching element is input.

  As this type of drive circuit, as shown in the following Patent Document 1, an on-off operation of a switching element of an upper arm and a switching element of a lower arm is known. Specifically, in this circuit, the switching speed of the switching element on the side of the upper and lower arms on which the operation state is to be switched (hereinafter referred to as the own arm) to the ON state is switched (hereinafter referred to as the operation state is not switched). , The opposite arm) is set based on the detected value of the current flowing in the free wheel diode connected in antiparallel to the switching element. Thereby, the switching loss is reduced.

JP 2011-10441 A

  Here, in the drive circuit described in Patent Document 1, the detection value of the current flowing through the free wheel diode of the opposite arm is required to set the switching speed of the switching element of the own arm to the on state. A certain amount of time is required from the detection of the current flowing through the free wheel diode of the opposite arm to the setting of the switching speed of the switching element of the own arm based on the detected current value. For this reason, when there is a time restriction on the setting of the switching speed, it is possible that the switching speed setting method based on the current detection value of the opposite arm cannot be adopted. In the driving circuit described in Patent Document 1, a detection circuit for the current flowing through the free wheel diode of the opposite arm is required for setting the switching speed, and the number of components increases. As described above, the drive circuit for reducing the switching loss still leaves room for improvement.

  The main object of the present invention is to provide a drive circuit for a new switching element that can reduce switching loss.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  According to the present invention, switching is performed by switching the operation state of the switching element by moving the charge of the switching control terminal of the switching element when a switching command of the operation state of the switching element (Scp, Scn, Sup to Swn) is input. In the element drive circuit, when the switching command is input, a period in the middle from the start of movement of the charge of the open / close control terminal to switch the operation state until the completion of the movement of the charge is a specified period. A command current of the switching control terminal in the specified period that does not depend on a current flowing between the input and output terminals of the switching element, and a command value that is set by monotonically changing the command current over time in the specified period In order to switch the operating state of the setting means (70) and the switching element, the command A current control means for controlling the current of the open-close control terminal set the command current by the setting means (62～65,66～69,70), characterized in that it comprises a.

  In the following description, the current of the switching control terminal required for switching the operating state of the switching element, which is the upper limit current of the switching control terminal that can avoid a decrease in reliability of the semiconductor element such as the switching element, is defined as the rate-limiting current. I will call it. In addition, the timing for determining the rate-limiting current in the period after the switching command is input and before the movement of the charge at the switching control terminal is completed is referred to as a rate-limiting point.

  As the current flowing between the input / output terminals of the switching element (hereinafter referred to as main current) increases, the rate-limiting current decreases. In addition, the time from when the switching command is input to when the rate determining point is reached depends on the main current.

  Here, when the inventor of this application plots the rate-limiting current at the rate-limiting point corresponding to various main currents on the time axis, the waveform of the rate-limiting current becomes a waveform that changes monotonously with time while maintaining the sign of the slope. I found out. Even if the rate-limiting current corresponding to the main current continues to flow over the period from the input of the switching command to the rate-limiting point corresponding to the main current, the reliability of the semiconductor element such as the switching element does not decrease. For this reason, after the switching command is input, the current of the switching control terminal at each rate-limiting point corresponding to various main currents is set to be equal to or less than each rate-limiting current corresponding to various main currents. It is possible to avoid a decrease in the reliability of the semiconductor element when switching between the two.

  From the viewpoint of reducing switching loss, it is desirable to increase the current at the switching control terminal as much as possible. For this reason, the switching loss when switching the operation state is reduced by controlling the current of the switching control terminal at each rate-limiting point corresponding to various main currents so as to follow the rate-limiting current that changes monotonically with time. Can do. In other words, the current of the switching control terminal has elapsed over a specified period, which is a period from when the charge of the switching control terminal starts to move due to the input of the switching command until the movement of the charge of the switching control terminal is completed. In addition, switching loss can be reduced by monotonously changing the switching loss.

  In view of this point, in the above invention, the command value is set by monotonously changing the command current with time in the specified period by the command value setting means. The current control means controls the current of the switching control terminal to the command current set by the command value setting means in order to switch the operation state of the switching element. Thereby, switching loss can be reduced, avoiding the fall of the reliability of semiconductor elements, such as a switching element.

  Further, in the above invention, the command current in the specified period is set to a value that does not depend on the main current. This setting is possible because the command current at each timing in the specified period is set using a rate-limiting current determined based on various main currents. As a result, the process of changing the setting of the command current in accordance with the main current can be made unnecessary, so that it is possible to suppress an increase in arithmetic processing capability required for the drive circuit. In addition, since the detection circuit for detecting the main current can be eliminated, an increase in the number of components of the drive circuit can be suppressed.

  Here, the said invention can be actualized as follows, for example.

  The specified period is a main discharge that is an intermediate period from when the charge of the open / close control terminal starts to be discharged until the discharge of the charge is completed by inputting an OFF command for switching the operation state to the OFF state. The command value setting means includes a discharge command value setting means for monotonously increasing the command discharge current of the switching control terminal with time in the main discharge period, and the current control means includes the Discharge control means (66 to 69, 70) for controlling the discharge current of the switching control terminal to the command discharge current set by the discharge command value setting means in order to switch the switching element to the OFF state.

  In the following description, the discharge current of the switching control terminal required to switch the switching element from the on state to the off state, and the upper limit discharge current of the switching control terminal that can avoid the deterioration of the switching element reliability is turned off. It will be referred to as a rate limiting current. Also, the timing for determining the off-rate-limiting current, which is in the middle of the discharge of the charge at the switching control terminal after the OFF command is input, is referred to as an off-rate-limiting point.

  The larger the main current immediately before the input of the off command, the smaller the off rate limiting current. Further, the larger the main current immediately before the input of the OFF command, the shorter the time from when the OFF command is input until the OFF rate-limiting point is reached.

  Here, the inventor of the present application has found that when the off-rate limiting current at the off-rate limiting point corresponding to various main currents is plotted on the time axis, the waveform of the off-rate limiting current becomes a waveform that monotonously increases with time. For this reason, after the OFF command is input, the switching current at the switching control terminal at each off-rate control point corresponding to various main currents is made equal to or less than each off-rate limiting current corresponding to various main currents. The switching loss can be reduced while avoiding the deterioration of the reliability of the switching element when switching to the OFF state. In view of this point, the above invention includes the discharge command value setting means and the discharge control means.

  Moreover, the said invention can also be actualized as follows, for example.

  The specified period is a main charge period in which the charge is charged to the open / close control terminal after the on command to switch the operation state to the on state is input and the charge charge is completed. The command value setting means includes charge command value setting means for monotonously decreasing the command charge current of the switching control terminal over time in the main charge period, and the current control means includes the Charge control means (62 to 65, 70) for controlling the charge current of the open / close control terminal to the command charge current set by the charge command value setting means to switch the switching element to the ON state.

  In the following description, it is the charging current of the switching control terminal required for switching the switching element from the OFF state to the ON state, and it is possible to avoid a decrease in the reliability of the semiconductor element (for example, the free wheel diode of the opposite arm) The upper limit charging current of the open / close control terminal is referred to as an on-rate limiting current. In addition, the timing for determining the on-rate-limiting current, which is an intermediate timing from the input of the on-command to the completion of charging of the charge of the switching control terminal, is referred to as an on-rate-limiting point.

  The larger the main current that flows after the ON command is input, the smaller the ON-controlled current. Further, the larger the main current that flows after the ON command is input, the longer the time from when the ON command is input until the ON rate-limiting point is reached.

  Here, the present inventor has found that when the on-rate limiting current at the on-rate limiting point corresponding to various main currents is plotted on the time axis, the waveform of the on-rate limiting current becomes a waveform that monotonously decreases with time. For this reason, after the ON command is input, the switching current at the ON / OFF control terminal corresponding to various main currents is set to be equal to or lower than the ON current limiting current corresponding to various main currents, thereby switching elements. The switching loss can be reduced while avoiding a decrease in the reliability of the semiconductor element when switching to the ON state. In view of this point, the above invention includes the charge command value setting means and the charge control means.

1 is an overall configuration diagram of an in-vehicle motor control system according to a first embodiment. The figure which shows the structure of a drive circuit. The figure which shows the relationship between a collector current, a gate discharge current, and a surge voltage. The figure for demonstrating a surge voltage. The figure which shows the relationship between a collector current and an off-rate limited current. The time chart which shows the relationship between a collector current and an OFF rate control point. The time chart which shows transition of gate command discharge current. The time chart which shows transition of each gate discharge current of this embodiment, constant voltage control, and constant current control. The figure which shows the improvement effect of the switching speed to the OFF state concerning this embodiment. The figure which shows the relationship between collector current, gate charge current, and collector current speed. The figure for demonstrating collector current speed. The figure which shows the relationship between a collector current and an ON rate-limiting current. The time chart which shows the relationship between a collector current and an ON rate-limiting point. The time chart which shows transition of gate command charge current. The time chart which shows transition of each gate charge current of this embodiment, constant voltage control, and constant current control. The time chart which shows transition of the gate command discharge current concerning a 2nd embodiment. The time chart for demonstrating the dead time reduction effect at the time of OFF. The time chart which shows transition of gate command charge current. The time chart for demonstrating the dead time reduction effect at the time of ON. The time chart which shows transition of the gate command discharge current concerning a 3rd embodiment. The time chart for demonstrating the switching loss reduction effect at the time of OFF. The time chart which shows transition of gate command charge current. The time chart for demonstrating the switching loss reduction effect at the time of ON. The figure which shows the relationship between the collector current concerning 4th Embodiment, a power supply voltage, and an OFF rate-limiting current. The time chart which shows an example of the setting of the command discharge current according to a power supply voltage. The figure which shows the relationship between a collector current, a power supply voltage, and an ON rate limiting current. The time chart which shows an example of the setting of the command charge current according to a power supply voltage. The time chart which shows the setting method of the command discharge current according to the power supply voltage concerning other embodiment. The time chart which shows the setting method of the command charge current according to the power supply voltage concerning other embodiment.

(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to a vehicle equipped with a rotating electrical machine (motor generator) as an in-vehicle main machine will be described with reference to the drawings.

<1. Description of basic configuration>
First, the basic configuration of this embodiment will be described. As shown in FIG. 1, the vehicle includes a high voltage battery 10, a buck-boost converter 20, an inverter 30, a motor generator 40, and a control device 50.

  The motor generator 40 is an in-vehicle main machine, and can transmit power to drive wheels (not shown). The motor generator 40 is electrically connected to the high voltage battery 10 via the inverter 30 and the step-up / step-down converter 20. In the present embodiment, a three-phase motor generator 40 is used. As the motor generator 40, for example, a permanent magnet synchronous motor can be used. Moreover, the high voltage battery 10 is a storage battery which has the voltage between terminals which becomes 100 V or more, for example. As the high voltage battery 10, for example, a lithium ion storage battery or a nickel hydride storage battery can be used.

  The step-up / step-down converter 20 includes a first capacitor 21, a second capacitor 22, a reactor 23, and series connection bodies of upper and lower arm step-up switching elements Scp and Scn. Specifically, the high voltage battery 10 is connected to the first capacitor 21 in parallel. A connection point of each step-up switching element Scp, Scn is connected to the first end of the first capacitor 21 via a reactor 23. A second capacitor 22 is connected in parallel to the series connection body of the step-up switching elements Scp and Scn. The step-up / step-down converter 20 has a function of boosting the DC voltage output from the high-voltage battery 10 and outputting the boosted voltage to the inverter 30 during powering driving in which an AC voltage is output from the inverter 30 to the motor generator 40. Further, the step-up / down converter 20 steps down the DC voltage output from the inverter 30 during regenerative driving in which the AC voltage output from the motor generator 40 is converted into a DC voltage by the inverter 30 and output to the step-up / down converter 20. And has a function of outputting to the high voltage battery 10.

  Incidentally, in the present embodiment, voltage control type semiconductor switching elements are used as Scp and Scn with each step-up switching element, and specifically, an IGBT is used. Each freewheeling diode Dcp, Dcn is connected in antiparallel to each step-up switching element Scp, Scn.

  The inverter 30 includes three sets of U, V, W phase upper arm switching elements Sup, Svp, Swp and U, V, W phase lower arm switching elements Sun, Svn, Swn connected in series. Each series connection body is connected in parallel to the second capacitor 22. One end of the U, V, W phase windings of the motor generator 40 is connected to the connection point of each series connection body.

  Incidentally, in this embodiment, a voltage-controlled semiconductor switching element is used as Sup to Swn with each switching element, and specifically, an IGBT is used. Each freewheel diode Dup, Dun, Dvp, Dvn, Dwp, Dwn is connected in antiparallel to each switching element Sup, Sun, Svp, Svn, Swp, Swn. Instead of the step-up / step-down converter 20, the inverter 30 may include a second capacitor 22.

  The control system according to the present embodiment includes a first voltage sensor 41 and a second voltage sensor 42. The first voltage sensor 41 is a first voltage detection unit that detects a voltage between terminals of the first capacitor 21, and the second voltage sensor 42 is a second voltage detection unit that detects a voltage between terminals of the second capacitor 22. is there.

  Detection values of the voltage sensors 41 and 42 are input to the control device 50. Control device 50 operates buck-boost converter 20 and inverter 30 to control the control amount (for example, torque) of motor generator 40 to the command value. Specifically, control device 50 generates operation signals gcp, gcn for turning on / off each boost switching element Scp, Scn of buck-boost converter 20 based on the detection value of each voltage sensor 41, 42, and each boost switching. It outputs to the drive circuit Dr provided separately for the elements Scp and Scn. The operation signals gcp and gcn take either an on command for instructing switching of the step-up switching elements Scp and Scn to an on state or an off command for instructing switching to an off state. Thereby, each step-up switching element Scp, Scn is turned on / off. In the present embodiment, during powering driving, the lower arm boost switching element Scn is turned on and off, and the upper arm boost switching element Scp is maintained in the off state. On the other hand, during regenerative driving, upper arm boost switching element Scp is turned on and off, and lower arm boost switching element Scn is maintained in the off state.

  The control device 50 sends operation signals gup, ung, gvp, gvn, gwp, gwn to the switching elements Sup to Swn in order to turn on / off the switching elements Sup, Sun, Svp, Svn, Swp, Swn of the inverter 30. To the drive circuit Dr provided individually. In the present embodiment, the operation signals gup, gun, gvp, gvn, gwp, and the operation signals gup, gun, gvp, gvp, gwp, gwn is generated. The operation signals gup to gwn take either an on command for instructing switching of the switching elements Sup to Swn to an on state or an off command for instructing switching to an off state. The operation signals gup, gvp, and gwp on the upper arm side and the corresponding operation signals gun, gvn, and gwn on the lower arm side are complementary to each other. Therefore, the upper arm switching elements Sup, Svp, Swp and the corresponding lower arm switching elements Sun, Svn, Swn are alternately turned on with a dead time interposed therebetween.

  Next, the configuration of the drive circuit Dr will be described with reference to FIG. The drive circuits Dr corresponding to the switching elements Scp, Scn, Sup to Swn in the present embodiment have basically the same configuration. FIG. 2 illustrates the drive circuit Dr corresponding to the U-phase upper arm switching element Sup of the inverter 30.

  As shown in the figure, power is supplied from the constant voltage power supply 60 to the drive circuit Dr. In FIG. 2, the output voltage of the constant voltage power supply 60 is indicated by “Vom”. In the present embodiment, the output voltage Vom of the constant voltage power supply 60 becomes the upper limit voltage of the potential difference (hereinafter referred to as gate voltage) of the gate (opening / closing control terminal) with respect to the emitter (output terminal) of the switching element Sup. The lower limit voltage of the gate voltage is the emitter potential (0). The drive circuit Dr includes an integrated circuit 61 that is made into one chip. A first terminal T1 of the integrated circuit 61 is connected to the constant voltage power supply 60 via a charging resistor 62. The gate of the switching element Sup is connected to the first terminal T1 via the P-channel MOSFET (hereinafter, charging switching element 63) and the second terminal T2 of the integrated circuit 61.

  The inverting input terminal of the first operational amplifier 64 is connected to the first terminal T1. The positive terminal of the first power supply 65 is connected to the non-inverting input terminal of the first operational amplifier 64, and the emitter of the switching element Sup is connected to the negative terminal of the first power supply 65 via the third terminal T3 of the integrated circuit 61. It is connected. The first power supply 65 is configured so that its output voltage can be variably set. According to such a configuration, the on-resistance of the charging switching element 63 is adjusted, and the potential difference of the first terminal T1 with respect to the third terminal T3 (emitter) can be set as the output voltage of the first power supply 65. That is, the gate charging current can be controlled by adjusting the output voltage of the first power supply 65. Incidentally, the configuration for controlling the gate charging current is not limited to the configuration shown in FIG.

  The gate of the switching element Sup is connected to the fifth terminal T5 of the integrated circuit 61 via a fourth terminal T4 of the integrated circuit 61 and an N-channel MOSFET (hereinafter, discharge switching element 66). A third terminal T3 is connected to the fifth terminal T5 via a discharging resistor 67.

  The inverting input terminal of the second operational amplifier 68 is connected to the fifth terminal T5. The non-inverting input terminal of the second operational amplifier 68 is connected to the positive terminal of the second power source 69, and the negative terminal of the second power source 69 is connected to the third terminal T 3. The second power supply 69 is configured so that its output voltage can be variably set. According to such a configuration, the on-resistance of the discharge switching element 66 is adjusted, and the potential of the fifth terminal T5 with respect to the third terminal T3 can be set as the output voltage of the second power supply 69. That is, the gate discharge current can be controlled by adjusting the output voltage of the second power source 69. Incidentally, the configuration for controlling the gate discharge current is not limited to the configuration shown in FIG.

  The integrated circuit 61 includes a drive control unit 70. An operation signal gup is input to the drive controller 70 via the sixth terminal T6 of the integrated circuit 61, and the voltage detected by the second voltage sensor 42 via the seventh terminal T7 (hereinafter referred to as the power supply voltage VH). ) Is entered. The drive control unit 70 drives the switching element Sup by alternately performing the charging process and the discharging process based on the input operation signal gup.

  When it is determined that the operation signal gup is turned on, the charging process outputs the enable signal SigC to the first operational amplifier 64 to drive the charging switching element 63 and the enable signal SigD to the second operational amplifier 68. This is a process for turning off the discharge switching element 66 by stopping the output. In the charging process, the output voltage of the first power supply 65 is adjusted by the energization operation in order to control the gate charging current to the command charging current. The output voltage of the first power supply 65 corresponding to the command charging current is stored in a memory 70 a that is a storage unit included in the drive control unit 70. When the gate voltage of the switching element Sup becomes equal to or higher than the threshold voltage Vth (threshold voltage) due to the execution of the charging process, the switching element Sup is switched from the off state to the on state. Incidentally, in the present embodiment, the charging resistor 62, the charging switching element 63, the first operational amplifier 64, the first power supply 65, and the drive control unit 70 constitute “charging control means”.

  On the other hand, in the discharge process, when it is determined that the operation signal gup is an off command, the enable signal SigD is output to the second operational amplifier 68 to drive the discharge switching element 66 and enable the first operational amplifier 64. This is a process for turning off the charging switching element 63 by stopping the output of the signal SigC. In the discharge process, the output voltage of the second power source 69 is adjusted by an energization operation so as to control the gate discharge current to the command discharge current. The output voltage of the second power supply 69 corresponding to the command discharge current is stored in the memory 70a. When the gate voltage becomes lower than the threshold voltage Vth by executing the discharge process, the switching element Sup is switched from the on state to the off state. Incidentally, in the present embodiment, the discharge switching element 66, the discharge resistor 67, the second operational amplifier 68, the second power source 69, and the drive control unit 70 constitute “discharge control means”.

<2. Explanation of command discharge current of gate>
Next, the command discharge current of the gate, which is a characteristic configuration of this embodiment, will be described. Here, after describing a method for adapting the command discharge current, a process for setting the command discharge current executed by the drive control unit 70 will be described. In the present embodiment, the switching element S * # (* = u, v, w, # = p, n) constituting the inverter 30 will be mainly described as an example.

  First, a method for adapting a command discharge current according to the present embodiment will be described.

  FIG. 3 shows the relationship between the gate discharge current Ig, the current (hereinafter referred to as the collector current Ic) flowing between the collector (input terminal) and the collector of the switching element S * #, and the surge voltage ΔV. In this embodiment, as shown in FIG. 4, the surge voltage ΔV includes the peak of the collector-emitter voltage Vce when the switching element S * # is switched to the off state, and the switching element S * # is switched to the off state. It is defined as the difference from the stable value of the collector-emitter voltage Vce after being generated (illustrated by the power supply voltage VH in the figure). FIG. 3 shows the relationship when the collector current Ic has the maximum value (hereinafter, maximum collector current Imax, for example, 400 A) and the collector current has the minimum value (hereinafter, minimum collector current Imin, for example, 50 A). And showed the relationship. The horizontal axis of FIG. 3 also shows that the switching speed (switching speed) from the on state to the off state of the switching element S * # decreases as the gate discharge current Ig decreases.

  As shown in FIG. 3, the surge voltage ΔV increases as the gate discharge current Ig is increased. However, when the gate discharge current Ig is further increased, the surge voltage ΔV starts to decrease. That is, there is a gate discharge current Ig having a peak surge voltage ΔV.

  The reason is different between, for example, a region where the collector current Ic is large and a region where the collector current Ic is small. Specifically, in a region where the collector current Ic is large, when the gate discharge current Ig is increased, the surge voltage when the switching element S * # is switched to the OFF state is absorbed by the dynamic avalanche of the switching element S * #. For this reason, there is a gate discharge current Ig at which the surge voltage ΔV peaks. However, setting the gate discharge current Ig to exceed the gate discharge current corresponding to the peak of the surge voltage does not maintain the reliability of the switching element S * #. This is because if the gate discharge current Ig is increased beyond the gate discharge current at which the surge voltage ΔV reaches a peak, the reliability of the switching element S * # is lowered by the dynamic avalanche.

  On the other hand, in the region where the collector current Ic is small, the gate discharge current cannot be controlled because the switching speed is determined by the element characteristics of the IGBT. Due to this, there is a gate discharge current Ig having a peak surge voltage ΔV.

  For the reasons described above, when the gate discharge current Ig is increased beyond the gate discharge current Ig at which the surge voltage ΔV peaks, there is a concern that the reliability of the switching element S * # is lowered. Further, the gate discharge current Ig at which the surge voltage ΔV reaches a peak decreases as the collector current Ic increases. Therefore, when switching the switching element S * # to the off state, the gate discharge current Ig corresponding to each collector current Ic needs to be equal to or less than the gate discharge current Ig at which the surge voltage ΔV peaks.

  Here, in this embodiment, from the viewpoint of reducing the switching loss, the gate discharge current Ig at which the surge voltage ΔV reaches the peak is selected as the off-rate limiting current Idrc (corresponding to the “upper limit discharge current”) for each collector current Ic. To do. FIG. 5 shows the off-rate limiting current Idrc corresponding to the case where the collector current Ic has various values between the minimum collector current Imin and the maximum collector current Imax. As shown in FIG. 5, as the collector current Ic immediately before the OFF command of the operation signal g * # is input to the drive circuit Dr increases, the OFF rate-limiting current Idrc decreases. In FIG. 5, the off-rate limiting current Idrc corresponding to the minimum collector current Imin is shown as the off-maximum current Iβ, and the off-rate limiting current Idrc corresponding to the maximum collector current Imax is shown as the off-minimum current Iα.

  Thus, the off-rate limiting current Idrc can be defined in relation to the collector current Ic. In the present embodiment, the timing for determining the off-rate limiting current Idrc is set to the timing at which the surge voltage ΔV peaks. In the present embodiment, this timing is referred to as an off-rate limiting point. Here, the larger the collector current Ic immediately before the OFF command is input, the shorter the time from when the OFF command is input until the OFF rate-limiting point is reached. FIG. 6 shows a time chart from when the OFF command is input to the drive control unit 70 to when the collector-emitter voltage Vce reaches a peak. Here, FIG. 6 shows changes in the collector current Ic, the collector-emitter voltage Vce, and the gate voltage Vge. As shown in FIG. 6, the time from when the OFF command is input to when the OFF rate-limiting point (time t1) corresponding to the maximum collector current Imax is reached corresponds to the minimum collector current Imin after the OFF command is input. It is shorter than the time until the OFF rate limiting point (time t2) is reached.

  Here, when the off-rate limiting points corresponding to various collector currents Ic and the off-rate limiting currents Idrc corresponding to the respective off-rate limiting points are plotted on the time axis, as shown at times t2 to t3 in FIG. The waveform of the off-rate limiting current Idrc is a waveform that monotonously increases with time. Even if the OFF rate-limiting current Idrc at each OFF rate-limiting point continues to flow over the period from the input of the OFF command at time t1 to the OFF rate-limiting point corresponding to the collector current Ic, the reliability of the switching element S * # Sex does not decrease. For this reason, after the OFF command is input, the gate discharge current at each OFF rate-determining point corresponding to various collector currents Ic is set to be equal to or less than each OFF-determining current Idrc corresponding to various collector currents Ic. Switching loss can be reduced while avoiding a decrease in the reliability of the switching element S * # when switching to.

  Here, in the present embodiment, the period from time t2 to t3 is referred to as a main discharge period. In addition, the start timing (time t2) of the main discharge period is set to an off rate-limiting point corresponding to the maximum collector current Imax (see FIG. 7B). Further, the end timing (time t3) of the main discharge period is set to an off rate-limiting point corresponding to the minimum collector current Imin. In the present embodiment, each of the start timing and end timing of the main discharge period is determined in advance by experiments or the like.

  On the other hand, a period from time t1 when the OFF command is input to the start timing (time t2) of the main discharge period is referred to as a pre-discharge period. In addition, a period from the end timing of the main discharge period (time t3) until the ON command is input immediately thereafter is referred to as an after discharge period.

  In the present embodiment, the command discharge current in the pre-discharge period is set to a constant value that is smaller than the OFF minimum current Iα. The command discharge current in the main discharge period is set to monotonously increase with time while maintaining continuity with the command discharge current at the end timing of the pre-discharge period. Specifically, the command discharge current at time t2 is set to a value less than the minimum OFF current Iα, and the command discharge current at time t3 is set to a value greater than the minimum OFF current Iα and less than the maximum OFF current Iβ. Yes. The command discharge current in the after discharge period is the same value as the command discharge current at the end timing of the main discharge period, and is set to a constant value.

  Furthermore, in this embodiment, the command discharge current in the main discharge period is set to a value that does not depend on the collector current Ic. This setting is possible because the command discharge current at each timing of the main discharge period is set based on the off-rate limiting current Idrc at each off-rate limiting point corresponding to various collector currents Ic. Thereby, the process which changes the setting of command discharge current according to collector current Ic can be made unnecessary. For this reason, it is not necessary to perform the setting change process of the command discharge current within one cycle of the carrier signal in the PWM process, and an increase in the arithmetic processing capability required for the drive circuit Dr can be suppressed. Further, a detection circuit for detecting the collector current Ic can be eliminated, and an increase in the number of components of the drive circuit Dr can be suppressed.

  In the present embodiment, information relating to the command discharge current shown in FIG. 7A is stored in the memory 70 a of the drive control unit 70. Specifically, the output voltage of the second power source 69 for realizing the command discharge current is stored in the memory 70a in relation to the elapsed time after the OFF command is input. The drive control unit 70 has a function of measuring the time from when the off command is input. Therefore, the drive control unit 70 can control the gate discharge current to the command discharge current shown in FIG. Incidentally, in the present embodiment, the drive control unit 70 corresponds to “discharge command value setting means”.

  Subsequently, the effects of the present embodiment will be described with reference to FIGS. 8 and 9. First, FIG. 8 shows the transition of the gate discharge current in this embodiment, constant voltage control, and constant current control. Here, the constant voltage control is control in which the discharge switching element 66 is fully turned on over the period in which the off command is input in the configuration shown in FIG. By fully turning on, the on-resistance of the discharge switching element 66 is substantially zero. On the other hand, the constant current control means that the output voltage of the second power source 69 is kept constant and the gate discharge current is kept constant over the period when the off command is inputted in the configuration shown in FIG. It is control.

  As shown in the figure, in the constant voltage control, the smaller the collector current Ic, the lower the mirror voltage of the switching element S * # and the smaller the gate discharge current. For this reason, switching speed falls and switching loss increases. Thus, in the constant voltage control, the switching speed depends on the collector current Ic.

  Here, in the constant voltage control and the constant current control, the gate discharge current is usually adapted so that the reliability of the switching element S * # is not lowered when the collector current Ic becomes the maximum collector current Imax. However, in this case, as the collector current Ic becomes smaller than the maximum collector current Imax, the gate discharge current cannot be increased although there is room for increasing the gate discharge current. For this reason, in the constant voltage control and the constant current control, the switching loss tends to increase in a region where the collector current Ic is low.

  On the other hand, according to the command discharge current setting method of the present embodiment, as shown in FIG. 9, the command discharge current corresponding to the minimum collector current Imin can be set larger than the constant voltage control or the constant current control. That is, the switching speed can be set high. As a result, compared to the constant voltage control and the constant current control, for example, switching loss can be reduced in a region where the collector current Ic is low.

  Incidentally, the above-described command discharge current setting method can be used for each step-up switching element Scp, Scp constituting the buck-boost converter 20 as well as the switching element S * # constituting the inverter 30.

<3. Explanation of command charge current of gate>
Next, the command charge current of the gate, which is a characteristic configuration of the present embodiment, will be described. Here, after describing the method of adapting the command charging current, the command charging current setting process executed by the drive control unit 70 will be described.

  First, a method for adapting a command charging current according to the present embodiment will be described.

  FIG. 10 shows the relationship between the gate charging current Ig, the collector current Ic, and the collector current speed “dIc / dt”. In the present embodiment, as shown in FIG. 11, the collector current speed is a change speed after the peak of the collector current Ic (specifically, among the collector current Ic when the switching element S * # is switched to the ON state) , The rate of change at times t2 to t3). Here, Iak and Vak indicate the current flowing through the free wheel diode of the opposite arm and the voltage between terminals. FIG. 10 shows the relationship when the collector current Ic is the maximum collector current Imax and the relationship when the collector current is the minimum collector current Imin. In addition, at time t1, due to the inductance of the coil of the motor generator 40, it has been shown that the collector-emitter voltage Vce on its own arm side decreases.

  The larger the collector current Ic is, the smaller the upper limit value of the collector current speed at which the reliability of the free wheel diode of the opposite arm can be avoided. The collector current speed of the own arm contributes to the reliability of the freewheel diode of the opposite arm. The higher the collector current speed, the more reliable the freewheel diode due to the dynamic avalanche during reverse recovery of the freewheel diode. It is because it becomes easy to fall. FIG. 10 shows the upper limit value Sth1 of the collector current speed corresponding to the minimum collector current Imin and the upper limit value Sth2 of the collector current speed corresponding to the maximum collector current Imax. As the gate discharge current Ig is increased, the collector current speed is increased. For this reason, when switching element S * # is switched on, gate charge current Ig corresponding to each collector current Ic needs to have a collector current speed equal to or lower than its upper limit.

  Here, in the present embodiment, from the viewpoint of reducing the switching loss, the gate charging current Ig whose collector current speed is the upper limit value is selected as the on-rate limiting current Icrc for each collector current Ic. FIG. 12 shows the on-rate limiting current Icrc corresponding to the case where the collector current Ic has various values between the minimum collector current Imin and the maximum collector current Imax. As shown in FIG. 12, as the collector current Ic increases, the on-rate limiting current Icrc decreases. In FIG. 12, the on-rate limiting current Icrc corresponding to the minimum collector current Imin is shown as the on-maximum current Iδ, and the on-rate limiting current Icrc corresponding to the maximum collector current Imax is shown as the on-minimum current Iγ.

  Thus, the on-rate limiting current Icrc can be defined in relation to the collector current Ic. In the present embodiment, the timing for determining the on-rate limiting current Icrc is set to the timing at which the collector current Ic of the own arm peaks. In the present embodiment, this timing is referred to as an on-rate limiting point. Here, the longer the collector current Ic that flows after switching to the ON state, the longer the time from when the ON command is input until the ON rate-limiting point is reached. FIG. 13 shows a time chart from when the ON command is input to the drive control unit 70 until the collector current Ic reaches a peak. Here, FIG. 13 shows transitions of the collector current Ic, the collector-emitter voltage Vce, the gate voltage Vge, and the loss (Ic × Vce). As shown in FIG. 13, the time from when the ON command is input until the ON rate-limiting point (time t2) corresponding to the maximum collector current Imax corresponds to the minimum collector current Imin after the ON command is input. Longer than the time until the ON rate-limiting point (time t1) is reached.

  Here, when the on-rate limiting points corresponding to various collector currents Ic and the on-rate limiting currents Icrc corresponding to the respective on-rate limiting points are plotted on the time axis, as shown at times t2 to t3 in FIG. The waveform of the on-rate limiting current Icrc becomes a waveform that monotonously decreases with time. Even if the on-rate limiting current Icrc at each on-rate limiting point continues to flow over the period from when the on-command is input at time t1 to the on-rate limiting point corresponding to the collector current Ic, Reliability is not reduced. For this reason, after the ON command is input, the gate charging current at each ON rate-determining point corresponding to various collector currents Ic is set to be equal to or less than each ON-determining current Icrc corresponding to various collector currents Ic. Switching loss can be reduced while avoiding a decrease in the reliability of the free wheel diode of the opposing arm when switching to.

  Here, in the present embodiment, the period from time t2 to t3 is referred to as a main charging period. Further, the start timing (time t2) of the main charging period is set to the ON rate-limiting point corresponding to the minimum collector current Imin (see FIG. 14B). Furthermore, the end timing (time t3) of the main charging period is set to the ON rate-limiting point corresponding to the maximum collector current Imax. In the present embodiment, each of the start timing and end timing of the main charging period is determined in advance through experiments or the like.

  On the other hand, the period from the time t1 when the ON command is input to the start timing (time t2) of the main charging period is referred to as a pre-charging period. Further, a period from the end timing of the main charging period (time t3) to the input of the off command immediately after that will be referred to as an after charging period.

  In the present embodiment, the command charging current in the pre-charging period is set to a constant value that is smaller than the on-maximum current Iδ and larger than the on-minimum current Iγ. The command charging current in the main charging period is set to monotonously decrease with time while maintaining continuity with the command charging current at the end timing of the precharging period. Specifically, the command charging current at time t2 is set to a value that is greater than the on-minimum current Iγ and less than the on-maximum current Iδ, and the command charging current at the time t3 is set to a value that is less than the on-minimum current Iγ. Yes. The command charging current in the after charging period is the same value as the command charging current at the end timing of the main charging period, and is set to a constant value.

  Further, in the present embodiment, the command charging current in the main charging period is set to a value that does not depend on the collector current Ic, like the command discharge current. Thereby, similarly to the discharge side, it is possible to suppress an increase in the arithmetic processing capability required for the drive circuit Dr, and it is possible to suppress an increase in the number of components of the drive circuit Dr.

  In the present embodiment, information relating to the command charging current shown in FIG. 14A is stored in the memory 70 a of the drive control unit 70. Specifically, the output voltage of the first power supply 65 for realizing the command charging current is stored in the memory 70a in relation to the elapsed time after the ON command is input. In the charging process, the drive control unit 70 can control the gate charging current to the command charging current shown in FIG. Incidentally, in the present embodiment, the drive control unit 70 corresponds to “charging command value setting means”.

  Then, the effect of this embodiment is demonstrated using FIG. FIG. 15 shows the transition of the gate charging current in the present embodiment, constant voltage control, and constant current control. Here, the constant voltage control is control in which the charging switching element 63 is fully turned on over the period in which the ON command is input in the configuration shown in FIG. On the other hand, the constant current control means that the output voltage of the first power supply 65 is kept constant and the gate charging current is kept constant over the period when the ON command is inputted in the configuration shown in FIG. It is control.

  As shown in the figure, in constant voltage control, the larger the collector current Ic, the higher the mirror voltage of the switching element S * # and the smaller the gate charging current. For this reason, switching speed falls and switching loss increases. Thus, in the constant voltage control, the switching speed depends on the collector current Ic.

  Here, in the constant voltage control and the constant current control, the gate charging current is usually adapted so that the reliability of the freewheeling diode is not lowered when the collector current Ic becomes the maximum collector current Imax. However, in this case, similarly to the discharge side, the switching loss increases as the collector current Ic becomes smaller than the maximum collector current Imax. On the other hand, according to the setting method of the command charging current of the present embodiment, the command charging current corresponding to the minimum collector current Imin can be set larger than the constant voltage control or the constant current control. As a result, for example, switching loss can be reduced in a region where the collector current Ic is low.

  Incidentally, the above-described command charging current setting method can be used for each step-up switching element Scp, Scp constituting the buck-boost converter 20 as well as the switching element S * # constituting the inverter 30.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) In the main discharge period, the command discharge current of the gate is set monotonously. And switching element S * # was switched to the OFF state by controlling the gate discharge current to the set command discharge current. Thereby, at the time of switching to an OFF state, switching loss can be reduced, avoiding the fall of the reliability of switching element S * #.

  Further, the command discharge current in the main discharge period is set to a value that does not depend on the collector current Ic immediately before the OFF command is input. As a result, the process of changing the setting of the command discharge current in accordance with the collector current Ic can be made unnecessary, so that it is possible to suppress an increase in arithmetic processing capability required for the drive circuit Dr. In addition, since it is not necessary for the drive circuit Dr to include a detection circuit that detects the collector flow, an increase in the number of components of the drive circuit Dr can be suppressed.

  (2) The start timing of the main discharge period is set to the off rate limiting point corresponding to the maximum collector current Imax. According to this setting, even when the maximum collector current Imax flows through the switching element, it is possible to accurately avoid a decrease in the reliability of the switching element S * # when switching to the off state.

  (3) The end timing of the main discharge period is set to an off rate limiting point corresponding to the minimum collector current Imin. In contrast to this setting, a configuration is also conceivable in which the end timing of the main discharge period is set to an off-rate limiting point corresponding to a collector current larger than the minimum collector current Imin. In this case, although there is room for increasing the command discharge current after the end timing of the main discharge period, the command discharge current is not increased, so that the switching loss may increase. On the other hand, according to the present embodiment, the command discharge current can be set large, and the switching loss can be accurately reduced.

  (4) In the main charging period, the command charging current of the gate was set to monotonously decrease. And switching element S * # was switched to the ON state by controlling the gate charging current to the set command charging current. Thereby, at the time of switching to an ON state, switching loss can be reduced, avoiding the fall of the reliability of the freewheel diode of an opposing arm.

  Furthermore, the command charging current in the main charging period was set to a value that does not depend on the collector current. Thereby, it is possible to suppress an increase in the arithmetic processing capability required for the drive circuit Dr, and it is also possible to suppress an increase in the number of components of the drive circuit Dr.

  (5) The end timing of the main charging period is set to the on-rate limiting point corresponding to the maximum collector current Imax. According to this setting, even when the maximum collector current Imax flows through the switching element, it is possible to accurately avoid a decrease in the reliability of the free wheel diode of the opposing arm at the time of switching to the ON state.

  (6) The start timing of the main charging period is set to the on-rate limiting point corresponding to the minimum collector current Imin. In contrast to this setting, a configuration in which the start timing of the main charging period is set to an on-rate limiting point corresponding to a collector current larger than the minimum collector current Imin is also conceivable. In this case, although there is room for increasing the command charging current before the start timing of the main charging period, the switching loss may increase because the command charging current is not increased. On the other hand, according to the present embodiment, the command charging current can be set large, and the switching loss can be accurately reduced.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In the present embodiment, the setting method of the command discharge current and the command charge current is changed.

  First, the command discharge current will be described. In this embodiment, as shown in FIG. 16, the command discharge current in the pre-discharge period (time t1 to t2) is set to be larger than the command discharge current at the start timing (time t2) of the main discharge period. Here, FIG. 16 corresponds to the previous FIG. In FIG. 16, the command discharge current concerning the said 1st Embodiment was shown with the broken line.

  According to the command discharge current setting method according to the present embodiment, the dead time can be shortened. Hereinafter, this will be described with reference to FIG.

  FIGS. 17A and 17B show changes in the upper and lower arm operation signals g * p and g * n, and FIG. 17B shows changes in the gate voltage Vge of the lower arm switching element S * n. FIG. 17C shows the transition of the collector current Ic of the lower arm switching element S * n, and FIG. 17D shows the transition of the collector-emitter voltage Vce of the lower arm switching element S * n. In FIG. 17, each transition of this embodiment and 1st Embodiment was shown on the basis of the time t3 when the operation signal g * p of an upper arm is switched to an ON command.

  In the method of setting the command discharge current according to the first embodiment, the gate voltage Vge starts to decrease when the off command is input at time t1a. Thereafter, when the gate voltage Vge falls below the threshold voltage Vth at time t2, the switching element S * n is switched to the off state.

  On the other hand, in the present embodiment, the time interval between the time t1b that is the input timing of the off command and the time t2 that is the timing when the gate voltage Vge decreases and falls below the threshold voltage Vth is greater than the time interval of the first embodiment. short. Therefore, the time interval TB between the input timing of the off command and the timing at which the upper arm operation signal g * p is switched to the on command can be made shorter than the time interval TA of the first embodiment. As a result, the dead time can be shortened and the controllability of the motor generator 40 can be improved.

  Next, the command charging current will be described. In this embodiment, as shown in FIG. 18, the command charging current in the pre-charging period (time t1 to t2) is set to be larger than the command charging current at the start timing (time t2) of the main charging period. FIG. 18 corresponds to the previous FIG. In FIG. 18, the command charging current according to the first embodiment is shown by a broken line.

  According to the setting method of the command charging current according to the present embodiment, the dead time can be shortened similarly to the discharge side. Hereinafter, this will be described with reference to FIG. FIG. 19 corresponds to FIG. In FIG. 19, each transition of this embodiment and 1st Embodiment was shown on the basis of the time t2 when the gate voltage Vge rises and becomes the threshold voltage Vth.

  The time interval TD between the input timing of the ON command and the time t2 according to the present embodiment is shorter than the time interval TD of the first embodiment. For this reason, dead time can be shortened and the controllability of the motor generator 40 can be improved.

  Incidentally, the above-described command charging current setting method can be used for each step-up switching element Scp, Scp constituting the buck-boost converter 20 as well as the switching element S * # constituting the inverter 30.

  Thus, according to the present embodiment, in addition to the effect of the first embodiment, an effect that the dead time can be shortened can be further obtained.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the second embodiment. In the present embodiment, the setting method of the command discharge current and the command charge current is changed.

  First, the command discharge current will be described. In the present embodiment, as shown in FIG. 20, the command discharge current in the after discharge period after time t3 is set larger than the command discharge current at the end timing of the main discharge period (time t3). FIG. 20 corresponds to FIG. In FIG. 20, the command discharge current concerning the said 1st Embodiment was shown with the broken line.

  According to the command discharge current setting method according to the present embodiment, switching loss can be reduced. Hereinafter, this will be described with reference to FIG. FIGS. 21A to 21C correspond to FIGS. 17C to 17E.

  As shown in the figure, according to the command discharge current setting method according to the present embodiment, the tail current at the times t1 to t2 can be reduced as compared with the first embodiment. As a result, switching loss that occurs when switching to the off state can be reduced.

  Next, the command charging current will be described. In the present embodiment, as shown in FIG. 22, the command charging current in the after charging period after time t3 is set to be larger than the command charging current at the end timing of the main charging period (time t3). FIG. 22 corresponds to FIG. In FIG. 22, the command charging current according to the first embodiment is shown by a broken line.

  According to the setting method of the command charging current according to the present embodiment, the switching loss can be reduced similarly to the discharge side. Hereinafter, this will be described with reference to FIG. FIGS. 23A to 23C correspond to FIGS. 19C to 19E.

  As shown in the figure, according to the command discharge current setting method according to the present embodiment, the collector-emitter voltage Vce between the times t2 and t3 after the time t1 when the gate voltage Vge becomes the threshold voltage Vth is set. This can be reduced as compared with the first embodiment. As a result, switching loss that occurs when switching to the ON state can be reduced.

  Incidentally, the above-described command charging current setting method can be used for each step-up switching element Scp, Scp constituting the buck-boost converter 20 as well as the switching element S * # constituting the inverter 30.

  Thus, according to the present embodiment, in addition to the effect of the first embodiment, an effect that the switching loss can be further reduced can be further obtained.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In the present embodiment, the command discharge current and the command charge current are variably set based on the power supply voltage VH.

  First, a method for setting the command discharge current will be described. In the present embodiment, the first off-side process for setting the command discharge current at the start timing of the main discharge period to be smaller is performed as the power supply voltage VH is higher. Further, as the power supply voltage VH is higher, a second off-side process is performed in which the end timing of the main discharge period is delayed with respect to the input timing of the off command. This is because, as shown in FIG. 24, the off-rate limiting current Idrc is adapted to be smaller as the power supply voltage VH is higher. Here, FIG. 24 shows the relationship among the power supply voltage VH, the collector current Ic, and the off-rate limiting current Idrc. Vmax indicates a maximum value (for example, 600 V) that the power supply voltage VH can take.

  In the present embodiment, the higher the power supply voltage VH, the smaller the off-rate limiting current Idrc is adapted. The change rate “dV / dt of the collector-emitter voltage Vce when the switching element S * # is switched to the off state. This is to suppress the "" below a predetermined speed.

  That is, the surge voltage output from the inverter 30 can be input to the motor generator 40, and the input surge voltage can be amplified in the motor generator 40. As a result, the reliability of the motor generator 40 may be reduced. The amplification phenomenon occurs because, for example, resonance occurs due to the inductance of the coil of the motor generator 40 and the parasitic capacitance of the coil. Here, the higher the power supply voltage VH, the higher the change rate of the collector-emitter voltage Vce when switching to the off state. The higher the rate of change, the higher the frequency included in the surge voltage. In the present embodiment, amplification of the surge voltage in the motor generator 40 is avoided by shifting the frequency included in the surge voltage to a lower frequency side than the resonance frequency of the motor generator 40.

  For this reason, when the power supply voltage VH is high, a process for reducing the switching speed is performed by reducing the off-rate limiting current Idrc (that is, the command discharge current). A specific example of this process is the first and second off-side processes. As a result, the rate of change “dV / dt” of the collector-emitter voltage Vce is suppressed to a predetermined voltage or less.

  FIG. 25 shows an example of a command discharge current setting method according to the power supply voltage VH. The power supply voltage Vd1 in FIG. 25 (a) is lower than the power supply voltage Vd2 in FIG. 25 (b). As shown in the figure, the command discharge current at the start timing (time t2) of the main discharge period is set smaller as the power supply voltage VH is higher. The time from the start timing to the end timing of the main discharge period with the higher power supply voltage (time t2 to t4) is set longer than the time with the lower power supply voltage (time t2 to t4). In the present embodiment, the start timing (time t2) of the main discharge period is fixed regardless of the power supply voltage VH. The command discharge current in the main discharge period is set to be equal to or less than the off-rate limiting current Idrc corresponding to the power supply voltage VH.

  Here, in the present embodiment, as shown in FIG. 24, when the drive control unit 70 determines that the power supply voltage VH is equal to or lower than the off-side specified voltage Vα, instead of the first and second off-side processes. The discharge switching element 66 is fully turned on over the period in which the OFF command is input. This is based on the fact that the gate discharge current cannot be made higher than a certain value Ilimit1 because the output voltage of the constant voltage power supply 60 has an upper limit. According to the full-on process, the discharge process is performed by constant voltage control.

  Next, a method for setting the command charging current will be described. In the present embodiment, as the power supply voltage VH is higher, the first on-side process for setting the command charging current at the end timing of the main charging period to be smaller is performed. Further, the second on-side process is performed to advance the start timing of the main charging period with respect to the input timing of the on command as the power supply voltage VH is higher. This is because, as shown in FIG. 26, the ON rate-limiting current Icrc is adapted to be smaller as the power supply voltage VH is higher. FIG. 26 shows a relationship among the power supply voltage VH, the collector current Ic, and the on-rate limiting current Icrc. In the present embodiment, the higher the power supply voltage VH, the smaller the on-rate limiting current Icrc is adapted for the same reason as on the discharge side.

  FIG. 27 shows an example of a method for setting the command charging current according to the power supply voltage VH. The power supply voltage Vc1 in FIG. 27 (a) is lower than the power supply voltage Vc2 in FIG. 27 (b). As shown in the drawing, the command charging current at the end timing (time t4) of the main charging period is set smaller as the power supply voltage VH is higher. The time from the start timing to the end timing of the main charging period with the higher power supply voltage (time t2 to t4) is set longer than the time with the lower power supply voltage VH (time t3 to t4). In the present embodiment, the end timing (time t4) of the main charging period is fixed regardless of the power supply voltage VH. The command charging current in the main charging period is set to be equal to or lower than the on-rate limiting current Icrc corresponding to the power supply voltage VH.

  Here, in the present embodiment, as shown in FIG. 26, when the drive control unit 70 determines that the power supply voltage VH is equal to or lower than the on-side specified voltage Vβ, instead of the first and second on-side processes. The charging switching element 63 is fully turned on over the period when the ON command is input. This is based on the fact that the gate charging current cannot be made higher than a certain value Ilimit2 as in the discharge side. With this process, the charging process is performed by constant voltage control.

  Incidentally, the above-described command charging current setting method can be used for each step-up switching element Scp, Scp constituting the buck-boost converter 20 as well as the switching element S * # constituting the inverter 30. Here, when the above setting method is used for the lower arm boost switching element Scn, for example, a voltage detected by the first voltage sensor 41 may be used instead of the power supply voltage VH. Further, when the above setting method is used for the upper arm boost switching element Scp, for example, a differential pressure between the voltage detected by the first voltage sensor 41 and the power supply voltage VH may be used instead of the power supply voltage VH.

  According to the present embodiment described above, since the command charge / discharge current is set according to the power supply voltage VH, it is possible to avoid a decrease in the reliability of the control system including the motor generator 40.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  The command charge / discharge current setting method based on the power supply voltage VH is not limited to the one exemplified in the fourth embodiment. For example, as shown in FIG. 28, the command discharge current may be set smaller as the power supply voltage VH is higher without changing the start timing and end timing of the main discharge period. Further, as shown in FIG. 29, the command charging current may be set smaller as the power supply voltage VH is higher without changing the start timing and end timing of the main charging period.

  In the fourth embodiment, only one of the first off-side process and the second off-side process may be performed. Further, only one of the first on-side process and the second on-side process may be performed.

  In each of the above embodiments, the command discharge current is set to a value less than the off-rate limiting current Idrc. However, the present invention is not limited to this, and the command discharge current may be set to the same value as the off-rate control current Idrc. The command charging current may be set to the same value as the on-rate limiting current Icrc.

  The start timing of the main discharge period may be set to an off rate limiting point corresponding to a collector current Ic that is less than the maximum collector current Imax and greater than the minimum collector current Imin. Even in this case, the effects (1) and (3) to (6) of the first embodiment can be obtained. Further, the end timing of the main discharge period may be set to an off rate-limiting point corresponding to a collector current Ic that is less than the maximum collector current Imax and greater than the minimum collector current Imin. Even in this case, the effects (1), (2), (4) to (6) of the first embodiment can be obtained.

  The start timing of the main charging period may be set to an on-rate limiting point corresponding to a collector current Ic that is less than the maximum collector current Imax and greater than the minimum collector current Imin. Even in this case, the effects (1) to (5) of the first embodiment can be obtained. Alternatively, the end timing of the main charging period may be set to an on-rate limiting point corresponding to a collector current Ic that is less than the maximum collector current Imax and greater than the minimum collector current Imin. Even in this case, the effects (1) to (4) and (6) of the first embodiment can be obtained.

  The command charging / discharging current setting method described in the second and third embodiments may be used together.

  The command current may be monotonously changed and set in either one of the discharge process and the charge process.

  The switching element is not limited to an IGBT, and may be another voltage control type switching element such as a MOSFET.

  The method of determining the rate-limiting point and the rate-limiting current in the first embodiment is merely an example. Specifically, for example, as shown in FIG. 13, it may be possible to determine the timing at which the loss W peaks when switched to the on state, as shown in FIG.

  62 ... charging resistor, 63 ... charging switching element, 64 ... first operational amplifier, 66 ... discharging switching element, 67 ... discharging resistor, 68 ... second operational amplifier, 70 ... drive control unit, Dr ... driving circuit , Scp, Scn, Sup to Swn... Switching elements.

Claims (15)

Switching element drive circuit that switches the operation state of the switching element by moving the charge of the switching control terminal of the switching element when a switching command of the operation state of the switching element (Scp, Scn, Sup to Swn) is input In
By inputting the switching command, a period in the middle from the start of movement of the charge of the opening / closing control terminal to switch the operation state until completion of the movement of the charge is defined as a specified period.
Command value setting means that is a command current of the switching control terminal in the specified period that does not depend on a current flowing between the input and output terminals of the switching element, and that is set by monotonically changing the command current over time in the specified period (70),
Current control means (62 to 65, 66 to 69, 70) for controlling the current of the switching control terminal to the command current set by the command value setting means to switch the operation state of the switching element. A switching element driving circuit. The specified period is a main discharge that is an intermediate period from when the charge of the open / close control terminal starts to be discharged until the discharge of the charge is completed by inputting an OFF command for switching the operation state to the OFF state. Period,
The command value setting means includes a discharge command value setting means for monotonously increasing the command discharge current of the switching control terminal over time in the main discharge period,
The current control means is a discharge control means (66 to 69, 70) for controlling the discharge current of the switching control terminal to the command discharge current set by the discharge command value setting means in order to switch the switching element to an off state. The switching element drive circuit according to claim 1, including: The discharge current of the switching control terminal required to switch the switching element from the on state to the off state, and the upper limit discharge current of the switching control terminal capable of avoiding the deterioration of the reliability of the switching element is the off rate limiting current age,
The timing for determining the off-rate-limiting current, which is an intermediate timing from the input of the off-command to the completion of the discharge of the charge of the switching control terminal, is the off-rate-limiting point,
The discharge command value setting means includes the command discharge current at the off-rate control point corresponding to each current flowing between the input / output terminals in the main discharge period, and the command discharge current corresponding to each current flowing between the input / output terminals. The switching element drive circuit according to claim 2, wherein the switching element drive circuit is set to be equal to or less than an off-rate limiting current.   4. The switching element drive circuit according to claim 3, wherein a start timing of the main discharge period is set to the off-rate limiting point corresponding to a maximum value of a range that can be taken by a current flowing between the input and output terminals. 5.   5. The switching element according to claim 3, wherein an end timing of the main discharge period is set to the off-rate-limiting point corresponding to a minimum value larger than 0 in a range that a current flowing between the input and output terminals can take. Drive circuit. The discharge command value setting means includes
A process for setting the command discharge current in the pre-discharge period, which is a period from the input of the off command to the start timing of the main discharge period, larger than the command discharge current at the start timing of the main discharge period;
The command discharge current in the after discharge period including the period from the end timing of the main discharge period until the voltage at the switching control terminal decreases to reach the lower limit voltage is used as the command discharge at the end timing of the main discharge period. The switching element drive circuit according to claim 2, wherein at least one of the processes set to be larger than the current is performed. The discharge command value setting means includes
When the voltage between the input and output terminals is high, a first off-side process for setting the command discharge current at the start timing of the main discharge period smaller than when the voltage between the input and output terminals is low;
When the voltage between the input and output terminals is high, the second off-side process for delaying the end timing of the main discharge period with respect to the input timing of the off command is lower than when the voltage between the input and output terminals is low. The switching element drive circuit according to claim 2, wherein at least one of the processes is further performed. The discharge control means is a series connection body connected between the output terminal of the switching element and the open / close control terminal, wherein the discharge resistor (67) and the discharge switching element (66) are in series. By having a connection body and adjusting the on-resistance of the discharge switching element, the discharge current of the switching control terminal is controlled to the command discharge current,
The discharge command value setting means performs the first off-side processing and the second off-side processing when the voltage between the input and output terminals is higher than the off-side specified voltage, and the voltage between the input and output terminals is The switching element drive circuit according to claim 7, wherein when the voltage is equal to or lower than the off-side specified voltage, a process for fully turning on the discharge switching element is performed instead of the first off-side process and the second off-side process. The specified period is a main charge period in which the charge is charged to the open / close control terminal after the on command to switch the operation state to the on state is input and the charge charge is completed. Period,
The command value setting means includes charge command value setting means for monotonously decreasing and setting the command charging current of the switching control terminal over time in the main charging period,
The current control means is a charge control means (62 to 65, 70) for controlling the charge current of the open / close control terminal to the command charge current set by the charge command value setting means to switch the switching element to an on state. The switching element drive circuit according to claim 1, further comprising: The switching elements are an upper arm switching element (Sup, Svp, Swp) and a lower arm switching element (Sun, Svn, Swn) connected in series to each other,
The upper arm switching element and the lower arm switching element are alternately turned on,
Of the upper arm switching element and the lower arm switching element, the switching element on the side that is going to be turned on is the self-arm switching element, the other is the opposing arm switching element,
The charging current of the switching control terminal required for switching the self-arm switching element from the OFF state to the ON state, and reducing the reliability of the free wheel diode connected in reverse parallel to the opposing arm switching element The upper limit charging current of the switching control terminal that can be avoided is an on-rate limiting current,
The timing for determining the on-rate-limiting current is an intermediate timing from the input of the on-command to the completion of charging of the charge of the switching control terminal.
The charge command value setting means reduces the command charge current corresponding to each current flowing between the input / output terminals to the on-rate limiting current corresponding to each current flowing between the input / output terminals during the main charging period. The switching element drive circuit according to claim 9, wherein the switching element drive circuit is set.   The switching element drive circuit according to claim 10, wherein the end timing of the main charging period is set to the on-rate limiting point corresponding to a maximum value of a range that can be taken by the current flowing between the input and output terminals.   12. The switching element according to claim 10, wherein a start timing of the main charging period is set to the on-rate limiting point corresponding to a minimum value larger than 0 in a range that can be taken by a current flowing between the input and output terminals. Drive circuit.   The charging command value setting means uses the command charging current in the pre-charging period, which is a period from the input of the ON command to the start timing of the main charging period, as the command charging current in the start timing of the main charging period. The command charging current in the after charging period including the period from the end timing of the main charging period and the end timing of the main charging period to the time when the voltage of the switching control terminal rises to reach the upper limit voltage. The drive circuit for a switching element according to any one of claims 9 to 12, wherein at least one of processing for setting the command charging current to be larger than the command charging current at the end timing of the period is performed. The charging command value setting means includes
When the voltage between the input and output terminals is high, a first on-side process for setting the command charging current at the end timing of the main charging period smaller than when the voltage between the input and output terminals is low;
When the voltage between the input and output terminals is high, the second on-side process of accelerating the start timing of the main charging period with respect to the input timing of the on command than when the voltage between the input and output terminals is low The switching element drive circuit according to claim 9, wherein at least one of the processes is further performed. The charging control means is a series connection body connected between a constant voltage power source (60) and the open / close control terminal, and is a series connection of a charging resistor (62) and a charging switching element (63). By having a connection body and adjusting the on-resistance of the charging switching element, the charging current of the switching control terminal is controlled to the command charging current,
The charging command value setting means performs the first on-side processing and the second on-side processing when the voltage between the input / output terminals is higher than the on-side specified voltage, and the voltage between the input / output terminals is The switching element drive circuit according to claim 14, wherein when the voltage is equal to or lower than an on-side specified voltage, a process for fully turning on the charging switching element is performed instead of the first on-side process and the second on-side process.