JP2016167585A - 半導体装置、表示装置及び該表示装置を用いた電子機器 - Google Patents
半導体装置、表示装置及び該表示装置を用いた電子機器 Download PDFInfo
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- JP2016167585A JP2016167585A JP2016035178A JP2016035178A JP2016167585A JP 2016167585 A JP2016167585 A JP 2016167585A JP 2016035178 A JP2016035178 A JP 2016035178A JP 2016035178 A JP2016035178 A JP 2016035178A JP 2016167585 A JP2016167585 A JP 2016167585A
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Abstract
【解決手段】トランジスタと、第1の絶縁膜と、一対の電極間に第2の絶縁膜を含む容量素子とを有する半導体装置であって、トランジスタは、ゲート電極と、ゲート電極に接して設けられたゲート絶縁膜と、ゲート絶縁膜に接して設けられ、ゲート電極と重畳する位置に設けられた第1の酸化物半導体膜と、第1の酸化物半導体膜に電気的に接続されたソース電極及びドレイン電極と、を有し、容量素子の一対の電極の一方が、第2の酸化物半導体膜を含み、第1の絶縁膜は、第1の酸化物半導体膜上に設けられ、第2の絶縁膜は、第2の酸化物半導体膜が第1の絶縁膜と第2の絶縁膜とによって挟持されるように、第2の酸化物半導体膜上に設けられる。
【選択図】図1
Description
本実施の形態では、本発明の一態様の半導体装置について、図1乃至図12を用いて説明する。
図1(A)は、本発明の一態様の半導体装置の上面図であり、図1(B)は、図1(A)の一点鎖線A−B間、一点鎖線C−D間、及び一点鎖線E−F間の各切断線に対応する断面図に相当する。なお、図1(A)において、煩雑になることを避けるため、半導体装置の構成要素の一部(ゲート絶縁膜等)を省略して図示している。なお、トランジスタの上面図においては、以降の図面においても図1(A)と同様に、構成要素の一部を省略して図示する場合がある。
第1の酸化物半導体膜110及び第2の酸化物半導体膜111に用いることのできる酸化物半導体膜は、膜中の酸素欠損及び/又は膜中の水素、水等の不純物濃度によって、抵抗率を制御することができる半導体材料である。そのため、第1の酸化物半導体膜110及び第2の酸化物半導体膜111へ酸素欠損及び/又は不純物濃度が増加する処理、または酸素欠損及び/又は不純物濃度が低減する処理を選択することによって、それぞれの酸化物半導体膜の抵抗率を制御することができる。
基板102の材質などに大きな制限はないが、少なくとも、後の熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、シリコンや炭化シリコンからなる単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板等を適用することも可能であり、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。なお、基板102として、ガラス基板を用いる場合、第6世代(1500mm×1850mm)、第7世代(1870mm×2200mm)、第8世代(2200mm×2400mm)、第9世代(2400mm×2800mm)、第10世代(2950mm×3400mm)等の大面積基板を用いることで、大型の表示装置を作製することができる。また、基板102として、可撓性基板を用い、可撓性基板上に直接、トランジスタ150、容量素子160等を形成してもよい。
第1の酸化物半導体膜110及び第2の酸化物半導体膜111は、少なくともインジウム(In)、亜鉛(Zn)及びM(Al、Ti、Ga、Y、Zr、La、Ce、Nd、SnまたはHf等の金属)を含むIn−M−Zn酸化物で表記される膜を含むことが好ましい。また、該酸化物半導体を用いたトランジスタの電気特性のばらつきを減らすため、それらと共に、スタビライザーを含むことが好ましい。
トランジスタ150のゲート絶縁膜として機能する絶縁膜106、107としては、プラズマCVD(CVD:Chemical Vapor Deposition)法、スパッタリング法等により、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁膜を、それぞれ用いることができる。なお、絶縁膜106、107の積層構造とせずに、上述の材料から選択された単層の絶縁膜を用いてもよい。
ゲート電極104、ソース電極112a及びドレイン電極112bに用いることのできる材料としては、アルミニウム、チタン、クロム、ニッケル、銅、イットリウム、ジルコニウム、モリブデン、銀、タンタル、またはタングステンなどの金属、またはこれを主成分とする合金を単層構造または積層構造として用いることができる。例えば、アルミニウム膜上にチタン膜を積層する二層構造、タングステン膜上にチタン膜を積層する二層構造、モリブデン膜上に銅膜を積層した二層構造、モリブデンとタングステンを含む合金膜上に銅膜を積層した二層構造、銅−マグネシウム−アルミニウム合金膜上に銅膜を積層する二層構造、チタン膜または窒化チタン膜と、そのチタン膜または窒化チタン膜上に重ねてアルミニウム膜または銅膜を積層し、さらにその上にチタン膜または窒化チタン膜を形成する三層構造、モリブデン膜または窒化モリブデン膜と、そのモリブデン膜または窒化モリブデン膜上に重ねてアルミニウム膜または銅膜を積層し、さらにその上にモリブデン膜または窒化モリブデン膜を形成する三層構造等がある。また、ソース電極112a、及びドレイン電極112bを三層構造とする場合、一層目及び三層目には、チタン、窒化チタン、モリブデン、タングステン、モリブデンとタングステンを含む合金、モリブデンとジルコニウムを含む合金、又は窒化モリブデンでなる膜を形成し、2層目には、銅、アルミニウム、金又は銀、或いは銅とマンガンの合金等の低抵抗材料でなる膜を形成することが好ましい。なお、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、酸化シリコンを添加したインジウム錫酸化物等の透光性を有する導電性材料を用いてもよい。また、ゲート電極104、ソース電極112a及びドレイン電極112bに用いることのできる材料は、例えば、スパッタリング法を用いて形成することができる。
導電膜120は、画素電極としての機能を有する。導電膜120としては、例えば、可視光において、透光性を有する材料を用いればよい。具体的には、インジウム(In)、亜鉛(Zn)、錫(Sn)の中から選ばれた一種を含む材料を用いるとよい。また、導電膜120としては、例えば、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム錫酸化物(ITO:Indium Tin Oxide)、インジウム亜鉛酸化物、酸化ケイ素を添加したインジウム錫酸化物などの透光性を有する導電性材料を用いることができる。また、導電膜120としては、例えば、スパッタリング法を用いて形成することができる。
トランジスタ150の保護絶縁膜として機能する絶縁膜114、116、118としては、プラズマCVD法、スパッタリング法等により、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁膜を、それぞれ用いることができる。
次に、図1(A)、(B)に示す半導体装置の作製方法の一例について、図3乃至図6を用いて説明する。
本実施の形態では、本発明の一態様の半導体装置について、実施の形態1に示す半導体装置の変形例について、図7乃至図9を用いて説明する。なお、実施の形態1の図1乃至図4で示した符号と同様の箇所または同様の機能を有する箇所については同様の符号を用い、その繰り返しの説明は省略する。
図7(A)は、本発明の一態様の半導体装置の上面図であり、図7(B)は、図7(A)の一点鎖線G−H間、一点鎖線I−J間、及び一点鎖線K−L間の各切断線に対応する断面図に相当する。なお、図7(A)において、煩雑になることを避けるため、半導体装置の構成要素の一部(ゲート絶縁膜等)を省略して図示している。
次に、図7(A)、(B)に示す半導体装置の作製方法の一例について、図8及び図9を用いて説明する。
本実施の形態では、本発明の一態様の半導体装置について、実施の形態1に示す半導体装置の変形例について、図10乃至図12を用いて説明する。なお、実施の形態1の図1乃至図4で示した符号と同様の箇所または同様の機能を有する箇所については同様の符号を用い、その繰り返しの説明は省略する。
図10(A)は、本発明の一態様の半導体装置の上面図であり、図10(B)は、図10(A)の一点鎖線M−N間、一点鎖線O−P間、及び一点鎖線Q−R間の各切断線に対応する断面図に相当する。なお、図10(A)において、煩雑になることを避けるため、半導体装置の構成要素の一部(ゲート絶縁膜等)を省略して図示している。
次に、図10(A)、(B)に示す半導体装置の作製方法の一例について、図11及び図12を用いて説明する。
本実施の形態では、本発明の一態様の半導体装置のトランジスタ、容量素子、及びゲート配線コンタクト部に適用可能な酸化物半導体の一例について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
以下では、CAAC−OSの成膜方法の一例について説明する。図18は、成膜室内の模式図である。CAAC−OSは、スパッタリング法により成膜することができる。
本実施の形態では、実施の形態1に示すトランジスタとは異なる構成のトランジスタの構成について、図21乃至図24を参照して説明する。
図21(A)は、トランジスタ270の上面図であり、図21(B)は、図21(A)に示す一点鎖線X1−X2間の切断線に対応する断面図に相当し、図21(C)は、図21(A)に示す一点鎖線Y1−Y2間の切断線に対応する断面図に相当する。なお、一点鎖線X1−X2方向をチャネル長方向、一点鎖線Y1−Y2方向をチャネル幅方向と呼称する場合がある。
次に、図21(A)(B)(C)に示すトランジスタ270と異なる構成例について、図22(A)(B)(C)(D)を用いて説明する。
本実施の形態では、本発明の一態様である表示装置80について、図25乃至図42を用いて説明する。
次に、表示装置80に含まれる素子基板の具体的な構成について説明する。まず、FFSモードによって駆動する表示装置80が有する複数の画素70a、70b、70cの上面図を図26に示す。
次に、表示装置80が有する、図26に示す画素とは異なる構成の複数の画素70d、70e、70fの上面図を図29に示す。
次に、図25(A)に示す表示装置80が有する、上記とは異なる構成の複数の画素370の構成について説明する。図41(A)に画素370の回路構成の一例を示す。また図41(B)は表示装置80が有する複数の画素370g、370h、370iの上面図であり、図42は図41(B)の一点鎖線Q3−R3、及びS3−T3における断面図である。
本実施の形態では、本発明の一態様の液晶表示装置に適用可能な垂直配向(VA:Vertical Alignment)モードで動作する液晶素子を備える画素の構成について、図43乃至図45を参照して説明する。図43は液晶表示装置が備える画素の上面図であり、図44は図43の切断線Z1−Z2における断面を含む側面図である。また、図45は、液晶表示装置が備える画素の等価回路図である。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する表示装置の一例について、図46及び図47を用いて以下説明を行う。
本実施の形態においては、本発明の一態様の表示装置、及び該表示装置の駆動方法について、図48乃至図51を用いて説明を行う。
ここで、本発明の一態様の表示装置の駆動方法について、図50を用いて説明する。
以下では、2つの異なるイメージ情報を含む画像を移動させて表示する例について示す。
次に、表示ウィンドウの大きさよりも大きな文書情報をスクロールさせて表示する例について説明する。
本実施の形態では、本発明の一態様の半導体装置を有する表示モジュール及び電子機器について、図52及び図53を用いて説明を行う。
スクロールの速度が遅い場合、スクロールの速度が速い場合に比べて、同じ期間に生じる輝度の変化が少なく、視覚刺激が抑制されることが分かった(図54(A)、図54(C)、図55(A)および図55(C)参照)。
13 導電膜
15 絶縁膜
17 絶縁膜
19a 酸化物半導体膜
19b 酸化物半導体膜
19c コモン電極
21a 導電膜
21b 導電膜
23 絶縁膜
25 絶縁膜
27 絶縁膜
28 絶縁膜
29 コモン電極
51 液晶素子
52 トランジスタ
55 容量素子
70 画素
70a 画素
70b 画素
70c 画素
70d 画素
70e 画素
70f 画素
71 画素部
74 走査線駆動回路
75 コモン線
76 信号線駆動回路
77 走査線
79 信号線
80 表示装置
100 直径
102 基板
104 ゲート電極
105 ゲート配線
106 絶縁膜
107 絶縁膜
108 絶縁膜
110 酸化物半導体膜
111 酸化物半導体膜
111a 酸化物半導体膜
111b 酸化物半導体膜
112 配線
112a ソース電極
112b ドレイン電極
114 絶縁膜
116 絶縁膜
118 絶縁膜
119 絶縁膜
120 導電膜
120a 導電膜
141 開口
142 開口
144 開口
146 開口
148 開口
150 トランジスタ
151 トランジスタ
160 容量素子
170 ゲート配線コンタクト部
171 ゲート配線コンタクト部
193 ターゲット
194 プラズマ
202 基板
204 導電膜
206 絶縁膜
207 絶縁膜
208 酸化物半導体膜
208a 酸化物半導体膜
208b 酸化物半導体膜
208c 酸化物半導体膜
211a 酸化物半導体膜
211b 酸化物半導体膜
212a 導電膜
212b 導電膜
214 絶縁膜
216 絶縁膜
218 絶縁膜
220b 導電膜
252a 開口部
252b 開口部
252c 開口部
270 トランジスタ
270A トランジスタ
270B トランジスタ
319b 酸化物半導体膜
329 導電膜
351a 液晶素子
351b 液晶素子
352 トランジスタ
355 容量素子
355a 容量素子
355b 容量素子
370 画素
370g 画素
370h 画素
370i 画素
450 表示部
451 ウィンドウ
452a 画像
452b 画像
453 ボタン
455 ウィンドウ
456 文書情報
457 スクロールバー
600 基板
601 基板
602 ゲート配線
604 容量配線
605 容量配線
613 配線
615 ゲート配線
616 配線
618 ドレイン電極
623 絶縁膜
624 画素電極
625 絶縁膜
626 画素電極
627 絶縁膜
628 トランジスタ
629 トランジスタ
630 容量素子
631 容量素子
633 開口
636 着色膜
640 コモン電極
644 突起
645 配向膜
646 スリット
647 スリット
648 配向膜
650 液晶層
651 液晶素子
652 液晶素子
700 表示装置
701 基板
702 画素部
704 ソースドライバ回路部
705 基板
706 ゲートドライバ回路部
708 FPC端子部
710 配線
711 配線部
712 シール材
716 FPC
734 絶縁膜
736 着色膜
738 遮光膜
750 トランジスタ
752 トランジスタ
760 接続電極
764 絶縁膜
766 絶縁膜
768 絶縁膜
772 導電膜
774 導電膜
775 液晶素子
776 液晶層
778 構造体
780 異方性導電膜
790 容量素子
5000 筐体
5001 表示部
5002 表示部
5003 スピーカ
5004 LEDランプ
5005 操作キー
5006 接続端子
5007 センサ
5008 マイクロフォン
5009 スイッチ
5010 赤外線ポート
5011 記録媒体読込部
5012 支持部
5013 イヤホン
5014 アンテナ
5015 シャッターボタン
5016 受像部
5017 充電器
5100 ペレット
5120 基板
5161 領域
5200 ペレット
5201 イオン
5202 横成長部
5203 粒子
5220 基板
5230 ターゲット
5240 プラズマ
5260 加熱機構
8000 表示モジュール
8001 上部カバー
8002 下部カバー
8003 FPC
8004 タッチパネル
8005 FPC
8006 表示パネル
8007 バックライト
8008 光源
8009 フレーム
8010 プリント基板
8011 バッテリ
Claims (9)
- トランジスタと、
第1の絶縁膜と、
一対の電極間に第2の絶縁膜を含む容量素子と、を有する半導体装置であって、
前記トランジスタは、
ゲート電極と、
前記ゲート電極に接して設けられたゲート絶縁膜と、
前記ゲート絶縁膜に接して設けられ、前記ゲート電極と重畳する位置に設けられた第1の酸化物半導体膜と、
前記第1の酸化物半導体膜に電気的に接続されたソース電極及びドレイン電極と、を有し、
前記容量素子の一対の電極の一方が、第2の酸化物半導体膜を含み、
前記第1の絶縁膜は、前記第1の酸化物半導体膜上に設けられ、
前記第2の絶縁膜は、前記第2の酸化物半導体膜が前記第1の絶縁膜と前記第2の絶縁膜とによって挟持されるように、前記第2の酸化物半導体膜上に設けられることを特徴とする、
半導体装置。 - 請求項1において、
導電膜を有し、
前記容量素子の一対の電極の他方が前記導電膜を含むことを特徴とする、
半導体装置。 - 請求項1または請求項2において、
前記トランジスタは、
前記第1の絶縁膜と、
前記第1の酸化物半導体膜と重畳する位置に設けられた前記第2の酸化物半導体膜と、を有することを特徴とする、
半導体装置。 - 請求項1または請求項2において、
前記トランジスタは、
前記第1の絶縁膜と、
前記第2の絶縁膜と、
前記第1の酸化物半導体膜と重畳する位置に設けられた前記導電膜と、を有することを特徴とする、
半導体装置。 - 請求項1乃至請求項4において、
前記容量素子は、可視光において透光性を有することを特徴とする、
半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記第1の酸化物半導体膜及び前記第2の酸化物半導体膜は、
In−M−Zn酸化物(MはAl、Ti、Ga、Y、Zr、La、Ce、Nd、SnまたはHfを表す)であることを特徴とする、
半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記第1の絶縁膜は、酸素を含み、
前記第2の絶縁膜は、水素を含むことを特徴とする、
半導体装置。 - 請求項1乃至請求項7のいずれか一つに記載の半導体装置と、
液晶素子と、
を有する表示装置。 - 請求項1乃至請求項7のいずれか一つに記載の半導体装置と、
スイッチ、スピーカ、表示部または筐体と、
を有する電子機器。
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JP2019024105A (ja) * | 2016-12-23 | 2019-02-14 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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US20220013545A1 (en) | 2022-01-13 |
KR20160107110A (ko) | 2016-09-13 |
US20160260751A1 (en) | 2016-09-08 |
JP6801969B2 (ja) | 2020-12-16 |
TW201637100A (zh) | 2016-10-16 |
JP2022171665A (ja) | 2022-11-11 |
TWI686870B (zh) | 2020-03-01 |
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JP2021048403A (ja) | 2021-03-25 |
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