JP2016167564A - Wiring board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board manufacturing method which is less likely to cause defects.SOLUTION: A wiring board manufacturing method of the present embodiment includes an intermediate substrate manufacturing process, an insulation layer formation process, a column removal process and a conductor formation process. In the intermediate substrate formation process, an intermediate substrate 20 including a blind hole 22 formed in a semiconductor substrate 2, a semiconductor column 10 standing in the blind hole 22 and an edge region 23 which is a portion of the semiconductor substrate 2 near an edge of the blind bole 22 and lower than the semiconductor column 10 is manufactured by etching. In the insulation layer formation process, an insulating material is filled in the blind hole 22 of the manufactured intermediate substrate 20 to form an insulation layer 3. In the column removal process, etching is performed after the insulation layer formation process to remove the semiconductor column 10 to form a columnar conductor hole. In the conductor formation process, a conductive material is filled in the columnar conductor hole to form a columnar conductor 4.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a method for manufacturing a wiring board.

  In response to downsizing and higher performance of electronic devices, cases where a three-dimensional structure is employed instead of a two-dimensional structure as the structure of a wiring board are increasing. In the three-dimensional structure, a plurality of substrates are stacked. A columnar conductor represented by a through silicon via (TSV) is used to connect the stacked substrates.

  The columnar conductor needs to be insulated from the semiconductor substrate on which the columnar conductor is formed. In Japanese Patent Application Laid-Open No. 2008-251964 (Patent Document 1), a ring-shaped separation groove surrounding a through electrode is formed in a semiconductor substrate. An insulating film is formed in the separation groove. In this case, the through electrode is insulated from the semiconductor substrate by the insulating film in the separation groove. However, in Patent Document 1, it is difficult to form an insulating film having a sufficient thickness. Therefore, the insulation function may not be sufficient.

  Japanese Patent No. 5225479 (Patent Document 2) discloses a method of manufacturing a wiring board capable of maintaining the insulating function of an insulating layer. Specifically, the manufacturing method of Patent Document 2 includes an insulating layer forming step and a conductor forming step. In the insulating layer forming step, holes or grooves are formed in the thickness direction of the semiconductor substrate, and an insulating layer is formed in the formed holes or grooves. In the conductor forming step, a hole or groove is formed in the insulating layer, and a conductor is formed by filling the hole or groove with a conductor component made of a metal component or the like. Patent Document 2 describes that this manufacturing method suppresses the formation of defects (such as gaps, cavities, and cracks) in the insulating layer and maintains a sufficient insulating function of the insulating layer.

  However, Patent Document 2 does not disclose a narrow pitch TSV forming technique in which a large number of narrow pitches are provided side by side. In the case of forming the narrow pitch TSV, if the formation positions of the conductor holes or grooves are slightly shifted, defects (for example, poor contact, etc.) may occur in the through electrodes.

  Japanese Patent No. 5490949 (Patent Document 3) discloses a technique for solving the problem of Patent Document 2. In Patent Document 3, columnar bodies made of a semiconductor substrate are present at intervals from each other in an insulating portion formed in the thickness direction from one surface of the semiconductor substrate. Then, the columnar body is removed, and the columnar conductor is filled in the removal trace.

  In Patent Document 3, each of the plurality of columnar conductors is insulated from each other by a common insulating portion and also from a semiconductor substrate. Therefore, as compared with the wiring board disclosed in Patent Document 2, Patent Document 3 describes that the pitch of the columnar conductors can be reduced and a wiring board having a narrow pitch TSV structure can be realized.

JP 2008-251964 A Patent No. 5225479 Patent No. 5490949

  However, the manufacturing method of Patent Document 3 may cause the following problem. In the manufacturing method of Patent Document 3, a bottomed hole in which a plurality of semiconductor pillars are erected from the bottom surface is formed on a semiconductor substrate, and the bottomed hole is filled with a fluid insulating material to form an insulating layer. At this time, the semiconductor pillar and the peripheral edge of the bottomed hole have the same height. Since it is necessary to sufficiently fill the bottomed hole with the fluid insulating material, the surplus insulating material is filled. Excess insulating material overflows from the bottomed hole and covers the upper end of the semiconductor pillar. Therefore, when the insulating layer is formed, the upper end of the semiconductor pillar is buried in the insulating layer. In order to remove the semiconductor pillar by etching, first, the insulator on the semiconductor pillar must be removed by etching using an etching mask having an opening at the position where the semiconductor pillar is disposed. In this case, the opening position of the mask must be accurately matched with the arrangement position of the semiconductor pillar. When the cross section of the semiconductor pillar is very small, the alignment of the etching mask is very difficult. Therefore, the etching accuracy is low, and defects such as poor contact may occur in the wiring board.

  An object of the present invention is to provide a method for manufacturing a wiring board in which defects are less likely to occur.

  The method for manufacturing a wiring board according to the present embodiment manufactures a wiring board. The wiring board includes a semiconductor substrate, an insulating layer, and a columnar conductor. The manufacturing method includes an intermediate substrate manufacturing process, an insulating layer forming process, a column removing process, and a conductor forming process. In the intermediate substrate manufacturing process, an intermediate substrate including a bottomed hole formed in the semiconductor substrate, one or more semiconductor pillars standing in the bottomed hole, and an edge region of the bottomed hole lower than the semiconductor pillar is provided. Manufactured by etching. In the insulating layer forming step, the bottomed hole of the manufactured intermediate substrate is filled with an insulating material to form an insulating layer. In the pillar removing step, the semiconductor pillar is removed by etching after the insulating layer forming step. In the conductor forming step, the hole formed by removing the semiconductor is filled with a conductive material to form a columnar conductor.

  The wiring board manufacturing method of this embodiment can manufacture a wiring board that is less prone to defects.

FIG. 1 is a perspective view of a wiring board manufactured by the manufacturing method of the first embodiment. FIG. 2 is a cross-sectional view shown in FIG. FIG. 3 is a perspective view showing one process in the manufacturing process of a known wiring board. FIG. 4 is a cross-sectional view of the wiring board for explaining the next step of FIG. FIG. 5 is a cross-sectional view of the intermediate substrate according to the present embodiment. 6 is a cross-sectional view of the intermediate substrate after the intermediate substrate shown in FIG. 5 is filled with an insulating material. FIG. 7 is a cross-sectional view of the semiconductor substrate showing one process in the manufacturing process of the wiring board of the present embodiment. FIG. 8 is a cross-sectional view of a semiconductor substrate for explaining the next step of FIG. FIG. 9 is a cross-sectional view of the semiconductor substrate for explaining the next step of FIG. FIG. 10 is a cross-sectional view of the semiconductor substrate for explaining the next step of FIG. FIG. 11 is a cross-sectional view of the semiconductor substrate for explaining the next step of FIG. FIG. 12 is a cross-sectional view of a semiconductor substrate for explaining the next step of FIG. FIG. 13 is a cross-sectional view of the semiconductor substrate for explaining the next step of FIG. FIG. 14 is a cross-sectional view of the semiconductor substrate for explaining the next step of FIG. FIG. 15 is a cross-sectional view of the semiconductor substrate after the semiconductor substrate of FIG. 14 is filled with an insulating material and the semiconductor pillar is removed. FIG. 16 is a cross-sectional view of a semiconductor substrate for explaining the next step of FIG. FIG. 17 is a cross-sectional view of a semiconductor substrate for explaining the second embodiment.

  The method for manufacturing a wiring board according to the present embodiment manufactures a wiring board. The wiring board includes a semiconductor substrate, an insulating layer filled in a hole formed in the semiconductor substrate, and one or more columnar conductors formed on the insulating layer and having an upper end exposed from the surface of the insulating layer. The manufacturing method includes an intermediate substrate manufacturing process, an insulating layer forming process, a column removing process, and a conductor forming process. In the intermediate substrate manufacturing process, a bottomed hole formed in the semiconductor substrate, one or more semiconductor pillars standing in the bottomed hole, and a portion of the semiconductor substrate near the edge of the bottomed hole, An intermediate substrate with a lower edge region is produced by etching. In the insulating layer forming step, the bottomed hole of the manufactured intermediate substrate is filled with an insulating material to form the insulating layer. In the column removing step, after the insulating layer forming step, the semiconductor columns are removed by etching to form columnar conductor holes. In the conductor forming step, the columnar conductor is formed by filling the hole for the columnar conductor with a conductive material.

  In the present embodiment, a step is formed between the semiconductor pillar and the edge region in the manufactured intermediate substrate. Specifically, the edge region is formed lower than the semiconductor pillar. Therefore, in the insulating layer forming process, even when the insulating material overflows from the bottomed hole when the bottomed hole is filled with the fluid insulating material, the insulating material covers the edge region but covers the upper end of the semiconductor pillar. Can be suppressed. Therefore, an etching mask need not be used in order to expose the upper end of the semiconductor pillar from the surface of the insulating layer. Therefore, it is possible to suppress the occurrence of contact failure or the like on the wiring board based on the positional shift when using the etching mask.

  The intermediate substrate manufacturing step includes, for example, a step of forming a first etching mask, a step of forming a second etching mask, a column forming step, a step of removing the second etching mask, a step forming step, And a step of removing the etching mask. In the step of forming the first etching mask, a first etching mask is formed which is disposed on the region where the semiconductor pillar of the semiconductor substrate is formed and has an opening on the region where the bottomed hole and the edge region are formed. In the step of forming the second etching mask, the second etching mask is formed on the first etching mask, disposed on the region where the semiconductor pillar is formed and the region where the edge region is formed, and on the region where the bottomed hole is formed. A second etching mask having an opening is formed. In the column forming step, after forming the second etching mask, anisotropic etching is performed to remove a part of the semiconductor substrate at the opening positions of the first and second etching masks, and the bottomed hole and the semiconductor column are formed. Form. After the hole forming step, the second etching mask is removed. In the step forming process, after removing the second etching mask, anisotropic etching is performed on the edge region using the first etching mask remaining on the semiconductor substrate, so that the edge region is lower than the semiconductor pillar. Form. After the step forming process, the first etching mask is removed.

  In the intermediate substrate manufacturing process described above, two-stage etching is performed using the stacked first and second etching masks. Thereby, a step can be easily formed between the semiconductor pillar and the edge region.

  In the above-described wiring board manufacturing method, in the insulating layer forming step, the upper end of the semiconductor pillar is exposed from the insulating layer when the insulating layer is formed.

  In the above-described method for manufacturing a wiring board, after the insulating layer forming step, the upper layer of the semiconductor pillar may be exposed from the insulating layer by removing the surface layer of the insulating layer.

  Even in this case, the above-described step is provided between the semiconductor pillar and the edge region. Therefore, most of the insulating layer overflowing from the bottomed hole flows to the edge region. Therefore, there are few insulating materials which cover the upper end of the semiconductor pillar. Therefore, even when the insulating layer is removed by etch back or the like, the upper end of the semiconductor pillar can be exposed from the surface of the insulating layer with a small removal amount.

  In the above column removal step, any one of plasma etching, gas etching, and wet etching may be performed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[First Embodiment]
[Configuration of wiring board]
FIG. 1 is a perspective view of a wiring board manufactured by the manufacturing method of this embodiment. With reference to FIG. 1, a wiring substrate 1 includes a semiconductor substrate 2, an insulating layer 3, and a plurality of columnar conductors 4.

  The semiconductor substrate 2 is, for example, a silicon (Si) semiconductor substrate. 2 is a cross-sectional view of a region indicated by a two-dot chain line in FIG. As shown in FIG. 2, the semiconductor substrate 2 has a through hole 21. Therefore, openings of through holes 21 are formed on the front and back surfaces of the semiconductor substrate 2.

  The insulating layer 3 is filled in the through hole 21. The insulating layer 3 is, for example, a well-known insulating resin. The insulating resin is, for example, a thermosetting resin. The thermosetting resin is, for example, a composition containing one or more of epoxy resin, cyanate resin, phenol resin and the like. The insulating resin may contain oxidized particles (silicon oxide, titanium oxide, etc.).

  A plurality of through holes are formed in the insulating layer 3. The columnar conductor 4 is formed by filling each through hole. The columnar conductor 4 functions as a through electrode, for example. The columnar conductor 4 is made of a known material, for example, a metal, an alloy, or the like. The columnar conductor 4 may contain another conductive substance in a metal, an alloy, or the like. More specifically, the columnar conductor 4 contains, for example, Au, Ag, Pt, Cu, Ti, Zn, Al, Fe, B, Si, Ni, In, Sn, Bi, and Ga.

  In FIG. 1, the cross section of the columnar conductor 4 is circular. However, the cross-sectional shape of the columnar conductor 4 is not particularly limited. The cross section of the columnar conductor 4 may be polygonal. In FIG. 1, the plurality of columnar conductors 4 are arranged in a matrix. However, the arrangement of the columnar conductors 4 is not limited to a matrix.

[Outline of manufacturing method of wiring board]
An example of a conventional method for manufacturing a wiring board is as follows. First, as shown in FIG. 3, a bottomed hole 22 is formed in the semiconductor substrate 2 by etching to manufacture an intermediate substrate (intermediate substrate manufacturing process). A plurality of semiconductor pillars 10 arranged in a matrix are erected on the bottom of the bottomed hole 22. The bottomed hole 22 and the semiconductor pillar 10 are formed by deep etching (anisotropic etching) using a mask (not shown). After the bottomed hole 22 and the semiconductor pillar 10 are formed, the bottomed hole 22 is filled with an insulating material to form an insulating layer (insulating layer forming step). After forming the insulating layer, the semiconductor pillar 10 is removed by a known method (etching or the like) to form a plurality of pillar-shaped conductor holes (pillar removal process). The columnar conductors 4 are formed by filling the columnar conductor holes with a conductor material (conductor formation step). The wiring board is manufactured through the above steps.

  In the insulating layer forming process described above, the bottomed hole 22 must be sufficiently filled with a fluid insulating material. As shown in FIG. 4, the height of the semiconductor pillar 10 and the height of the edge region 23 of the bottomed hole 22 in the semiconductor substrate 2 are the same. In this case, if the bottomed hole 22 is sufficiently filled with the insulating material, the insulating material overflows from the bottomed hole 22, and the insulating material covers the semiconductor pillar 10 and the edge region 23. As a result, the insulating layer 3 covers the semiconductor pillar 10 and the edge region 23.

  After the insulating layer 3 covers the semiconductor pillar 10 and the edge region 23 as shown in FIG. 4, the insulating layer portion on the semiconductor pillar 10 is removed by etching using an etching mask to expose the upper end of the semiconductor pillar 10. In this case, it is necessary to accurately match the opening position of the etching mask with the arrangement position of the semiconductor pillar 10. However, the semiconductor pillar 10 is embedded in the insulating layer 3. Therefore, it is difficult to accurately match the opening position of the etching mask with the arrangement position of the semiconductor pillar 10. If the opening position of the etching mask and the arrangement position of the semiconductor pillar 10 are shifted, the upper end of the semiconductor pillar 10 is not sufficiently exposed. In this case, the semiconductor pillar 10 is not sufficiently removed in the removing step. In this case, a contact failure or the like may occur in the columnar conductor, and a failure may occur in the wiring board.

  In the present embodiment, as shown in FIG. 5, the edge region 23 is formed lower than the semiconductor pillar 10 in the intermediate substrate 20. In this case, even if the insulating material overflows from the bottomed hole 22 by sufficiently filling the bottomed hole 22 with the insulating material in the insulating layer forming step, the surplus insulating material flows mainly onto the edge region 23. Therefore, as shown in FIG. 6, the upper end of the semiconductor pillar 10 is not buried in the insulating layer 3 and is easily exposed from the surface of the insulating layer 3. When the upper end of the semiconductor pillar 10 is exposed from the insulating layer 3, the opening position of the etching mask is more accurately aligned with the arrangement position of the semiconductor pillar 10 than when the upper end of the semiconductor pillar 10 is not exposed from the insulating layer 3. Easy to fit. Further, in this case, since the upper end of the semiconductor pillar 10 is already exposed, the semiconductor pillar 10 can be removed by etching without using an etching mask. Therefore, the malfunction which arises when using the above-mentioned etching mask does not occur. As a result, it is possible to suppress the occurrence of defects such as contact failure in the wiring board. Hereinafter, the manufacturing method of the wiring board of this embodiment will be described in detail.

[Method of manufacturing a wiring board]
The method for manufacturing a wiring board according to the present embodiment includes an intermediate substrate manufacturing process, an insulating layer forming process, a column removing process, and a conductor forming process. Hereinafter, each step will be described.

[Intermediate substrate manufacturing process]
In the intermediate substrate manufacturing process, the intermediate substrate 20 shown in FIG. 5 is manufactured. As described above, the intermediate substrate 20 includes the bottomed hole 22 formed in the semiconductor substrate 2, the plurality of semiconductor pillars 10, and the edge region 23.

  A plurality of semiconductor pillars 10 are erected on the bottom of the bottomed hole 22. The semiconductor pillars 10 are arranged apart from each other. The semiconductor pillar 10 is columnar. The cross-sectional shape of the semiconductor pillar 10 is not particularly limited. The cross shape of the semiconductor pillar 10 may be circular or polygonal.

  The edge region 23 is a region near the edge of the bottomed hole 22 in the semiconductor substrate 2. The edge region 23 is formed lower than the semiconductor pillar 10. More specifically, the upper end of the edge region 23 is lower than the upper end of the semiconductor pillar 10.

  As described above, the intermediate substrate 20 has a step between the semiconductor pillar 10 and the edge region 23. This step can prevent the upper end of the semiconductor pillar 10 from being covered with the insulating material when the bottomed hole 22 is filled with the insulating material.

  The manufacturing method of the intermediate substrate 20 is not particularly limited. In the present embodiment, as an example of the intermediate substrate manufacturing process, a method of manufacturing the intermediate substrate 20 by forming double etching masks and etching in two stages will be described.

  The intermediate substrate manufacturing process includes a first mask forming process, a second mask forming process, a column forming process, a second mask removing process, a step forming process, and a first mask removing process. Hereinafter, each step will be described.

[First mask forming step]
As shown in FIG. 7, first, a first etching mask 50 is formed on the semiconductor substrate 2. The first etching mask 50 is made of, for example, silicon dioxide. The first etching mask 50 may be a metal such as nickel. At this point, the first etching mask does not have a mask pattern (opening).

  After forming the first etching mask 50, a resist layer 51 is further formed on the first etching mask 50. The resist layer 51 is formed on the semiconductor substrate 2 on the region to be the semiconductor pillar 10 and the bottomed hole 22 and is not formed on the region to be the edge region 23. After the resist layer 51 is formed, etching is performed by a known method. As a result, as shown in FIG. 8, a part of the first etching mask 50 is removed, and a region of the semiconductor substrate 2 where the edge region 23 is formed is exposed. Thereafter, as shown in FIG. 9, the resist layer 51 is removed.

[Second mask forming step]
Subsequently, a mask pattern is formed on the first etching mask 50. Specifically, as shown in FIG. 10, a second etching mask 52 is formed on the first etching mask 50. The second etching mask 52 is made of a well-known resist (photosensitive material), and is formed on the region to be the edge region 23 and the region to be the semiconductor pillar 10. Therefore, the second etching mask has an opening on a region where the bottomed hole 22 is formed.

  After the second etching mask 52 is formed, anisotropic etching is performed to form a mask pattern on the first etching mask 50 as shown in FIG. At this time, the first etching mask 50 is disposed on the region where the semiconductor pillar 10 is formed, and has an opening on the region where the bottomed hole 22 and the edge region 23 are formed.

  As described above, in the present embodiment, the first and second etching masks 50 and 52 are formed. As described above, the first etching mask 50 has openings in the region to be the bottomed hole 22 and the region to be the edge region 23. On the other hand, the second etching mask 50 includes a portion stacked on the first etching mask and a portion stacked on a region corresponding to the edge region 23. For this reason, the second etching mask 50 has an opening in a region to be the bottomed hole 22, but does not have an opening in a region corresponding to the edge region 23. The intermediate substrate 20 having a step can be manufactured by performing the two-stage etching using the two stacked etching masks.

[Column forming step (first etching during two-stage etching)]
Subsequently, anisotropic etching is performed on the semiconductor substrate 2 using the first and second etching masks 50 and 52. A typical example of anisotropic etching is the Bosch process. The Bosch process includes an etching step and a protective film forming step.

  In the etching process, isotropic etching is performed using an etching gas. The etching gas is, for example, fluorine gas. The fluorine gas is, for example, sulfur hexafluoride (SF6) gas.

In the protective film forming step, a protective film is formed on the side wall of the hole formed by the etching step. By protecting the side wall by forming the protective film, etching on the side wall is suppressed in the etching process. As a result, anisotropic etching can be realized. The protective film forming gas is, for example, a fluorocarbon gas and / or 2,3,3,3-tetrafluoropropene (HFO1234yf). The fluorocarbon gas is, for example, C ₄ F ₈ .

  In the Bosch process, the etching process and the protective film forming process are alternately performed. In this case, by controlling the flow rate of the protective film forming gas and the etching gas and the switching timing of the etching process and the protective film forming process, the anisotropic etching is controlled while adjusting the etching to the sidewall of the formed hole. Can do.

  As a result of performing the above-described anisotropic etching, a bottomed hole 22, a plurality of semiconductor pillars 10, and an edge region 23 are formed in the semiconductor substrate 2 as shown in FIG.

[Step forming step (second etching during two-step etching)]
Subsequently, a step is formed on the semiconductor substrate 2 using the first etching mask 50. Specifically, first, as shown in FIG. 13, the second etching mask 52 is removed by a known method. At this time, although the first etching mask 50 is formed on the semiconductor pillar 10, the edge region 23 is exposed. Therefore, anisotropic etching is performed using the first etching mask 50. By this etching, the edge region 23 is etched. As a result, as shown in FIG. 14, the edge region 23 is lower than the semiconductor pillar 10. In this etching, not only the edge region but also the bottomed hole 22 is etched, and the bottomed hole 22 becomes deeper. The first etching mask 50 is removed by a known method to manufacture the intermediate substrate 20 shown in FIG.

[Insulating layer forming step]
In the insulating layer forming step, the bottomed hole 22 of the intermediate substrate 20 is filled with a fluid insulating material. The insulating material is, for example, the above-described thermosetting resin.

  As described above, in the intermediate substrate 20, the edge region 23 is formed lower than the semiconductor pillar 10. Therefore, by sufficiently filling the bottomed hole 22 with the insulating material, even if the bottomed hole 22 overflows the insulating material, the insulating material flows out into the edge region 23 and covers the edge region 23 as shown in FIG. However, it is difficult to cover the semiconductor pillar 10. Therefore, even after the insulating material is cured and the insulating layer 3 is formed, the upper end of the semiconductor pillar 10 is easily exposed from the insulating layer 3.

  As described above, in the present embodiment, by providing a step between the semiconductor pillar 10 and the edge region 23, it is difficult to cover the upper end of the semiconductor pillar 10 with the insulating material when the insulating layer 3 is formed. If the upper end of the semiconductor pillar 10 is exposed from the insulating layer 3, it is not necessary to expose the upper end of the semiconductor pillar 10 from the insulating layer using an etching mask. For this reason, it is possible to suppress the occurrence of defects such as poor contact of the wiring board due to the displacement of the etching mask position.

[Column removal process]
In the column removing step, the semiconductor column 10 exposed from the insulating layer 3 is removed with reference to FIG. Specifically, the semiconductor pillar 10 is removed by a known etching technique. Preferably, any one of plasma etching, gas etching, and wet etching is performed as an etching technique. The selection ratio of the insulating layer 3 to the semiconductor pillar 10 is high. Therefore, in this case, the semiconductor pillar 10 can be sufficiently removed. At this time, it is not necessary to use an etching mask. As a result of the etching, as shown in FIG. 15, the semiconductor pillar 10 is removed, and a conductor hole 24 (bottomed hole) for forming the pillar-shaped conductor 4 is formed. Preferably, in the column removing step, gas etching using CIF ₃ and gas etching using XeF ₂ (xenon difluoride) are performed. In these gas etchings, the selectivity can be increased. Therefore, in this case, the semiconductor pillar 10 can be etched and removed without using an etching mask.

[Conductor formation process]
In the conductor forming step, as shown in FIG. 16, the conductor hole 24 is filled with a conductor material to form the columnar conductor 4. The columnar conductor 4 is made of a known material as described above. It is sufficient to apply a known method for filling the conductor material. Examples of the filling method include a plating method, a molten metal filling method, and a conductive paste method.

  If necessary, the surface layer portion of the back surface 25 of the semiconductor substrate 2 is removed. The removal method is, for example, grinding. As a result, the wiring substrate 1 shown in FIGS. 1 and 2 is manufactured. Depending on the application, the wiring substrate 1 may be used without removing the back surface 25.

  As described above, in the manufacturing method of the present embodiment, a two-step etching is performed using the two stacked etching masks 50 and 52 to form a step between the semiconductor pillar 10 and the edge region 23. Thereby, when the insulating layer 3 is formed, the upper end of the semiconductor pillar 10 is not easily covered with the insulating material. That is, the upper end of the semiconductor pillar 10 is easily exposed from the insulating layer 3. If the semiconductor pillar 10 is exposed from the insulating layer 3, the semiconductor pillar 10 can be removed without using an etching mask. Therefore, it is possible to suppress the occurrence of defects such as poor contact in the wiring board due to the displacement of the etching mask position.

[Second Embodiment]
As described above, if the intermediate substrate 20 having a step is used, the semiconductor pillar 10 can be prevented from being covered with the insulating material in the insulating layer forming step. However, as shown in FIG. 17, even if the insulating material flows on the edge region 23, the upper end of the semiconductor pillar 10 may be covered with the insulating material. In this case, the insulating layer 3 is also formed on the semiconductor pillar 10 as shown in FIG.

  In such a case, the entire surface layer of the insulating layer 3 is removed, and the upper surface of the semiconductor pillar 10 is exposed from the insulating layer 3 as shown in FIG. A method for removing the entire surface layer of the insulating layer 3 is, for example, etch back. If the entire surface layer of the insulating layer 3 is etched by etch back, the upper end of the semiconductor pillar 10 is exposed from the insulating layer 3 without using an etching mask.

  The method of removing the entire surface layer of the insulating layer 3 is not limited to etch back. For example, the insulating layer 3 may be removed by grinding. In this case, a part of the upper end of the semiconductor pillar 10 is also removed together with the insulating layer 3.

  As described above, even if the insulating material is covered on the semiconductor pillar 10 as shown in FIG. 17, the entire surface layer of the insulating layer 3 is removed by etching back or the like, so that the upper end of the semiconductor pillar 10 is used without using an etching mask. Can be exposed from the insulating layer 3. Therefore, no misalignment or the like due to the etching mask occurs, and the occurrence of defects such as contact failure is suppressed in the manufactured wiring board.

  In the above-described embodiment, a plurality of semiconductor pillars 10 are erected. However, only one semiconductor pillar 10 may be erected.

The columnar conductor 4 shown in FIGS. 1 and 2 penetrates the semiconductor substrate 2 and functions as a through electrode. However, as described above, only one of the two ends of the columnar conductor 4 may be exposed on the surface of the semiconductor substrate 2.
In FIG. 2, a region 23 having a step with the columnar conductor 4 is formed. The region 23 may be formed in a cross section perpendicular to the cross section in FIG. 2 (a cross section in a direction from the front side to the back side in FIG. 1). In short, the region 23 may be formed at any edge of the bottomed hole.

  The embodiment of the present invention has been described above. However, the above-described embodiment is merely an example for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately changing the above-described embodiment without departing from the spirit thereof.

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor substrate 3 Insulating layer 4 Columnar conductor 10 Semiconductor pillar 20 Intermediate substrate 23 Edge region 24 Conductor hole 50 1st etching mask 52 2nd etching mask

Claims (6)

A method of manufacturing a wiring board comprising a semiconductor substrate, an insulating layer, and a columnar conductor,
Manufacturing an intermediate substrate comprising a bottomed hole formed in the semiconductor substrate, a semiconductor pillar standing in the bottomed hole, and an edge region of the bottomed hole lower than the semiconductor pillar by etching;
Filling the bottomed hole of the intermediate substrate with an insulating material to form the insulating layer;
Forming the insulating layer and then etching to remove the semiconductor pillar;
And a step of filling the hole formed by removing the semiconductor pillar with a conductive material to form the columnar conductor. It is a manufacturing method of the wiring board according to claim 1,
The step of manufacturing the intermediate substrate includes:
Forming a first etching mask disposed on a region of the semiconductor substrate where the semiconductor pillar is formed and having an opening in a region where the bottomed hole and the edge region are formed;
A second etching mask formed on the first etching mask, disposed on the region where the semiconductor pillar is formed and the region where the edge region is formed, and having an opening in the region where the bottomed hole is formed Forming a step;
After forming the second etching mask, anisotropic etching is performed to remove a part of the semiconductor substrate at the opening positions of the first and second etching masks, and the bottomed hole and the semiconductor pillar are formed. A column forming step to be formed;
A step of removing the second etching mask after the column forming step;
After removing the second etching mask, anisotropic etching is performed on the edge region by using the first etching mask remaining on the semiconductor substrate, so that the edge region is more than the semiconductor pillar. A step forming step to be formed low;
And a step of removing the first etching mask after the step forming step. It is a manufacturing method of the wiring board according to claim 1 or 2,
In the step of forming the insulating layer, a method of manufacturing a wiring board, wherein an upper end of the semiconductor pillar is exposed from the insulating layer when the insulating layer is formed. The method for manufacturing a wiring board according to claim 1 or 2, further comprising:
After forming the insulating layer, the surface layer of the insulating layer is removed, and an exposure step of exposing the upper end of the semiconductor pillar from the insulating layer is provided,
A method for manufacturing a wiring board, comprising performing a step of removing the semiconductor pillar after the exposing step. It is a manufacturing method of the wiring board according to claim 4,
In the exposing step, the upper end of the semiconductor pillar is exposed from the insulating layer by etch back. A method of manufacturing a wiring board according to any one of claims 1 to 5,
In the step of removing the semiconductor pillar, any one of plasma etching, gas etching, and wet etching is performed.

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