JP2016154213A - Semiconductor light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-definition semiconductor light-emitting device.SOLUTION: A semiconductor light-emitting device 110 includes: a first semiconductor layer 11 of a first conductivity type; a second semiconductor layer 12 of a second conductivity type; a third semiconductor layer 13 provided between the first semiconductor layer and the second semiconductor layer; and a first transistor 20. The first transistor includes a first gate electrode G1 and a first amorphous semiconductor layer. The first amorphous semiconductor layer overlaps with the first gate electrode in a first direction from the first semiconductor layer toward the second semiconductor layer. The first gate electrode overlaps with the second semiconductor layer in the first direction.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  In recent years, the market for micro-displays for enlarged projection applications such as head-mounted displays, head-up displays, AR (Augmented Reality) glasses, and projectors is growing. Development of semiconductor devices aimed at improving the performance of microdisplays is underway. There is a semiconductor light emitting device in which an arrayed LED (Light Emitting Diode) and a thin film transistor (TFT) are arranged to drive an active matrix. In such a semiconductor light emitting device, high definition is desired.

U.S. Pat. No. 8441018

  Embodiments of the present invention provide a high-definition semiconductor light emitting device.

  According to an embodiment of the present invention, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and between the first semiconductor layer and the second semiconductor layer. A third semiconductor layer provided on the first and a first transistor. The first transistor includes a first gate electrode and a first amorphous semiconductor layer. The first amorphous semiconductor layer overlaps the first gate electrode in a first direction from the first semiconductor layer toward the second semiconductor layer. The first gate electrode overlaps the second semiconductor layer in the first direction.

1 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a first embodiment. 1 is an equivalent circuit diagram illustrating a semiconductor light emitting device according to a first embodiment. FIG. 5 is a schematic partial enlarged view illustrating another semiconductor light emitting device according to the first embodiment. FIG. 6 is a schematic perspective plan view illustrating a semiconductor light emitting device according to a second embodiment. FIG. 5 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a second embodiment. FIG. 6 is an equivalent circuit diagram illustrating a semiconductor light emitting device according to a third embodiment. FIG. 7A to FIG. 7C are timing charts illustrating the light emission time control according to the third embodiment. It is a graph which illustrates the characteristic of the semiconductor light-emitting device concerning 3rd Embodiment. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a fourth embodiment. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a fifth embodiment. FIG. 10 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a sixth embodiment. FIG. 10 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to a seventh embodiment. FIG. 10 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to an eighth embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the semiconductor light emitting device according to the first embodiment.
As illustrated in FIG. 1, the semiconductor light emitting device 110 according to the embodiment includes a first light emitting region 10 and a first transistor 20.

  The first light emitting region 10 includes a first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13. The first semiconductor layer 11 is the first conductivity type. The second semiconductor layer 12 is of the second conductivity type. The third semiconductor layer 13 is a light emitting layer. The third semiconductor layer 13 is provided between the first semiconductor layer 11 and the second semiconductor layer 12. The third semiconductor layer 13 emits the emitted light L1.

  The first conductivity type is, for example, n-type. The second conductivity type is, for example, a p-type. The first conductivity type may be p-type and the second conductivity type may be n-type. In the embodiment, a case where the first conductivity type is n-type and the second conductivity type is p-type is illustrated.

  The first transistor 20 is, for example, a TFT (Thin Film Transistor). The first transistor 20 includes a first gate electrode G 1, a first source electrode S 1, a first drain electrode D 1, and a first amorphous semiconductor layer 21. The first amorphous semiconductor layer 21 includes, for example, an oxide semiconductor. In this case, the first amorphous semiconductor layer 21 is the first conductivity type (n-type). Note that an amorphous semiconductor is an amorphous semiconductor having a particle size of, for example, 10 nanometers (nm) or less. Unlike a polycrystalline semiconductor, an amorphous semiconductor does not have a clear crystal grain boundary, and thus has an advantage of excellent uniformity of TFT characteristics.

  In the embodiment, the first amorphous semiconductor layer 21 overlaps the first gate electrode G1 in the first direction. The first gate electrode G1 is provided on the second semiconductor layer 12 in the first direction. The first direction is, for example, the Z-axis direction. The Z-axis direction is a direction from the first semiconductor layer 11 toward the second semiconductor layer 12 (stacking direction). One direction orthogonal to the Z-axis direction is taken as the X-axis direction. One direction orthogonal to the Z-axis direction and the X-axis direction is taken as a Y-axis direction. The second direction is a direction that intersects the first direction. The second direction is, for example, the X-axis direction. Note that “overlap” means a state in which at least part of the images overlap when projected onto a plane orthogonal to the Z-axis direction. The phrase “provided on” includes not only a state of being provided in direct contact but also a state of being provided via an inclusion.

  The semiconductor light emitting device 110 further includes a support substrate (first layer) 40, a first electrode e1, and a second electrode e2. The support substrate 40 is, for example, conductive. The first electrode e1 is, for example, an n electrode. The second electrode e2 is, for example, a p electrode.

  The first semiconductor layer 11 includes a first region r1 and a second region r2. The second region r2 is aligned with the first region r1 in the X-axis direction. The second semiconductor layer 12 is provided between the second region r2 and the support substrate 40. The third semiconductor layer 13 is provided between the second region r2 and the second semiconductor layer 12.

  The first electrode e1 is provided between the first region r1 and the support substrate 40. The first electrode e1 is electrically connected to the first region r1. The second electrode e2 is electrically connected to the second semiconductor layer 12. Note that the state of being electrically connected includes not only a direct contact state but also a state in which another conductive member or the like is interposed therebetween.

  The first light emitting region 10, the first electrode e1, and the second electrode e2 correspond to LEDs.

  Here, there is a reference example of a semiconductor light emitting device in which LEDs and TFTs are arranged side by side in the X axis direction. In such an arrangement, if the pixel size is reduced and the resolution is increased, a sufficient aperture ratio cannot be ensured and the luminance is lowered. Here, the “aperture ratio” means the ratio of the light emitting area (LED) to the pixel area per pixel. That is, the region where the TFT is arranged is a non-light emitting region. For this reason, an aperture ratio is reduced.

  In contrast, in the embodiment, the TFT is disposed on the LED in the Z-axis direction. That is, the LED and the TFT overlap in the Z-axis direction. For this reason, a sufficient aperture ratio can be secured even if the definition is increased. Thereby, the luminance can be improved.

  Furthermore, in the above reference example, polycrystalline silicon (polysilicon) is used as the semiconductor layer of the TFT. This polycrystalline silicon has a larger particle size than amorphous, and it is difficult to ensure uniformity of TFT characteristics. In particular, when the pixels are made higher in definition and the size of the TFT semiconductor layer is reduced, the influence of variation in characteristics becomes more serious.

  On the other hand, in the embodiment, amorphous is used as the semiconductor layer of the TFT. For this reason, the uniformity of TFT characteristics can be improved as compared with polycrystalline silicon. Uniform display performance can be obtained even if the pixels are made high definition.

  Further, the semiconductor light emitting device 110 includes an insulating layer 30, a protective metal layer (barrier metal) 50, a bonding metal layer (bonding metal) 60, and a back electrode 70.

  The insulating layer 30 includes a planarization layer 31, an undercoat layer 32, a gate insulating layer 33, an etching protection layer 34, and a passivation layer 35. The planarization layer 31 is provided on the first electrode e1 and the second electrode e2. The undercoat layer 32 is provided on the planarizing layer 31. The gate insulating layer 33 is provided on the undercoat layer 32 and on the first gate electrode G1. The etching protection layer 34 is provided on the gate insulating layer 33 and on the first amorphous semiconductor layer 21. The passivation layer 35 is provided on the etching protection layer 34.

  The barrier metal 50 is provided between the passivation layer 35 and the bonding metal 60. The barrier metal 50 is provided on the passivation layer 35. For example, the barrier metal 50 is in contact with the passivation layer 35.

  The bonding metal 60 is provided between the barrier metal 50 and the support substrate 40. The bonding metal 60 is provided on the barrier metal 50. For example, the bonding metal 60 is in contact with the barrier metal 50.

  The support substrate 40 is provided on the bonding metal 60. The support substrate 40 includes a first surface 41 and a second surface 42 provided on the side opposite to the first surface 41. The first surface 41 is electrically connected to the bonding metal 60. For example, the first surface 41 is in contact with the bonding metal 60. The second surface 42 is electrically connected to the back electrode 70. The second surface 42 is in contact with the back electrode 70, for example.

  That is, the barrier metal 50 is provided on the first transistor 20 via the insulating layer 30. The bonding metal 60 is provided on the barrier metal 50. The support substrate 40 is provided on the bonding metal 60. The back electrode 70 is provided on the support substrate 40.

  Next, a specific example of the semiconductor light emitting device 110 according to the embodiment will be described.

  The first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 include, for example, a nitride semiconductor.

  For the first electrode e1, a material capable of obtaining a good contact with the first semiconductor layer 11 is used. As the first electrode e1, for example, a laminated film of Al / Ni / Au is used. The laminated film is laminated in the order of Al / Ni / Au from the first semiconductor layer 11 side. The thickness of this laminated film is, for example, not less than 250 nm and not more than 350 nm.

  A material that can efficiently reflect the emitted light emitted from the third semiconductor layer 13 is used for the second electrode e2. As the second electrode e2, for example, a laminated film of Ag / Pt is used. The stacked films are stacked in the order of Ag / Pt from the second semiconductor layer 12 side. The thickness of this laminated film is, for example, not less than 150 nm and not more than 250 nm.

  The first transistor 20 (TFT) is provided on the second electrode e2.

  A planarizing layer 31 and an undercoat layer 32 are provided on the second electrode e2. For each of the planarization layer 31 and the undercoat layer 32, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a laminated film thereof can be used.

  Here, an oxide semiconductor is preferably used for the first amorphous semiconductor layer 21. By using an oxide semiconductor, a TFT can be formed at a relatively low temperature. For example, the maximum process temperature can be 400 ° C. or lower (preferably 300 ° C. or lower). Thereby, the performance degradation of LED by a TFT preparation process can be suppressed. For example, it is possible to suppress a decrease in reflectivity due to oxidation of the second electrode e2, which is a reflective electrode containing Ag.

  When an oxide semiconductor is used for the first amorphous semiconductor layer 21, for example, aluminum oxide is preferably used as the undercoat layer 32. Aluminum oxide functions as a hydrogen barrier film. In other words, hydrogen generated from the oxide semiconductor of the first amorphous semiconductor layer 21 can be prevented from entering the nitride semiconductor layer (for example, p-GaN layer) of the first light emitting region 10. When hydrogen penetrates into the nitride semiconductor layer, the acceptor (Mg) is deactivated, causing an increase in resistance. Such a resistance increase can be effectively suppressed by using a hydrogen barrier film such as aluminum oxide. Thereby, the performance degradation of LED can be suppressed.

  A first gate electrode G 1 is provided on the undercoat layer 32. For example, a DC magnetron sputtering method is used to form the first gate electrode G1. In this case, it is carried out under an Ar atmosphere. For example, W, Mo, Ta, Ti, Al, AlNd, Cu, ITO, IZO, or the like is used for the first gate electrode G1. A DC reactive magnetron sputtering method may be used to form the first gate electrode G1.

  A gate insulating layer 33 is provided on the first gate electrode G1. For the gate insulating layer 33, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a stacked film thereof can be used.

  The first amorphous semiconductor layer 21 is provided on the gate insulating layer 33. For example, a DC reactive magnetron sputtering method is used to form the first amorphous semiconductor layer 21. The first amorphous semiconductor layer 21 preferably contains an oxide of at least one of In, Ga, and Zn. For example, InGaZnO (IGZO) is used for the first amorphous semiconductor layer 21. For the first amorphous semiconductor layer 21, InZnO, InGaO, InSnZnO, InSnGaZnO, or InSnO may be used.

  An etching protection layer 34 is provided on the first amorphous semiconductor layer 21. The first amorphous semiconductor layer 21 provided with the etching protection layer 34 is subjected to a heat treatment at about 200 ° C. to 500 ° C. For the etching protective layer 34, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a stacked structure thereof can be used. As an atmosphere for the heat treatment, an inert atmosphere such as nitrogen, a mixed atmosphere containing oxygen, hydrogen, or water vapor may be used.

  A part of the etching protection layer 34 and the gate insulating layer 33 is opened, and the first source electrode S1 and the first drain electrode D1 are provided. For the first source electrode S1 and the first drain electrode D1, for example, any of Ti, Mo, Al, Cu, Ta, W, TiN, TaN, MoN, ITO, IZO, and InGaZnO is used. For the first source electrode S1 and the first drain electrode D1, a laminated structure of these alloys or films of these materials may be used.

  The first transistor 20 and the second electrode e2 are electrically connected. In this way, the first transistor 20 is provided on the second electrode e2. Thereby, the function of the pixel circuit can be provided without reducing the aperture ratio. As a result, high definition can be achieved.

  Next, a passivation layer 35 is provided on the first transistor 20. For the passivation layer 35, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a stacked structure thereof can be used.

Here, it is preferable that hydrogen can be prevented from entering the nitride semiconductor layer (p-GaN layer) of the first light emitting region 10. Therefore, the hydrogen atom concentration of the first amorphous semiconductor layer 21, ^{10 18} / cm ³ or more, ^{10 22} / cm ³ or less, more preferably ^{10 20} / cm ³ or less. Thereby, performance deterioration of LED can be suppressed in combination with the above-described hydrogen barrier film.

  In the manufacturing process of the first transistor 20, for example, a planarization process may be performed before the formation of the first amorphous semiconductor layer 21. As a planarization method, for example, chemical mechanical polishing, a coating insulating film (for example, SOG: Spin On Glass), reflow using BPSG (Boron Phosphorus Silicon Glass) or PSG (Phosphorus Silicon Glass) can be used. . In this example, the structure of the first transistor 20 has been described as a structure in which the first amorphous semiconductor layer 21 is disposed between the first gate electrode G1 and the support substrate 40. The structure of the first transistor 20 may be a structure in which the first gate electrode G <b> 1 is disposed between the first amorphous semiconductor layer 21 and the support substrate 40.

  In this example, the semiconductor light emitting device 110 includes a support substrate 40 that is electrically connected to the first transistor 20. Specifically, the barrier metal 50 and the bonding metal 60 are provided on the passivation layer 35. The bonding metal 60 is made of a material that can obtain good connection with the support substrate 40. As the bonding metal 60, for example, a laminated film of Ti / Au is used. The laminated film is laminated in the order of Ti / Au from the side of the passivation layer 35. The thickness of this laminated film is, for example, not less than 750 nm and not more than 850 nm.

  The support substrate 40 is bonded to the bonding metal 60. The support substrate 40 includes at least a conductive material. The material of the support substrate 40 is not particularly limited. As the support substrate 40, for example, a semiconductor substrate such as Si or Ge, a metal plate such as CuW or Cu, or a thick film plating layer is used. Further, the entire substrate does not need to have conductivity, and may be a resin having metal wiring.

  In the embodiment, Si is used as an example of the support substrate 40. The support substrate 40 is bonded to the bonding metal 60 via, for example, solder made of AuSu alloy. A back electrode 70 is provided on the support substrate 40.

Moreover, the support substrate 40 is excellent in heat dissipation and thermal conductivity. For this reason, deterioration due to heat generation of the light emitting element and the transistor due to energization can be suppressed.
For example, the first semiconductor layer 11 is provided on a growth substrate (not shown), the third semiconductor layer 13 is provided on the first semiconductor layer 11, and the second semiconductor layer is provided on the third semiconductor layer 13. 12 is provided. After these semiconductor layers are bonded to the support substrate 40, for example, the growth substrate is removed. Sapphire, silicon (Si), or the like is used for the growth substrate. For example, a metal organic chemical vapor deposition method is used for forming the semiconductor layer.

  For example, when a sapphire substrate is used as the growth substrate, for example, from the side of the growth substrate (not shown) with respect to the first light emitting region 10, for example, a third harmonic (355 nm) or quadruple of a YVO 4 solid-state laser. Harmonic (266 nm) laser light is irradiated. The laser light has a wavelength shorter than the forbidden bandwidth wavelength based on the forbidden bandwidth of GaN in the GaN buffer layer (for example, a non-doped GaN buffer layer). That is, the laser light has an energy higher than the forbidden band width of GaN. This laser light is efficiently absorbed in a region on the single crystal AlN buffer layer side of the GaN buffer layer (non-doped GaN buffer layer). As a result, the GaN on the single crystal AlN buffer layer side of the GaN buffer layer is decomposed by heat generation. When a Si substrate is used as a growth substrate, the growth substrate is removed by grinding to a certain thickness, not by laser light irradiation, and then removing the remaining Si substrate by etching.

  The first amorphous semiconductor layer 21 includes a third region r3, a fourth region r4, and a fifth region r5. The fourth region r4 is aligned with the third region r3 in the X-axis direction. In the third region r3, for example, the first source electrode S1 (one end of the first transistor 20) is provided. For example, a first drain electrode D1 (the other end of the first transistor 20) is provided in the fourth region r4. The fifth region r5 is provided between the third region r3 and the fourth region r4. The fifth region r5 overlaps the first gate electrode G1 in the Z-axis direction.

FIG. 2 is an equivalent circuit diagram illustrating the semiconductor light emitting device according to the first embodiment.
As shown in FIG. 2, the second electrode e2 is electrically connected to the high potential end PVDD. The first electrode e1 is electrically connected to the first drain electrode D1 (fourth region r4). The first source electrode S1 (third region r3) is electrically connected to the low potential end PVSS. As the low potential end PVSS, for example, a conductive support substrate 40 can be used. The first source electrode S1 is electrically connected to the support substrate 40, for example. That is, the potential of the support substrate 40 can be used as a common potential (ground potential). Thereby, a potential drop can be suppressed and a uniform display can be obtained.

  The semiconductor light emitting device 110 can further include a second transistor 22 (see FIG. 4). The second transistor 22 is electrically connected to the first gate electrode G1. The second transistor 22 is a switching TFT. That is, the second transistor 22 switches on / off the gate voltage Vgs applied to the first gate electrode G1, and controls the drain current Ids flowing through the first transistor 20. The first transistor 20 is a driving TFT.

FIG. 3 is a schematic partial enlarged view illustrating another semiconductor light emitting device according to the first embodiment.
In the embodiment, the first semiconductor layer 11 includes a main surface 11 a provided on the side opposite to the third semiconductor layer 13. A plurality of convex portions 11p may be provided on the main surface 11a. For example, the maximum width ΔW along the X-axis direction of the protrusion 11 p is longer than the peak wavelength in the first semiconductor layer 11 of the emitted light emitted from the third semiconductor layer 13. Thereby, the emitted light at the interface between the first semiconductor layer 11 and the outside can be regarded as Lambertian reflection, and the light extraction efficiency can be further increased. Here, the peak wavelength is the wavelength of light having the highest intensity among the emitted light emitted from the third semiconductor layer 13. The peak wavelength is a wavelength corresponding to the peak value of the spectrum distribution of the emitted light. In the case of a spectrum having two or more peak values that are not noise levels, the wavelength of either peak value may be selected.

  Thus, according to the embodiment, a sufficient aperture ratio can be ensured even if the definition is increased. Thereby, the luminance can be improved. Thereby, a high-definition semiconductor light-emitting device can be provided.

(Second Embodiment)
FIG. 4 is a schematic perspective plan view illustrating the semiconductor light emitting device according to the second embodiment.
FIG. 5 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the second embodiment.
FIG. 5 is a diagram illustrating an A1-A2 cross section of FIG. 4.

  In order to make the drawing easier to see, in the perspective plan view of FIG. 4, some of the components shown in the sectional view of FIG. 5 are omitted.

  In the embodiment, the first source electrode S1 is electrically connected to the second electrode e2. The first drain electrode D <b> 1 is electrically connected to the support substrate 40 through the barrier metal 50 and the bonding metal 60.

  The first region r1 is arranged around the second region r2 when projected onto a plane perpendicular to the Z-axis direction. The first electrode e1 overlaps a part of the first region r1 in the Z-axis direction. That is, the first electrode e1 surrounds the second electrode e2 and is arranged in a mesh shape. A region surrounded by the first electrode e1 corresponds to one pixel Px1. By disposing the first electrode e1 in a mesh shape, it is possible to suppress a drop in the common potential of the first transistor 20.

  The semiconductor light emitting device 111 according to the embodiment further includes a region 80, a first wiring 23, and a second wiring 24. The first wiring 23 is, for example, a signal line for the first transistor 20. The second wiring 24 is, for example, a control line for the first transistor 20. For example, a light reflective metal material is used for each of the first wiring 23 and the second wiring 24.

  The region 80 is provided between the first electrode e1 and the second electrode e2 in the X-axis direction. The region 80 is an interelectrode insulating layer such as silicon oxide. The first wiring 23 is provided between the first electrode e1 and the support substrate 40 in the Z-axis direction. The second wiring 24 is provided between the first electrode e1 and the support substrate 40 in the Z-axis direction. The first wiring 23 and the second wiring 24 intersect with each other and are provided in a mesh shape. The first wiring 23 overlaps the region 80 in the Z-axis direction. The second wiring 24 overlaps the region 80 in the Z-axis direction.

  That is, in the embodiment, the TFT wiring is arranged between the p-electrode arrays of the pixel Px1. Thereby, the leaked light L2 to the TFT side is reflected by the first wiring 23 (and the second wiring 24) to be reflected light L3. Thereby, the leakage light L2 can be reduced. Thereby, light leakage and light deterioration of the TFT can be suppressed. Moreover, the light extraction efficiency of the LED in the direction of the emitted light L1 can be increased. Thereby, crosstalk between pixels can be suppressed.

(Third embodiment)
FIG. 6 is an equivalent circuit diagram illustrating a semiconductor light emitting device according to the third embodiment.
The semiconductor light emitting device 111 a according to the embodiment includes a first transistor 20, a second transistor 22, and a third transistor 25. The first transistor 20 is a driving TFT. The second transistor 22 is a switching TFT. The third transistor 25 is a light emission time control (duty control) TFT.

  As shown in FIG. 1 described above, the first amorphous semiconductor layer 21 includes a third region r3, a fourth region r4, and a fifth region r5. The fourth region r4 is aligned with the third region r3 in the X-axis direction. In the third region r3, for example, the first source electrode S1 (one end of the first transistor 20) is provided. For example, a first drain electrode D1 (the other end of the first transistor 20) is provided in the fourth region r4. The fifth region r5 is provided between the third region r3 and the fourth region r4. The fifth region r5 overlaps the first gate electrode G1 in the Z-axis direction.

  In this example, the first gate electrode G1 is electrically connected to the source electrode of the second transistor 22. In the second transistor 22, the control line cn1 is connected to the gate electrode, and the signal line sg1 is connected to the drain electrode. The third region r3 (first source electrode S1) is electrically connected to the second electrode e2. The fourth region r4 (first drain electrode D1) is electrically connected to the third transistor 25. In the third transistor 25, the control line cn2 is connected to the gate electrode. The third transistor 25 has a source electrode connected to the first transistor 20 and a drain electrode connected to the high potential terminal PVDD. In this example, the first electrode e1 (first semiconductor layer 11) side is a low potential end PVSS.

FIG. 7A to FIG. 7C are timing charts illustrating the light emission time control according to the third embodiment.
FIG. 7A is a timing chart of the control line cn1 connected to the second transistor 22. FIG.
FIG. 7B is a timing chart of the control line cn2 connected to the third transistor 25 when the external quantum efficiency has a high current density.

  FIG. 7C is a timing chart of the control line cn2 connected to the third transistor 25 when the luminance is low and the current density is low and the external quantum efficiency is reduced.

  In FIG. 7A, T represents one cycle. When the current density is small and the external quantum efficiency is lowered, as shown in FIG. 7B, the duty ratio is lowered to increase the current density to increase the external quantum efficiency, and low luminance is realized with high efficiency. . In order to suppress a decrease in light emission efficiency at low current density, low luminance is realized by light emission time control.

FIG. 8 is a graph illustrating characteristics of the semiconductor light emitting device according to the third embodiment.
In the figure, the horizontal axis i represents current density (A / m ² ), and the vertical axis eff represents external quantum efficiency (%).

  For example, if the current density is small when the luminance is low, the external quantum efficiency of the LED is reduced. For this reason, the third transistor 25 is used to reduce the duty ratio and increase the current density i1 to the current density i2. As a result, even when the luminance is low, the display can be operated with a high current density and the power consumption of the display can be reduced.

(Fourth embodiment)
FIG. 9 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the fourth embodiment.
In the above-described embodiment, the structure of one pixel is illustrated, but in the present embodiment, the structure of a plurality of pixels is illustrated.

  The semiconductor light emitting device 112 according to the embodiment includes a first pixel Px1 and a second pixel Px2. The structure of the first pixel Px1 is the same as that of the semiconductor light emitting device 110 shown in FIG. Both the first pixel Px1 and the second pixel Px2 are provided on the first semiconductor layer 11. That is, the first semiconductor layer 11 is continuously provided in the X-axis direction.

The basic structure of the second pixel Px2 is the same as that of the first pixel Px1. The second pixel Px2 includes a second light emitting region 10a and a fourth transistor 26. The second light emitting region 10 a includes a first semiconductor layer 11, a fourth semiconductor layer 14, and a fifth semiconductor layer 15. The fourth semiconductor layer 14 is, for example, the second conductivity type (p-type). The fifth semiconductor layer 15 is provided between the first semiconductor layer 11 and the fourth semiconductor layer 14 and is located on the first semiconductor layer 11. The fifth semiconductor layer 15 is a light emitting layer.
The fourth transistor 26 includes a second gate electrode G 2 and a second amorphous semiconductor layer 27. The second amorphous semiconductor layer 27 overlaps with the second gate electrode G2 in the Z-axis direction. The second gate electrode G2 is provided on the fourth semiconductor layer 14 in the Z-axis direction.

  Thus, according to the embodiment, a common semiconductor layer (first semiconductor layer 11) is used for a plurality of pixels. For this reason, the first semiconductor layer 11 can be used for the common potential of the TFT. Thereby, in addition to high definition, the fall of a common potential can be suppressed.

(Fifth embodiment)
FIG. 10 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the fifth embodiment.
In the fourth embodiment, a common semiconductor layer is used for a plurality of pixels, but in this embodiment, a semiconductor layer separated for each pixel is used.

  The semiconductor light emitting device 113 according to the embodiment includes a first pixel Px1 and a second pixel Px2. The structure of the first pixel Px1 is the same as that of the semiconductor light emitting device 110 shown in FIG. The first pixel Px1 includes a first gate electrode G1. The first gate electrode G1 is provided on the first semiconductor layer 11. The second pixel Px2 includes a second gate electrode G2. The second gate electrode G2 is provided on the sixth semiconductor layer 16. The sixth semiconductor layer 16 is separated from the first semiconductor layer 11. That is, the semiconductor layer is provided in a state where the semiconductor layer is separated in the X-axis direction for a plurality of pixels.

The basic structure of the second pixel Px2 is the same as that of the first pixel Px1. The second pixel Px2 includes a third light emitting region 10b and a fourth transistor 26. The third light emitting region 10 b includes a sixth semiconductor layer 16, a seventh semiconductor layer 17, and an eighth semiconductor layer 18. The sixth semiconductor layer 16 is, for example, the first conductivity type (n-type). The seventh semiconductor layer 17 is, for example, the second conductivity type (p-type). The eighth semiconductor layer 18 is provided between the sixth semiconductor layer 16 and the seventh semiconductor layer 17 and is located on the sixth semiconductor layer 16. The eighth semiconductor layer 18 is a light emitting layer.
The fourth transistor 26 includes a second gate electrode G 2 and a second amorphous semiconductor layer 27. The second amorphous semiconductor layer 27 overlaps with the second gate electrode G2 in the Z-axis direction. The second gate electrode G2 is provided on the seventh semiconductor layer 17 in the Z-axis direction.

  Thus, according to the embodiment, the semiconductor layers (the first semiconductor layer 11 and the sixth semiconductor layer 16) separated from each other for the plurality of pixels are used. Thereby, in addition to high definition, light leakage to the peripheral pixels of the light emitting pixels can be suppressed, and crosstalk between the pixels can be suppressed.

(Sixth embodiment)
FIG. 11 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the sixth embodiment.
The semiconductor light emitting device 114 according to the embodiment includes a pixel circuit 101 and a peripheral circuit 102. The pixel circuit 101 includes a first pixel Px1 and a second pixel Px2. The structure of the first pixel Px1 and the second pixel Px2 is the same as the structure of FIG.

  The peripheral circuit 102 includes a fifth transistor 28 for the peripheral circuit. The fifth transistor 28 is a TFT like the other transistors. The fifth transistor 28 is provided on the first electrode e1a and the second electrode e2a. That is, the peripheral circuit 102 is not necessarily provided with an electrode. On the other hand, in the present embodiment, the fifth transistor 28 is provided on the electrode while leaving the light reflective electrode. Thereby, in addition to high definition, light shielding to TFT (5th transistor 28) can be performed.

  The first electrode e1a of the peripheral circuit 102 is electrically connected to the IC chip 103 through a wiring. Thereby, it can be used as a display.

(Seventh embodiment)
FIG. 12 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the seventh embodiment.
Similar to the sixth embodiment, the semiconductor light emitting device 115 according to the embodiment includes a first pixel Px1 and a second pixel Px2. The first pixel Px1 further includes a first phosphor layer 121, and the second pixel Px2 further includes a second phosphor layer 122. Coloring is realized by these phosphor layers.

  The first semiconductor layer 11 is provided between the third semiconductor layer 13 and the first phosphor layer 121 and between the fifth semiconductor layer 15 and the second phosphor layer 122. The average particle size of these phosphor layers is, for example, 50 μm or less. When making a pixel high-definition, blurring of the pixel can be reduced by reducing the particle diameter and film thickness of the phosphor to about the pixel size. For example, nanoparticle-based phosphors and quantum dots can be used. The particle diameter of these phosphors is, for example, 1 μm or less. These phosphor layers may be patterned for each pixel. The patterning is, for example, a stripe shape.

  A first color filter 131 is provided below the first phosphor layer 121. A first microlens 141 is provided below the first color filter 131. A second color filter 132 is provided below the second phosphor layer 122. A second microlens 142 is provided below the second color filter 132.

  Thus, according to the embodiment, in addition to high definition, it can be used as a full color display.

(Eighth embodiment)
FIG. 13 is a schematic cross-sectional view illustrating a semiconductor light emitting device according to the eighth embodiment.
In the semiconductor light emitting device 116 according to the embodiment, the first gate electrode G <b> 1 is disposed between the first amorphous semiconductor layer 21 and the support substrate 40. That is, the first amorphous semiconductor layer 21 may be provided between the second semiconductor layer 12 and the first gate electrode G1. The semiconductor light emitting device 116 includes an insulating layer 30. The insulating layer 30 includes a planarization layer 31, an undercoat layer 32, a gate insulating layer 33, a passivation layer 35, and a gate protective layer 36. The gate protective layer 36 is provided between the gate insulating layer 33 and the passivation layer 35.

  According to the embodiment, a high-definition semiconductor light emitting device can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element such as the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the first transistor is appropriately selected from a well-known range by those skilled in the art, and the present invention is similarly implemented. As long as the same effect can be obtained, it is included in the scope of the present invention.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting devices that can be implemented by those skilled in the art based on the semiconductor light-emitting devices described above as embodiments of the present invention are also included in the scope of the present invention as long as they include the gist of the present invention. Belonging to.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st light emission area | region, 10a ... 2nd light emission area | region, 10b ... 3rd light emission area | region, 11 ... 1st semiconductor layer, 11a ... main surface, 11p ... convex part, 12-18 ... 2nd-8th semiconductor layer, DESCRIPTION OF SYMBOLS 20 ... 1st transistor, 21 ... 1st amorphous semiconductor layer, 22 ... 2nd transistor, 23 ... 1st wiring, 24 ... 2nd wiring, 25 ... 3rd transistor, 26 ... 4th transistor, 27 ... 2nd amorphous semiconductor Layer, 28 ... fifth transistor, 30 ... insulating layer, 31 ... planarizing layer, 32 ... undercoat layer, 33 ... gate insulating layer, 34 ... etching protective layer, 35 ... passivation layer, 36 ... gate protective layer, 40 ... First layer (support substrate) 41... First surface 42. Second surface 50. Barrier metal 60. Junction metal 70. Back electrode 80 Region 110-111 Semiconductor light emitting device 111a Half Body light-emitting device, 112-115, 116 ... Semiconductor light-emitting device, D1 ... First drain electrode, G1 ... First gate electrode, G2 ... Second gate electrode, S1 ... First source electrode, L1 ... Emission light, L2 ... Leakage Light, L3 ... reflected light, PVDD ... high potential end, PVSS ... low potential end, Px1 ... first pixel, Px2 ... second pixel, cn1, cn2 ... control line, e1 ... first electrode, e2 ... second electrode, i1, i2 ... current density, r1-r5 ... first to fifth regions, sg1 ... signal line

Claims (11)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type;
A third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer;
The first transistor, comprising: a first gate electrode; and a first amorphous semiconductor layer that overlaps the first gate electrode in a first direction from the first semiconductor layer toward the second semiconductor layer. When,
With
The semiconductor light emitting device, wherein the first gate electrode overlaps the second semiconductor layer in the first direction.   The semiconductor light emitting device according to claim 1, wherein the first gate electrode is provided between the second semiconductor layer and the first amorphous semiconductor layer.   The semiconductor light-emitting device according to claim 1, wherein the first amorphous semiconductor layer is provided between the second semiconductor layer and the first gate electrode. The first layer;
A first electrode;
A second electrode;
Further comprising
The first semiconductor layer further includes a first region and a second region aligned with the first region in a second direction intersecting the first direction,
The second semiconductor layer is provided between the second region and the first layer;
The third semiconductor layer is provided between the second region and the second semiconductor layer;
The first electrode is provided between the first region and the first layer and electrically connected to the first region;
The semiconductor light emitting device according to claim 1, wherein the second electrode is provided between the second semiconductor layer and the first layer and is electrically connected to the second semiconductor layer. . The first region is arranged around the second region when projected onto a plane perpendicular to the first direction;
The semiconductor light emitting device according to claim 4, wherein the first electrode overlaps a part of the first region in the first direction. The first amorphous semiconductor layer includes a third region in which one end of the first transistor is provided, a fourth region in which the other end of the first transistor is provided alongside the third region in the second direction, A fifth region provided between the third region and the fourth region and overlapping the first gate electrode in the first direction;
The first layer is electrically conductive and electrically connected to the third region;
The semiconductor light emitting device according to claim 4, wherein the first electrode is electrically connected to the fourth region. A region provided between the first electrode and the second electrode in the second direction;
A wiring provided between the first electrode and the first layer in the first direction;
Further comprising
The semiconductor light emitting device according to claim 4, wherein the wiring overlaps the region in the first direction. A second transistor,
The semiconductor light emitting device according to claim 1, wherein the second transistor is electrically connected to the first gate electrode. A second transistor;
A third transistor;
Further comprising
The first amorphous semiconductor layer includes a third region in which one end of the first transistor is provided, a fourth region in which the other end of the first transistor is provided alongside the third region in the second direction, A fifth region provided between the third region and the fourth region and overlapping the first gate electrode in the first direction;
The first gate electrode is electrically connected to the second transistor;
The third region is electrically connected to the second electrode;
The semiconductor light emitting device according to claim 4, wherein the fourth region is electrically connected to the third transistor. A fourth transistor;
A fourth semiconductor layer of the second conductivity type;
A fifth semiconductor layer provided between the first semiconductor layer and the fourth semiconductor layer;
Further comprising
The fourth transistor includes:
A second gate electrode;
A second amorphous semiconductor layer overlapping the second gate electrode in the first direction;
Including
The semiconductor light emitting device according to claim 2, wherein the second gate electrode is provided between the fourth semiconductor layer and the second amorphous semiconductor layer. A fourth transistor;
A sixth semiconductor layer of the first conductivity type separated from the first semiconductor layer;
A seventh semiconductor layer of the second conductivity type;
An eighth semiconductor layer provided between the sixth semiconductor layer and the seventh semiconductor layer;
Further comprising
The fourth transistor includes:
A second gate electrode;
A second amorphous semiconductor layer overlapping the second gate electrode in the first direction;
Including
The semiconductor light emitting device according to claim 2, wherein the second gate electrode is provided between the seventh semiconductor layer and the second amorphous semiconductor layer.

Images