JP2016115700A - Electrode structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrode structure of semiconductor having high bond strength of an electrode and a Cu wire even after Cu wire bonding of large load and vibration, and thereby having high reliability, and is excellent in conformity with the wafer process.SOLUTION: An electrode structure provided on a semiconductor substrate includes an electrode layer, a barrier layer provided on the electrode layer, a first metal layer provided on the barrier layer, a second metal layer provided on the first metal layer, and a wire electrode bonded to the second metal layer. The first metal layer is an Ag alloy containing at least one kind of Nd:0.10-2.0 atom% and Bi:0.08-2.0 atom% as an alloy element, the second metal layer is Cu or Cu alloy, and the wire electrode is Cu or Cu alloy.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an electrode structure. The present invention relates to an electrode structure in a power semiconductor, for example.

  In recent years, insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors, power MOS type field effect transistors) have become widespread as power devices that control high power. ing.

  A general IGBT configuration will be described with reference to FIG. A collector electrode 1 is connected to the p-type collector layer 2. The collector electrode 1 is fixed and connected to a circuit board or the like not shown in FIG. 1 via a solder layer. An n-type base layer 3 is formed on the collector layer 2. A p-type body region 4 is formed above the n-type base layer 3, and an n-type emitter layer 5 is formed therein. A region of the n-type base layer 3 between the two emitter layers 5 is a channel region, and a gate insulating film 6, a gate electrode 7, and an interlayer insulating film 8 are formed on the channel region. An emitter electrode is formed as an electrode layer 9 on the emitter layer 5. In general, these n-type region and p-type region include P, B, or B at a dose amount, acceleration voltage, or implantation angle determined for each region, whether P or B is originally contained in a substrate made of Si or the like. After ion implantation, activation heat treatment is performed at a temperature and time determined for each region.

  In a p-type IGBT having a channel region, a positive bias is applied to the gate electrode 7 in parallel with applying a negative bias to the emitter electrode as the electrode layer 9 and a positive bias to the collector electrode 1 as the back electrode. As a result, an inversion layer is formed in the channel region, and the emitter layer 5 and the n-type base layer 3 are connected by the inversion layer, and a current flows. This current flows through the collector electrode 1.

  Conventionally, Al or Au has been used as a metal bonding wire for taking out current from an electrode on a chip to the outside. However, power semiconductors such as IGBTs have increased in power density year by year as their applications expand, and the current value handled with this has also increased, so the heat generated in the bonding wire itself and the bonding wire-chip connection is ignored. I can't. Therefore, recently, as a countermeasure against the heat generation, a method of connecting to an external terminal using a wire or ribbon made of Cu or Cu alloy having high conductivity and high thermal conductivity has been proposed. Hereinafter, bonding of the wire made of Cu or Cu alloy is referred to as “Cu wire bonding”, and the wire made of Cu or Cu alloy used for the bonding is referred to as “Cu wire”.

  In general, bonding of a metal bonding wire is performed by applying a load to the metal bonding wire and the electrode and applying pressure to vibrate and applying ultrasonic waves together with heat to form a metal bond to be electrically connected. Since the Cu wire has a higher hardness than conventional bonding wires such as Al and Au, there is a problem that when the Cu wire is joined, the element is broken due to a strong load and vibration, that is, the substrate is easily cracked. In addition, when the bonding strength between the bonding wire and the electrode is insufficient, there is a problem in that the wire is disconnected at the connecting portion, resulting in an element malfunction. Therefore, there is a demand for a semiconductor electrode structure having high bonding strength between the metal bonding wire and the electrode and high bonding reliability, that is, high connection reliability.

  For example, Patent Document 1 discloses a semiconductor device including a semiconductor substrate containing SiC or GaN as a main component and a plurality of metal layers bonded on the semiconductor substrate. Specifically, the plurality of metal layers include a wiring metal layer for electrical connection with the outside in an outermost layer, and the wiring metal layer includes at least one of Cu, Al, Be, and Sb mainly composed of Ag. It is an alloy layer to which a small amount of solute element is added, and the addition amount of the solute element to Ag contained in the wiring metal layer is 0.1 at% Cu or more, 0.3 at% Al or more, 0.1 at A semiconductor device having% Be or more and 0.15 at% Sb or more is shown. That is, Patent Document 1 discloses that the outermost metal electrode for wire bonding is an Ag alloy electrode in order to increase the durability beyond the recrystallization temperature at the time of mounting.

  However, the above-mentioned patent document 1 aims to obtain a semiconductor that can operate stably without changing the resistivity of the wiring metal even at an operating temperature of 150 ° C. or higher. As a metal wire, an Au wire, a Cu wire, and an Al wire are provided. The type of the metal wire is not particularly limited. That is, Patent Document 1 does not consider securing bonding strength after bonding in view of the fact that element destruction is likely to occur during Cu wire bonding on the premise that a Cu wire is used.

  On the other hand, Patent Document 2 proposes the following semiconductor device in view of the fact that Cu is easily oxidized, and bonding using a Cu wire is likely to cause a defect, and particularly deteriorates when stored at a high temperature. . That is, a semiconductor element mounted on a substrate, an electrode pad provided on the semiconductor element, a Cu wire connecting the connection terminal provided on the substrate and the electrode pad, the semiconductor element and the Cu wire A region of the electrode pad in a range of 3 μm or less in the depth direction from the bonding surface with the Cu wire, the main component being a metal having a smaller ionization tendency than Al, A semiconductor device has been proposed in which the sulfur content in the Cu wire is 15 ppm or more and 100 ppm or less with respect to the entire Cu wire. That is, in the above-mentioned Patent Document 2, the electrode pad region connected to the Cu wire is mainly composed of a metal having a smaller ionization tendency than Al, so that corrosion due to the battery effect generated between the electrode surfaces connected to the Cu wire is prevented. Reduced, improved moisture resistance and high temperature storage. However, Patent Document 2 does not consider that the bonding strength between the Cu wire and the electrode can be reliably increased in consideration of the thermal history in the manufacturing process of the semiconductor device.

  In order to obtain a semiconductor device having high bonding strength even after the wire bonding, the material constituting the semiconductor device may exhibit high durability against heat history received in the manufacturing process of the semiconductor device, that is, excellent heat resistance. is necessary. Specifically, in the manufacturing process of the IGBT or the like, the collector layer is ion-implanted from the back surface of the substrate after the emitter electrode is formed. Next, the implanted ions are activated by performing a heat treatment at 450 ° C. or lower. Therefore, the material constituting the electrode structure is required to have durability against these heats.

  Bonding with a metal bonding wire is also required to have excellent consistency with a wafer process.

JP 2013-125922 A International Publication No. 2013/140746

  The present invention has been made paying attention to the above-described circumstances, and the purpose thereof is to provide a high bonding strength between the electrode and the Cu wire even after the Cu wire bonding with a large load and vibration, resulting in reliability. It is to provide a highly reliable semiconductor electrode structure.

  Another object of the present invention is to provide a semiconductor electrode structure excellent in consistency with a wafer process. In the present invention, “excellent in compatibility with the wafer process” means that the lamination of the Ag alloy and the barrier layer can be satisfactorily collectively etched as evaluated in Example 2 described later.

  Other objects of the present invention will become apparent from the following detailed description.

  The electrode structure of the present invention that has solved the above problems is an electrode structure provided on a semiconductor substrate, and is provided on the electrode layer, the barrier layer provided on the electrode layer, and the barrier layer. A first metal layer, a second metal layer provided on the first metal layer, and a wire electrode joined to the second metal layer, the first metal layer comprising: An alloy containing at least one of Nd: 0.10 atomic% and 2.0 atomic% and Bi: 0.08 atomic% and 2.0 atomic% as the alloy elements, The metal layer is characterized in that it is Cu or Cu alloy, and the wire electrode is Cu or Cu alloy.

  In a preferred embodiment of the present invention, the first metal layer is an Ag alloy further containing Cu in an amount of more than 0 atomic% and not more than 2.0 atomic% as an alloy element.

  In a preferred embodiment of the present invention, the second metal layer is a Cu foil or a Cu alloy foil formed by rolling or plating.

  In a preferred embodiment of the present invention, the barrier layer is any one selected from the group consisting of Mo, Mo alloy, Mo nitride, and IZO.

  In a preferred embodiment of the present invention, the electrode layer is Ti, Mo, Ni, Al, Au, or an alloy thereof.

  The present invention also includes a semiconductor device characterized by having the electrode structure.

  In the following description, the case where the electrode layer in the electrode structure is used for an emitter electrode made of Al or an Al alloy will be described as an example. However, the present invention is not limited to this, and the electrode layer is a pad of a gate electrode. The case where it is a part is also included. Hereinafter, the Al or Al alloy may be referred to as “Al-based”, and the Cu or Cu alloy may be referred to as “Cu-based”.

  ADVANTAGE OF THE INVENTION According to this invention, it can bond using a Cu wire and can provide the electrode structure which was able to raise the joint strength of a wire and an electrode. In particular, in the electrode structure of the present invention, since the Cu wire is connected to the Cu material of the same material, the connection reliability is excellent. According to the electrode structure of the present invention, the laminated structure of the electrode layer, the barrier layer, the first electrode layer, and the second electrode layer serves as a cushion during Cu wire bonding, and the Cu wire is placed on the element side. Even if it is pushed in, element destruction due to disconnection is suppressed. In addition, since the electrode structure of the present invention has a barrier layer, there is no Ag aggregation even after heat treatment at 400 ° C. for ion activation on the collector electrode side, and mutual diffusion of Ag and Al Can be prevented.

  Furthermore, the semiconductor electrode structure of the present invention is designed on the premise of bonding with an Al wire, and even in an IGBT chip that is currently used in general, on the emitter electrode formed as an electrode layer, as in the configuration of the present invention, By laminating the barrier layer, the first metal layer, and the second metal layer in this order, Cu wire bonding can be performed, and a semiconductor electrode structure with high bonding strength between the Cu wire and the electrode can be easily obtained. .

FIG. 1 is a schematic cross-sectional view showing a configuration of a general IGBT. FIG. 2 is a schematic cross-sectional view showing the electrode structure of the present invention. FIG. 3 is a diagram showing the relationship between the heat treatment temperature and the Ag-based reflectivity.

  The inventors of the present invention have made extensive studies to solve the above problems. In particular, even after Cu wire bonding with a large load and vibration, the bonding strength between the electrode and the Cu wire is high, and as a result, earnest research was repeated to obtain a highly reliable semiconductor electrode structure. Specifically, the electrode structure has been intensively studied from various viewpoints such as materials, thickness, hardness, and formation methods such as plating and thin film coating.

  As a result, a barrier layer between the electrode layer and the wire electrode that is Cu or Cu alloy; a prescribed Ag alloy described later as the first metal layer; and Cu or Cu alloy as the second metal layer; It was found that an electrode structure with high bonding strength can be obtained by forming in this order and bonding a wire electrode made of Cu or Cu alloy to the second metal layer. More preferably, if a barrier layer that is recommended is used, the durability against the thermal history received in the manufacturing process is further increased, and the bonding strength can be further increased. In the manufacturing process, the first metal layer and the barrier layer can be collectively etched.

  Hereinafter, one embodiment of the electrode structure of the present invention will be described with reference to the drawings.

  FIG. 2 is a cross-sectional view schematically showing the electrode structure of the present invention. As shown in FIG. 2, the electrode structure of the present invention is provided on a semiconductor substrate 10, and includes an electrode layer 9, a barrier layer 11, a first metal layer 12, a second metal layer 13, and a wire electrode. 14. The electrode structure of the present invention can be applied to a substrate using silicon as the semiconductor substrate 10, and semiconductor materials such as SiC, GaN, and diamond can also be suitably applied as the substrate. The kind of semiconductor element to which the electrode structure of the present invention is applicable is not particularly limited. For example, the electrode structure of the present invention can be suitably applied to a switching element such as IGBT or MOSFET, or a rectifying element such as a diode.

  When the semiconductor element is, for example, an IGBT having a vertical structure, the semiconductor substrate 10 shown in FIG. 2 is formed with the collector layer 2 to the interlayer insulating film 8 shown in FIG. A collector electrode not shown in FIG. 2 is formed on the surface of the semiconductor substrate 10 of FIG. 2 opposite to the electrode layer 9. The collector electrode is directly connected to the semiconductor package and taken out to the outside. An emitter electrode is formed as the electrode layer 9 in FIG. The emitter electrode is connected to a lead terminal by a wire electrode 14.

  Hereinafter, the electrode structure on the side connected by the wire, specifically, each layer from the electrode layer 9 to the wire electrode 14 in FIG. 2 will be described in detail.

Electrode Layer An electrode layer 9 is formed on the semiconductor substrate 10. As the electrode layer 9, for example, Ti, Mo, Ni, Al, Au; or alloys of these metal elements, that is, alloys based on Ti, Mo, Ni, Al, or Au; or these metal elements Can be used.

  When the alloy is used as the electrode layer 9, the alloy element is at least one selected from the group X consisting of Ta, Nb, Re, Zr, W, Mo, V, Hf, Ti, Cr, Pt and rare earth elements. An X group element may be used. These are elements that contribute to improving heat resistance at high temperatures. By containing the X group element, excellent heat resistance is exhibited even when a thermal history of about 400 ° C. is received in the semiconductor manufacturing process.

  The rare earth elements may be added alone or in combination of two or more. Here, the rare earth element means a lanthanoid element, that is, an element group obtained by adding scandium and yttrium to a total of 15 elements from La with atomic number 57 to Lu with atomic number 71 in the periodic table.

  The total content of the group X elements is preferably 0.1 to 5 atomic%.

  When the alloy is used as the electrode layer 9, the alloy element may contain at least one element of Ni and Co and at least one element of Ge and Cu. In addition to containing these elements together with the X group element described above, these elements can be used alone without using the X group element.

  Further, in order to prevent the metal element of the electrode layer 9 from diffusing into the semiconductor region, a barrier layer between the electrode layer 9 and the semiconductor substrate 10, not shown in FIG. May be. The barrier layer between the electrode layer and the semiconductor substrate is formed by sputtering, ion plating, electron beam evaporation, or vacuum evaporation of a metal, an alloy, or a compound such as Ti, TiN, TiW, or TaN. It is obtained by doing.

  The thickness of the electrode layer of the present invention is preferably 1 μm or more from the viewpoint of ensuring that a large current flows and cushioning properties during wire bonding. The thickness is more preferably 2 μm or more, and further preferably 4 μm or more. On the other hand, from the viewpoint of reducing the film thickness for the purpose of forming efficiency and apparatus miniaturization, the thickness is preferably 10 μm or less, more preferably 8 μm or less, and still more preferably 5 μm or less.

Barrier layer The barrier layer 11 interposed between the electrode layer and the first metal layer has the following role. That is, for example, when the electrode layer 9 made of Al and the first metal layer 12 made of Ag alloy are directly laminated, mutual diffusion easily occurs. When interdiffusion occurs between them and an Ag compound is formed, the electrical resistance of the electrode structure increases, that is, the conductivity decreases, and a brittle interdiffusion layer is formed at the interface between the layers, so that the performance of the device deteriorates. Further, when Ag atoms diffused from the first metal layer 12 to the electrode layer 9 further diffuse into the lower semiconductor substrate 10, the semiconductor characteristics are remarkably deteriorated. By forming the barrier layer 11 between the electrode layer 9 and the first metal layer 12, the mutual diffusion can be prevented.

  As an example, the present inventors made a laminated structure of an electrode layer made of Al, the barrier layer, and a first metal layer made of an Ag alloy, and simulated a thermal history in the manufacturing process at 400 ° C. for 1 hour. After performing the heat treatment, SEM observation of the cross section in the thickness direction of the laminated structure was performed. The presence or absence of interdiffusion was confirmed by SEM-EDX (Scanning Electron Microscope-Energy Dispersive X-ray spectroscopy, energy dispersive X-ray spectroscopy). As a result, it was confirmed that the mutual diffusion of the Ag alloy and Al did not occur by providing the barrier layer.

  The barrier layer is also required to have the following characteristics. That is, since a large current flows through the electrode as described above, the barrier layer is required to have conductivity. Further, in order to easily form a pattern in the electrode manufacturing process, it is required that both the barrier layer and an Ag alloy described later can be etched. In particular, when an acid is used as the etching solution, the etching rate of the Ag alloy is very high, and therefore the barrier layer is required to be easily etched at almost the same rate as the Ag alloy.

  As a barrier layer having these characteristics, in addition to Mo, which is widely used as a barrier layer, Mo alloy, Mo nitride, IZO, Ti, Cr, Ta, W, and alloys based on these metal elements, And nitrides of the metal elements. Among these, Preferably it is either selected from the group which consists of Mo, Mo alloy, Mo nitride, and IZO, More preferably, any one selected from the group which consists of Mo alloy, Mo nitride, and IZO It is. Hereinafter, the barrier layer including Mo alloy, Mo nitride, and IZO will be described.

  Examples of the Mo alloy include alloys using at least one of Nb, Ti, Ta, W, Cr, and Ni as alloy elements. For example, when the alloy element is Nb, a Mo—Nb alloy containing 5 to 15% by mass of Nb can be given.

  The Mo—Nb alloy has higher corrosion resistance than Mo, and oxidation in a humid atmosphere such as a constant temperature and humidity test is suppressed. In addition, the Mo—Nb alloy has a slower etching rate than Mo, and thus is suitable when it is necessary to adjust the etching shape in an electrode having a laminated structure.

  Next, Mo nitride will be described. Nitrogen atoms constituting Mo nitride do not become a contamination that deteriorates characteristics by creating a level in the band gap of a silicon semiconductor, like a transition metal atom. Moreover, it becomes amorphous by adding nitrogen. As a result, as described below, the formation of crystal grain boundaries serving as diffusion paths is suppressed, and diffusion is suppressed as compared with the case where Mo is used for the barrier layer. That is, when the Mo is used as a barrier layer between an Al-Si emitter electrode and an Ag alloy as the first metal layer as an electrode layer, for example, an interfacial reaction or diffusion occurs gradually as the process temperature rises. start. In particular, when the thickness of Mo is thin, there is a risk of diffusion starting from the thin portion. In the experiments so far, it has been found that when the temperature of the Al, Mo and Ag stack is gradually raised, the electrical resistance gradually increases from around 400 ° C. From this, it can be seen that interfacial reaction and diffusion between Mo and other layers are starting to occur. The diffusion starts from a grain boundary having a high diffusion rate. That is, the more the grain boundaries that serve as diffusion paths, the more likely diffusion occurs. On the other hand, it is considered that the amorphized Mo nitride is suppressed in diffusion due to the small number of crystal grain boundaries.

  IZO is an oxide represented by In—Zn—O. It is used as a transparent conductive layer and contains 30% by mass of ZnO. This IZO can be etched with phosphorous nitric acid. IZO is a material widely used as a transparent pixel electrode of a display and has high process compatibility. Furthermore, since IZO is amorphous and has no grain boundary, diffusion through the grain boundary is less likely to occur.

  In addition to IZO, ITO, that is, In—Sn—O, IGO, that is, In—Ge—O, and IWO, that is, In—W—O, are used as a transparent conductive film based on In oxide. Can be used.

  Among the barrier layers, Mo, Mo alloy, Mo nitride, and IZO can be formed by a sputtering method and can be formed as an electrode layer using the same etching solution as an Al-Si electrode or an Ag alloy that is a first metal layer, For example, an etching process using phosphorous nitric acid is possible. Therefore, etching with the upper layer Ag alloy is possible. That is, since the conventional process can be applied, it can be said that the process compatibility is high. Note that Mo alloy, Mo nitride, and IZO all have a lower etching rate than Mo. That is, when an Ag alloy and a laminate of these are collectively etched, the Ag alloy is more easily etched. However, since the size of the electrode is larger than the size of the tapered portion, it is considered that the level is not a problem even when side etching of the Ag alloy progresses.

  When the barrier layer is thin, mutual diffusion may easily occur after the heat treatment. For example, when an Al-based electrode layer is used and the barrier layer is made of metal, the barrier layer is polycrystalline and includes a grain boundary. Therefore, when heat treatment is performed at a high temperature, Ag atoms may diffuse into Al through grain boundaries. This is because the diffusion rate of Ag atoms at the grain boundary is very fast, and Ag and Al easily form a compound even at a low temperature. In order to suppress such a phenomenon and sufficiently prevent diffusion between the Al-based electrode layer and the Ag alloy as the first metal layer, the thickness of the barrier layer should be 200 nm or more. Preferably, it is 300 nm or more. On the other hand, if the barrier layer is too thick, peeling due to stress occurs or etching in the lateral direction rather than in the thickness direction becomes difficult, so that it is difficult to achieve good etching. It is as follows.

First Metal Layer Of the electrode structure in the present invention, the first metal layer is a specific Ag alloy. This Ag alloy is, for example, a bonding layer necessary to ensure electrical conduction by directly contacting the Al-based material corresponding to the terminal of the emitter electrode and the Cu-based metal layer.

  Moreover, in this invention, heat resistance can be ensured with respect to the heat history received in the manufacturing process of an electrode structure by using a specific Ag alloy as explained below.

  That is, when Ag is used for the bonding layer, the surface of Ag is easily aggregated and roughened by the heat of 400 ° C. received in the manufacturing process of the electrode structure. Ag aggregation is caused by thermal migration. When a Cu-based second electrode layer is formed on the Ag surface where aggregation occurs and the surface is roughened, voids are generated at these interfaces, resulting in a decrease in bonding strength, that is, a decrease in adhesion, and thus a reliability of bonding. Cause a decline in sex. Further, when the surface roughness of the Ag alloy is transferred to the Cu-based surface, a sufficient contact surface between the Cu wire and the Cu-based second electrode layer cannot be obtained during subsequent Cu wire bonding, resulting in a decrease in bonding strength. Also in this case, the reliability of bonding is lowered. Therefore, it is necessary to suppress the migration in the heat treatment at 300 to 400 ° C. received in the electrode manufacturing process.

  Therefore, in the present invention, an Ag alloy that can suppress the migration is used. In the case of the Ag alloy specified in the present invention, the added alloy element suppresses the surface migration of Ag due to heat, so that aggregation does not occur and flatness can be maintained. As a result, the bonding strength between the Cu alloy formed on the Ag alloy and the Ag alloy can be increased. Further, a Cu-based material formed on the Ag alloy can be obtained with a flat surface, and the bonding strength between the Cu-based material and the Cu wire can be increased. As a result, a semiconductor electrode structure having high connection reliability between the electrode and the Cu wire can be obtained.

  The Ag alloy contains at least one of Nd: 0.10 atomic% and 2.0 atomic% and Bi: 0.08 atomic% and 2.0 atomic% as alloying elements.

  Since Nd has a larger atomic radius than Ag, it has the effect of suppressing Ag diffusion by trapping vacancies. This effect is not seen when only Cu is added to Ag. In order to exert this effect, Nd is contained in an amount of 0.10 atomic% or more. The content of Nd is preferably 0.12 atomic% or more, more preferably 0.15 atomic% or more, and further preferably 0.20% or more. On the other hand, if Nd is excessively contained, the electrical resistivity is increased, so the Nd content is 2.0 atomic% or less, preferably 1.5 atomic% or less.

  Bi is an element having a large effect of suppressing the above-described migration of Ag due to heat and maintaining flatness without causing aggregation. Further, Bi and Nd can suppress the grain growth of Ag after heat treatment by addition of a small amount, and thus can suppress the abnormal grain growth of Ag that causes surface roughness. In order to exhibit this effect, Bi is contained by 0.08 atomic% or more. The Bi content is preferably 0.10 atomic% or more, more preferably 0.12 atomic% or more. On the other hand, if Bi is excessively contained, the electrical resistivity increases, so the Bi content is 2.0 atomic% or less, preferably 1.5 atomic% or less.

  Nb and Bi can be used alone or in combination. Examples of the Ag alloy of the present invention include those containing the above-mentioned alloy elements in the above-mentioned amount and comprising the balance Ag and inevitable impurities.

  The first metal layer may further contain more than 0 atomic% and not more than 2.0 atomic% of Cu as an alloy element. The Cu content is preferably 0.10 atomic% or more.

  For example, an Ag alloy containing the above amount of Nd together with the above amount of Cu has a heat history of 300 to 400 ° C. that is received in the manufacturing process of the electrode structure, as in the case of an Ag alloy containing the above amount of Nd, as shown in the examples described later. Excellent heat resistance.

  The thickness of the first metal layer should be 300 nm or more from the viewpoint of satisfactorily bonding the Al-based electrode layer and the Cu-based second metal layer and ensuring heat resistance against thermal history. Preferably, it is 500 nm or more. On the other hand, if the first metal layer is too thick, etching in the lateral direction rather than in the thickness direction is likely to proceed, and good etching becomes difficult. Therefore, the thickness of the first metal layer is preferably 1000 nm or less, more preferably 700 nm or less.

Second metal layer As the second metal layer, a Cu-based material is formed for easy connection to the following Cu wire. By providing this second metal layer, the Cu wire is connected to the homogeneous material, so that the connection reliability is excellent. Moreover, mechanical damage to the element at the time of bonding can also be prevented by using a hard Cu-based material having a high hardness as the counterpart material of the Cu wire. A Cu foil or Cu alloy foil formed by rolling or plating is preferable as the Cu-based second metal layer from the viewpoint of easy film thickening. More preferably, it is a rolled foil or plating foil with a pattern on which an electrode pattern has been applied in advance, corresponding to the transfer method. As Cu-based, in addition to Cu, Cu-0.15 atomic% Sn, Cu-0.3 atomic% Cr-0.25 atomic% Sn-0.2 atomic% Zn, which are generally distributed as Cu alloy foils, A Cu alloy such as Cu-0.03 atomic% Zr can be used.

  The thickness of the second metal layer is preferably 3 μm or more, more preferably 5 μm or more, from the viewpoint of easily connecting to the Cu wire and ensuring the bonding strength. On the other hand, since it is difficult to process the electrode pattern even if the second metal layer is too thick, the thickness of the second metal layer is preferably 35 μm or less, more preferably 15 μm or less.

  The electrode structure of the present invention is obtained by bonding a wire electrode to the Cu system. The wire electrode used for the bonding may be Cu or Cu alloy that has been used conventionally.

  According to the electrode structure of the present invention, when being subjected to Cu wire bonding, the hard Cu system is formed on the outermost surface, and the electrode layer, the barrier layer, and the first metal layer are sequentially formed from the semiconductor substrate side. Since the second metal layer forms a laminated structure, even if the Cu wire is pushed into the element side during Cu wire bonding, the laminated structure serves as a cushion, and element destruction due to disconnection is suppressed and bonding is performed. Reliability is improved.

  Hereinafter, the manufacturing process of the electrode structure of the present invention will be described with reference to FIG.

  The semiconductor substrate 10 may be a substrate generally used in a power semiconductor that can use Cu wires. For example, in addition to the Si substrate used in the following examples, a SiC substrate, a GaN substrate, a diamond substrate, and the like can be given.

  The electrode layer 9 can be obtained by a sputtering method, an ion plating method, an electron beam vapor deposition method, a vacuum vapor deposition method, or the like, but is preferably formed by a sputtering method using a sputtering target. Hereinafter, the sputtering target may be simply referred to as “target”.

  Subsequently, an electrode layer 9 is formed by etching. The etching may be performed by a general method. For example, when Al or Al—Si is applied to the electrode layer 9, wet etching using phosphorous nitric acid may be used.

  Since the barrier layer 11 is preferably formed to be relatively thinner than an Ag alloy that is a first metal layer and a Cu metal that is a second metal layer, which will be described later, for example, a sputtering method such as a DC magnetron sputtering method, vapor deposition, or the like. It is preferable to form by a method. Mo nitride can be formed by reactive sputtering.

  When Mo or Mo alloy is formed as the barrier layer 11, sputtering may be performed using a Mo alloy target having the same composition as Mo or the Mo alloy as a target. When IZO, ITO, IGO, or IWO is formed as the barrier layer 11, sputtering may be performed using an IZO target, ITO target, IGO target, or IWO target having the same composition.

  The Mo or Mo—Nb alloy has a grain boundary. As described above, these are likely to be diffused as compared with amorphous Mo nitride or the like. However, if the thickness is increased to 500 nm and the grain boundary density is reduced by controlling the formation conditions, that is, the crystal grain size is increased, diffusion can be suppressed. On the other hand, Mo nitride, IZO, and ITO are amorphous and have no grain boundary, so that Ag atoms hardly diffuse.

The conditions for forming the metal, alloy, oxide such as IZO in the sputtering method are not particularly limited, but for example, the following conditions are preferably employed.
-Substrate temperature: Room temperature to 150 ° C
Atmospheric gas: Inert gas such as Ar Gas pressure at the time of formation, for example, Ar gas pressure: 1.0 to 5.0 mTorr
・ Sputtering power: 100-2000W
-Ultimate vacuum: 1 x ^10-5 Torr or less

Mo nitride can be formed by reactive sputtering. More specifically, for example, argon gas containing, for example, 17 to 44% nitrogen gas as a sputtering gas and nitrogen gas can be formed under the following conditions.
-Substrate temperature: Room temperature to 150 ° C
-Total gas pressure during formation: 1.0 to 5.0 mTorr
・ Sputtering power: 100-2000W
-Ultimate vacuum: 1 x ^10-5 Torr or less

  For example, when Mo having a thickness of about 500 nm is formed as the barrier layer 11, if it is formed at a general gas pressure condition, for example, 2 mTorr, the stress increases and peeling easily occurs. In order to prevent this, it is recommended to use a relatively high gas pressure at which the stress is reduced for the formation of the barrier layer having the above thickness.

Next, an Ag alloy that is the first metal layer 12 is formed. Examples of the method for forming the Ag alloy include sputtering methods such as DC magnetron sputtering, vapor deposition, electrolytic plating, screen printing, and ink jet. Examples of the formation conditions in the sputtering method include using an Ag alloy target having the same composition as that of the Ag alloy, and employing the following conditions, for example.
-Substrate temperature: Room temperature to 150 ° C
Atmospheric gas: Inert gas such as Ar Gas pressure at the time of formation, for example, Ar gas pressure: 1 to 5 mTorr
・ Sputtering power: 100-2000W
-Ultimate vacuum: 1 x ^10-5 Torr or less

  Next, a photoresist is applied to the stacked layer of the barrier layer 11 and the first metal layer 12, and a resist pattern is formed by lithography. According to the laminated structure of the barrier layer and the prescribed Ag alloy recommended in the present invention, these laminated layers can be wet-etched collectively using phosphorous nitric acid. Examples of the photoresist include use of Nagase ChemteX's trade name: AC-101 at a liquid temperature of 40 ° C., for example, as phosphorous nitrate acetic acid.

  Next, the resist is stripped using a product name: TOK104 manufactured by Tokyo Ohka Kogyo Co., Ltd. as the stripping solution. Thereafter, the collector layer on the back surface of the wafer (not shown in FIG. 2) is ion-implanted, and Al is formed as a collector electrode by a sputtering method. According to the present invention, since the migration of the Ag alloy is suppressed in this heat treatment, the surface of the Ag alloy is kept smooth even after the heat treatment.

  Next, a Cu-based material that is the second metal layer 13 is formed. In addition to rolling, plating, sputtering, and vapor deposition methods, Cu-based formation includes screen printing and ink jet methods. Among these, it is preferable to form Cu foil or Cu alloy foil by rolling or plating. The plating method generally includes an electrolytic plating method, but an electroless plating method may be performed. Examples of the electroless plating method include formation of a copper film by an autocatalytic reaction; and formation of a copper film that selectively reduces copper ions in a plating bath on palladium as a catalyst or a copper base. In the electroless plating method, the film thickness tends to be thin, and therefore, the electroplating may be further performed to increase the film thickness. In addition, when applying the rolling method or the plating method, for example, a “copper foil pattern transfer method” in which a rolled copper foil or an electrolytic copper foil that has been subjected to an electrode pattern in advance is pressed and transferred onto an Ag alloy while heating is applied. can do.

  When forming a Cu system by the sputtering method or the vapor deposition method, pattern processing using lithography is necessary after the Cu system is formed. The advantage of the sputtering method or the vapor deposition method is that the thickness can be controlled in the order of nm and the uniformity is excellent. However, in the case of the sputtering method or the vapor deposition method, the formation efficiency is inferior to other methods from the viewpoint of increasing the thickness of the Cu-based film necessary for suppressing damage to the Cu wire.

  In the plating method, alkali metals are used as additives, and when these diffuse into the device and cause wafer contamination, the device characteristics deteriorate, so care must be taken. In addition, the plating method has disadvantages such as plating bath and waste liquid management.

  Bonding is performed using a Cu wire as the electrode wire 14 on the Cu-based second metal layer. More specifically, when ultrasonic vibration is applied by crimping a Cu system and a Cu wire, an oxide layer on the surface of the Cu system and the Cu wire is broken and an intrinsic surface is obtained. Can be bonded. In order to obtain the bonding strength between the Cu system and the Cu wire, the bonding is generally performed in an inert gas. If it is in an inert gas, the formation of an oxide layer on the Cu surface can be prevented, and bonding is possible by exposing the intrinsic surface by ultrasonic vibration and pressing. In some cases, hydrogen is added to the atmosphere during bonding, for example, in a reducing atmosphere.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, but may be appropriately modified within a range that can meet the purpose described above and below. Of course, it is possible to implement them, and they are all included in the technical scope of the present invention.

Example 1
In order to evaluate the surface roughness of the Ag alloy used for the first metal layer, Mo having a thickness of 500 nm and various Ag alloys having a thickness of 1000 nm shown in Table 1 were formed on the Si substrate. A sample was prepared. A sample in which Ag was formed instead of the Ag alloy was also prepared. In Table 1, “at%” is “atomic%”. The Mo was formed under the conditions of sputtering gas: argon, gas pressure: 10 mTorr, sputtering power: DC260W. The Ag or Ag alloy was formed by DC magnetron sputtering under the conditions of substrate temperature: room temperature to 150 ° C., atmosphere gas: inert gas such as Ar, Ar gas pressure: 2 mTorr, and sputtering power: DC 260 W.

  In this example, the reflectivity correlated with the surface roughness was measured as an index of the surface roughness that affects the bonding yield.

The Ag-based reflectance was measured as follows. That is, after performing heat treatment at a heat treatment temperature of 300 ° C. or 400 ° C. for 1 hour in a vacuum using the above sample, the visible light reflectance is increased by light having a wavelength of 380 to 780 nm with a D65 light source based on JIS R 3106. It measured using the spectrophotometer (The JASCO Corporation make: Visible and ultraviolet spectrophotometer "V-570"). Specifically, the ratio of the reflected light intensity (measured value) of the prepared sample to the reflected light intensity of the reference mirror, that is, [reflected light intensity of sample / reflected light intensity of reference mirror] × 100% is “reflected”. Rate ". In this example, the reflectance at λ = 400 nm was evaluated according to the following criteria. And in the case of A and B having a reflectance of 70% or more, the surface roughness is small, and the bonding strength with the Cu-based material is secured, and in the case of C in which the reflectance is less than 70%, the surface Since the roughness was large and the bonding strength with the Cu system was insufficient, it was rejected. The results are shown in Table 1.
Evaluation criteria for reflectance A: Reflectance is 80% or more B: Reflectance is 70% or more and less than 80% C: Reflectance is less than 70%

  From Table 1, the following can be understood. As a comparative example, No. 1 using a laminated structure of Ag and Mo. In No. 1, the Ag surface was easily agglomerated by heat, the reflectivity was lowered at a heat treatment temperature of 300 ° C., and the reflectivity was drastically lowered due to the rough surface at 400 ° C. Moreover, although it is an Ag alloy, the Nd content is insufficient. No. 2 or Bi content is insufficient. The reflectance of 8 also decreased. Further, No. containing Nd and Bi and containing only Cu as an alloy element. The reflectance also decreased in 5-7. In contrast, no. As in 3, 4, 9-12, when an Ag alloy containing at least one of Nd and Bi in the specified amount is formed, a reflectance of 80% or more can be secured by heat treatment at 300 ° C., and further 400 ° C. Even after the heat treatment at, the reflectance of 70% or more was secured, and the surface roughness was suppressed.

  No. in Table 1 1 Ag, No. 1 11 Ag-0.7 at% Nd-0.9 at% Cu, No. 11 For 12 Ag-0.2 at% Nd-0.35 at% Bi, the reflectance was also measured when the heat treatment conditions were “no heat treatment”, “heat treatment temperature 200 ° C.”, and “heat treatment temperature 500 ° C.”. The relationship between these heat treatment conditions and reflectance is shown in FIG.

  The following can be understood from FIG. That is, Ag is more likely to agglomerate after the heat treatment than the alloy, and when the heat treatment temperature exceeds 300 ° C., the reflectance decreases rapidly. On the other hand, Ag-0.7 at% Nd-0.9 at% Cu and Ag-0.2 at% Nd-0.35 at% Bi, which are the Ag alloys specified in the present invention, are also subjected to heat treatment at 400 ° C. in a vacuum. The reflectivity decrease is small, and the reflectivity decrease is small even after heat treatment at 500 ° C., and the mirror surface is maintained. Among these, it can be said that Ag-0.7 at% Nd-0.9 at% Cu is particularly less resistant to aggregation at heat treatment temperatures of 300 ° C. and 400 ° C., and has higher aggregation resistance.

  From the results shown in Table 1 and FIG. 3, if a prescribed Ag alloy is formed, high bonding strength with the Cu-based material that is in direct contact with the Ag alloy can be secured, and as a result, the reliability of the electrode structure can be improved. I understand that. In addition, the flatness of the Cu-based surface can be secured, and an improvement in bonding strength between the Cu-based and Cu wire bonding can be expected.

Example 2
On the Si substrate, the barrier layer shown in Table 2 with a film thickness of 500 nm and the film thickness of 1000 nm with No. An Ag alloy corresponding to the first metal layer having the same composition as 11 and 12 was formed to obtain a sample for evaluation. As a barrier layer in Table 2, Mo was formed in the same manner as in Example 1, and Mo nitride, Mo—Nb alloy, IZO, ITO, and Ti were formed under the following conditions.

A Mo target was used to form the Mo nitride, and a mixed gas of argon and nitrogen was used as the sputtering gas. At this time, the flow rate ratio of nitrogen gas to the total gas flow rate of argon + nitrogen was 30%. The sputtering conditions for Mo nitride are shown below.
Mo-nitride sputtering conditions and sputtering gas: Argon + Nitrogen (nitrogen gas flow rate ratio 30%)
・ Gas pressure: 2mTorr
・ Power: RF500W

For the formation of the Mo—Nb alloy, a Mo—Nb alloy containing 8 at% Nb was used as a target. The sputtering conditions for the Mo—Nb alloy are shown below.
Sputtering conditions of Mo—Nb alloy ・ Sputtering gas: Argon ・ Gas pressure: 2 mTorr
・ Power: DC260W

IZO is represented by In—Zn—O and is an oxide containing 30% by mass of ZnO. ITO is an oxide containing In-Sn-O and containing 30% by mass of SnO. The sputtering conditions for IZO and ITO are shown below.
Sputtering conditions of IZO and ITO ・ Sputtering gas: Argon and oxygen mixed gas ・ Gas pressure: 2 mTorr
・ Power: DC260W

Further, Ti was obtained as a barrier layer in Table 2 by performing sputtering under the following conditions using a Ti sputtering target.
Sputtering conditions of Ti ・ Sputtering gas: Argon ・ Gas pressure: 2 mTorr
・ Power: DC260W

  After forming each of the barrier layers, assuming a pattern width of the Al—Si electrode, a bonding pad pattern having a designed line width of 1000 μm square was formed to obtain an evaluation sample. And this sample for evaluation was wet-etched using phosphorous nitrate acetic acid. In detail, it etched using the phosphoric-acetic-acetate type etching liquid which is the product name: AC-101 by Nagase ChemteX, and whose liquid temperature is 40 degreeC. And the case where etching residue does not arise and the line width after an etching exceeds 80% of the said line width was evaluated as collective etching OK. On the other hand, the case where the line width after etching was 80% or less of the line width was evaluated as batch etching NG. In addition, when an etching residue of the barrier layer or the Ag alloy occurs; or, when an extreme undercut, specifically, when the barrier layer is etched quickly and the upper Ag alloy remains in a bowl shape; peeling occurs. Case: was also evaluated as batch etching NG. These results are shown in Table 2.

  Table 2 shows the following. From Table 2, it can be seen that Mo nitride, Mo—Nb alloy, and IZO can be etched together with phosphorous acetic acid simultaneously with Ag, but ITO and Ti cannot be etched together.

DESCRIPTION OF SYMBOLS 1 Collector electrode 2 Collector layer 3 Base layer 4 Body region 5 Emitter layer 6 Gate insulating film 7 Gate electrode 8 Interlayer insulating film 9 Electrode layer 10 Semiconductor substrate 11 Barrier layer 12 1st metal layer 13 2nd metal layer 14 Wire electrode

Claims (6)

An electrode structure provided on a semiconductor substrate,
An electrode layer;
A barrier layer provided on the electrode layer;
A first metal layer provided on the barrier layer;
A second metal layer provided on the first metal layer;
A wire electrode joined to the second metal layer,
The first metal layer includes, as an alloy element, Ag containing at least one of Nd: 0.10 atomic% to 2.0 atomic% and Bi: 0.08 atomic% to 2.0 atomic%. Alloy,
The second metal layer is Cu or Cu alloy;
The electrode structure is characterized in that the wire electrode is Cu or a Cu alloy.   2. The electrode structure according to claim 1, wherein the first metal layer is an Ag alloy further containing Cu in an amount of more than 0 atomic% and not more than 2.0 atomic% as an alloy element.   The electrode structure according to claim 1, wherein the second metal layer is a Cu foil or a Cu alloy foil formed by rolling or plating.   The electrode structure according to claim 1, wherein the barrier layer is selected from the group consisting of Mo, Mo alloy, Mo nitride, and IZO.   The electrode structure according to claim 1, wherein the electrode layer is one of Ti, Mo, Ni, Al, Au, or an alloy thereof.   A semiconductor device comprising the electrode structure according to claim 1.