JP2017117953A - Laminated electrode and semiconductor device including laminated electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for combining strong adhesion and high thermal conductivity, in a laminated electrode using copper as the electrode material.SOLUTION: A laminated electrode 6 includes a contact layer 3 for coming into electrical contact with a semiconductor substrate 2, a bonding layer 5 of a copper alloy for bonding with an external terminal, and a conductive barrier metal layer 4 containing Ta or Ti, provided between the contact layer 3 and bonding layer 5, and in contact with both the contact layer 3 and bonding layer 5. The bonding layer 5 contains an added metal. The added metal contains at least one kind of Ti, Ta, W, Mo, Au, Ag, Pt and Pd.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a laminated electrode provided on a semiconductor substrate. The technology disclosed in this specification also relates to a semiconductor device including a stacked electrode.

  Development of power semiconductor devices used in inverters, converters, and the like is underway. This type of semiconductor device is required to efficiently dissipate heat generated inside the element. For this reason, attempts have been made to employ copper having excellent thermal conductivity as an electrode material used in this type of semiconductor device.

  Patent Document 1 discloses a laminated electrode in which copper is employed as an electrode material. The laminated electrode includes a contact layer for making electrical contact with the semiconductor substrate, a copper layer for bonding with an external terminal, and a barrier metal layer provided between the contact layer and the copper layer. The barrier metal layer is for suppressing copper from diffusing into the semiconductor substrate beyond the contact layer, and is a conductive metal layer containing Ta or Ti.

JP 2014-107345 A

  In the laminated electrode of Patent Document 1, there is a concern that the adhesion between the copper layer and the barrier metal layer is reduced and the both are peeled off, so that the electrical characteristics or mechanical characteristics of the semiconductor device are deteriorated. For this reason, Patent Document 1 proposes to interpose a Ti adhesive layer between the copper layer and the barrier metal layer. However, when such an adhesive layer is interposed, there is a problem that the number of layers of the laminated electrode increases and the thermal resistance increases.

  The present specification provides a technique for achieving both strong adhesion and high thermal conductivity in a laminated electrode using copper as an electrode material.

  This specification discloses the laminated electrode provided on the semiconductor substrate. The laminated electrode is provided between a contact layer for electrically contacting the semiconductor substrate, a copper alloy bonding layer for bonding to an external terminal, and the contact layer and the bonding layer. And a conductive barrier metal layer containing Ta or Ti. The bonding layer includes an additive metal. The additive metal includes at least one of Ti, Ta, W, Mo, Au, Ag, Pt, and Pd.

  The atomic radius of the additive metal contained in the bonding layer is closer to the atomic radius of Ta or Ti of the barrier metal layer than copper. For this reason, the additive metal contained in the bonding layer is easily dissolved in the barrier metal layer. As a result, the bonding layer and the barrier metal layer can obtain a strong adhesion. Furthermore, since there is no need to interpose another layer between the bonding layer and the barrier metal layer, an increase in the number of layers of the laminated electrode can be suppressed, and an increase in thermal resistance can also be suppressed. Thus, the laminated electrode of the said aspect can make strong adhesive force and high heat conductivity compatible.

The principal part sectional view of the semiconductor device indicated by this specification is shown typically. A cross-sectional view of a test chip is schematically shown.

  As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 2 and a laminated electrode 6. The semiconductor substrate 2 is, for example, a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate, on which circuit elements that exhibit a specific function are formed. In this example, for example, a power semiconductor device such as an IGBT, MOSFET, or diode is formed on the semiconductor substrate 2.

  The laminated electrode 6 is connected to a power semiconductor device formed on the semiconductor substrate 2 and has a contact layer 3, a barrier metal layer 4, and a copper alloy bonding layer 5.

The contact layer 3 is in contact with the surface of the semiconductor substrate 2 and is in electrical contact with an impurity region constituting the power semiconductor device. For example, the contact layer 3 is in ohmic contact or Schottky contact with an impurity region constituting the power semiconductor device. For example, when the material of the semiconductor substrate 2 is silicon carbide, nickel silicide is used as the material of the contact layer 3 in ohmic contact with the n-type impurity region. Nickel silicide is an intermetallic compound of nickel and silicon. In one example, the nickel silicide includes at least one selected from the group consisting of Ni ₃ Si, Ni ₂ Si, Ni ₃ Si ₂ , and NiSi. The contact layer 3 is formed on the surface of the semiconductor substrate 2 using, for example, a sputtering technique.

  The barrier metal layer 4 is provided between the contact layer 3 and the bonding layer 5 and is in contact with both the contact layer 3 and the bonding layer 5. The barrier metal layer 4 is a conductive metal layer containing Ta or Ti, and is preferably Ta, Ti, TiN or TaN. The barrier metal layer 4 is provided to suppress the copper contained in the bonding layer 5 from diffusing into the semiconductor substrate 2 beyond the contact layer 3. The barrier metal layer 4 is formed on the surface of the contact layer 3 by using, for example, a sputtering technique.

  The bonding layer 5 is provided on the barrier metal layer 4 and is bonded to an external terminal. For example, solder is applied to the surface of the bonding layer 5, and lead frames, wires, and the like are bonded by reflow. The bonding layer 5 is a copper alloy containing an additive metal. As the additive metal, at least one of Ti, Ta, W, Mo, Au, Ag, Pt, and Pd is used. The barrier metal layer 4 is formed on the surface of the barrier metal layer 4 by using, for example, a sputtering technique.

  The laminated electrode 6 is characterized in that an additive metal is contained in the bonding layer 5. The atomic radius of the additive metal contained in the bonding layer 5 is closer to the atomic radius of Ta or Ti of the barrier metal layer 4 than copper. That is, the difference between the atomic radius of the added metal and the atomic radius of Ta or Ti is smaller than the difference between the atomic radius of copper and the atomic radius of Ta or Ti. For this reason, the additive metal contained in the bonding layer 5 easily dissolves in the barrier metal layer 4. Thereby, the bonding layer 5 and the barrier metal layer 4 can obtain a strong adhesion. The laminated electrode 6 is characterized in that the bonding layer 5 and the barrier metal layer 4 are in direct contact with each other. In other words, no other layer is interposed between the bonding layer 5 and the barrier metal layer 4. For this reason, since the laminated electrode 6 is composed of a small number of layers, the thermal resistance is low and high thermal conductivity can be obtained. Further, since the laminated electrode 6 is configured with a small number of layers, the production process is simplified, and the laminated electrode 6 can be formed at a low production cost.

  The content of the additive metal contained in the bonding layer 5 is desirably 0.2 atomic% or more. When the content is 0.2 atomic% or more, a sufficient number of atoms that contribute to the improvement of the adhesion between the bonding layer 5 and the barrier metal layer 4 is ensured. Thereby, the adhesive force between the bonding layer 5 and the barrier metal layer 4 is improved. Further, when the content is 0.2 atomic% or more, the crystal grains of the bonding layer 5 are miniaturized. For this reason, the stress applied to the grain boundary of the bonding layer 5 is reduced. As a result, the thermal stress at the interface between the bonding layer 5 and the barrier metal layer 4 is reduced, and the adhesion between the bonding layer 5 and the barrier metal layer 4 is improved. . In this respect, the crystal grain size of the bonding layer 5 is desirably 500 nm or less. Further, the content of the additive metal contained in the bonding layer 5 is desirably 5 atomic% or less. When the content is 5 atomic% or less, the bonding layer 5 that is a copper alloy can maintain high thermal conductivity.

(Adhesion test)
A test chip 10 shown in FIG. 2 was prepared, and an adhesion evaluation test of the laminated electrode 16 was performed. The test chip 10 shown in FIG. 2 was prepared by the following procedure. First, an n-type silicon carbide semiconductor substrate 12 was prepared. Next, a nickel silicide (Ni ₂ Si) contact layer 13 and a tantalum nitride (TaN) barrier metal layer 14 were sequentially formed on the semiconductor substrate 12 by using a sputtering technique. The contact layer 13 has a thickness of about 0.2 μm, and the barrier metal layer 14 has a thickness of about 0.1 μm. Next, a copper alloy bonding layer 15 was formed on the barrier metal layer 14 by using a sputtering technique. The thickness of the bonding layer 15 is about 5 μm. A plurality of types of test chips 10 were prepared by changing the type of metal added to the bonding layer 15.

  The adhesion evaluation test was performed by SAICAS (Surface and Interfacial Cutting Analysis System) method. Specifically, a cutting blade having a blade width of 300 μm is horizontally moved along the interface between the bonding layer 15 and the barrier metal layer 14, and the value obtained by dividing the horizontal drag applied to the cutting blade by the blade width of the cutting blade is peeled off. Calculated as intensity. In the adhesion evaluation test, the peel strength before and after the thermal cycle was measured. In the cooling / heating cycle, a temperature cycle of −40 ° C. and 200 ° C. was performed for 1 hour, and this temperature cycle was repeated 500 times. Table 1 shows the results of the adhesion evaluation test.

  As shown in Table 1, each of Examples 1 to 12 has a higher peel strength before the cooling and heating cycle than Comparative Example 1. For this reason, it was confirmed that the bonding layer 15 tightly adheres to the barrier metal layer 14 by including the additive metal. Further, in all of Examples 1 to 12, the change in peel strength is small before and after the cooling cycle, and the peel strength is 200 N / m or more even after the cooling cycle. On the other hand, in both Comparative Examples 1 and 2, the change in peel strength greatly decreases after the cooling and heating cycle. It was confirmed that Examples 1-12 can maintain strong adhesiveness before and after the cooling cycle. From these results, it was suggested that the semiconductor device including the laminated electrode 16 can exhibit stable electrical characteristics and mechanical characteristics even in a severe thermal environment.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: Semiconductor device 2: Semiconductor substrate 3: Contact layer 4: Barrier metal layer 5: Bonding layer 6: Multilayer electrode

Claims (4)

A laminated electrode provided on a semiconductor substrate,
A contact layer for making electrical contact with the semiconductor substrate;
A copper alloy bonding layer for bonding to an external terminal;
Provided between the contact layer and the bonding layer, in contact with both the contact layer and the bonding layer, and comprising a conductive barrier metal layer containing Ta or Ti,
The bonding layer includes an additive metal;
The laminated electrode, wherein the additive metal includes at least one of Ti, Ta, W, Mo, Au, Ag, Pt, and Pd.   2. The laminated electrode according to claim 1, wherein the content of the additive metal contained in the bonding layer is 0.2 atomic% or more and 5 atomic% or less.   The multilayer electrode according to claim 1, wherein the barrier metal layer is Ta, Ti, TaN, or TiN.   The semiconductor device which has the laminated electrode as described in any one of Claims 1-3.

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