JP2017118039A - Laminate, semiconductor element and electrical apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminate that can be used in a semiconductor element having a small electrical junction resistance value of ohmic junction, and a high strength for physical immobilization, and to provide a semiconductor element.SOLUTION: A laminate includes an oxide substrate 54 having a first surface 541 and a second surface 542 facing each other, and a contact resistance reduction layer 61, a solder erosion prevention layer 62, a bond strength improvement and/or contact resistance reduction layer 63, in this order, on the first surface 541 of the oxide substrate. The bond strength improvement and/or contact resistance reduction layer 63 is fixed to a frame by means of a solder 70, and at least an oxide semiconductor layer 10 and a Schottky electrode layer 20 are provided on the second surface 542 of the oxide substrate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a laminate, a semiconductor element, and an electric device.

As a method for forming an electrode of a semiconductor element using an oxide semiconductor, for example, when an electrode is formed on a Ga ₂ O ₃ (gallium oxide) single crystal, a technique using a Ti electrode (for example, Patent Document 1), A technique for forming a Ti electrode after plasma treatment (for example, Patent Document 2), a technique for performing heat treatment at 600 ° C. to 1000 ° C. after forming an In electrode on a Ga ₂ O ₃ single crystal (for example, Patent Document 3), A technique (for example, Patent Document 4) is known in which dry etching is performed on the surface of a Ga ₂ O ₃ single crystal to form an altered layer, and then a metal electrode is formed to perform ohmic bonding. In addition, a technique for forming an oxide semiconductor on a conductive substrate and forming a metal electrode by sputtering (for example, Patent Documents 5 and 6) is also known.

JP 2009-81468 A JP 2009-130013 A JP 2009-302257 A International Publication 2013/069729 International Publication No. 2015/025499 International Publication No. 2015/025500

  When a semiconductor is mounted, there are cases where a plurality of semiconductor elements are coupled on a substrate by wiring or used alone as a single-function discrete element. In either case, it is necessary to electrically connect the semiconductor element to the wiring board and physically fix it. Specifically, an ohmic junction function with a semiconductor and physical fixing to a wiring board, a frame, or the like are required. However, if you try to lower the electrical junction resistance value of the ohmic junction, the strength of physical immobilization will decrease, or if you try to increase the strength of physical immobilization, the electrical junction resistance value of the ohmic junction will There was a case to go up.

  An object of the present invention is to provide a stacked body and a semiconductor element that can be used for a semiconductor element having a small electrical junction resistance value of an ohmic junction and a high strength for physical fixation.

According to the present invention, the following laminates and the like are provided.
1. An oxide substrate having opposing first and second surfaces;
On the first surface side of the oxide substrate, it has a contact resistance reducing layer, a solder erosion preventing layer, an adhesion strength improving and / or a contact resistance reducing layer in this order,
The adhesive strength improving and / or contact resistance reducing layer is fixed to the frame with solder,
A stacked body including at least an oxide semiconductor layer and a Schottky electrode layer on a second surface side of the oxide substrate.
2. 2. The laminate according to 1, wherein the contact resistance reducing layer is a metal layer containing one or more selected from Ti, Mo, In, Sn, V, Cr, W, Pd, and Co.
3. 3. The laminate according to 1 or 2, wherein the solder erosion preventing layer is a metal layer containing one or more selected from Ni, Ni alloy, Cr and Cr alloy.
4). The laminate according to any one of claims 1 to 3, wherein the adhesion strength improving and / or contact resistance reducing layer is a metal layer containing at least one selected from Au, Ag, Pt and Pd. .
5. The laminate according to any one of 1 to 4, wherein the oxide substrate is made of β-Ga ₂ O ₃ .
A semiconductor element comprising the laminate according to any one of 6.1 to 5.
7). 7. The semiconductor element according to 6, which is a discrete element.
An electrical apparatus comprising the semiconductor element according to 8.6 or 7.

  ADVANTAGE OF THE INVENTION According to this invention, the laminated body and semiconductor element which can be used for the semiconductor element with small electrical junction resistance value of ohmic junction and high intensity | strength to fix physically can be provided.

It is a schematic sectional drawing which shows the Schottky barrier diode which concerns on one Embodiment of this invention. 1 is a schematic plan view of a discrete element according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of the discrete element of FIG. 2.

[Laminate]
The laminate of the present invention has an oxide substrate having first and second surfaces facing each other, and a contact resistance reducing layer, a solder erosion preventing layer, an adhesive strength on the first surface side of the oxide substrate. An improvement and / or contact resistance reduction layer (adhesion strength improvement / contact resistance reduction layer) is provided in this order. At least the oxide semiconductor layer and the Schottky electrode layer are provided on the second surface side of the oxide substrate. The adhesive strength improving / contact resistance reducing layer is fixed to the frame with solder.

  A contact resistance reduction layer, a solder erosion prevention layer, and an adhesion strength improvement / contact resistance reduction layer are formed in this order on the back surface of the oxide substrate on which the oxide semiconductor layer is formed, and are fixed to the frame with solder. For this reason, the electrical resistance value of the ohmic junction is reduced, and the physical fixing strength is also increased.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
Since the embodiments described below are preferred specific examples of the present invention, various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the following description. As long as there is no description, it is not restricted to these aspects.

FIG. 1 is a schematic cross-sectional view showing a multilayer body and a Schottky barrier diode according to an embodiment of the present invention.
The oxide substrate 54 has a first surface 541 and a second surface 542 facing each other.
On the first surface 541, a contact resistance reducing layer 61, a solder erosion preventing layer 62, an adhesion strength improving and / or contact resistance reducing layer 63 are laminated in this order. The contact resistance reducing layer 61, the solder erosion preventing layer 62, and the adhesion strength improving / contact resistance reducing layer 63 form a back contact layer 60 for taking out the electrode. The adhesion strength improving / contact resistance reducing layer 63 is fixed to a frame (not shown) via a solder layer 70.
A Schottky electrode layer 20 and an aluminum layer 40 are provided in this order on the oxide semiconductor layer 10, and an insulating film 30 is interposed between a portion of the oxide semiconductor layer 10 and the Schottky electrode layer 20. It is preferable. One end of the insulating film 30 becomes thinner toward the insulating film non-intervening region and is tapered at an angle θ. The aluminum layer 40 reduces heat and ultrasonic damage in a wire bonding process such as Al or Cu.
The oxide semiconductor layer 10, the Schottky electrode layer 20, the aluminum layer 40, the oxide substrate 54, and the back contact layer 60 form the Schottky barrier diode 1.

  In this embodiment, the Schottky electrode layer 20 is a stacked body of a first layer 21 made of a metal having Schottky characteristics and a second layer 22 made of a metal having Schottky characteristics. The first layer 21 and the second layer 22 are preferably separate metal layers. The first layer 21 is a layer that contacts (acts) with the oxide semiconductor layer 10 and exhibits Schottky characteristics. The second layer 22 itself has Schottky characteristics, and aluminum atoms enter the first layer 21 from the aluminum layer stacked on the second layer 22 to reduce the Schottky characteristics, It plays a role to prevent becoming a new resistance layer. Even if the thickness of the first layer 21 is increased, it is difficult to suppress the diffusion and reaction of aluminum. Therefore, it is preferable to provide the second layer 22 and have a laminated structure of different materials. By separating the functions in this way, the Schottky characteristics can be maintained more stably.

  2 is a schematic plan view showing a discrete element according to an embodiment of the present invention, and FIG. 3 is a schematic cross-sectional view taken along line AA of FIG. In the discrete element 100 shown in these drawings, the Schottky barrier diode 1 is fixed to the frame 2 through the solder layer 70 as shown in FIG. As shown in FIG. 2, the Schottky barrier diode 1 is connected to the anode / cathode portion 4 by a bonding wire 3.

Hereinafter, each layer will be described.
<Oxide substrate>
As the oxide substrate, for example, a single crystal β-Ga ₂ O ₃ substrate, α-Ga ₂ O ₃ substrate, InGaO ₃ substrate, or the like can be used. Preferably, an n-type doped β-Ga ₂ O ₃ substrate, α-Ga ₂ O ₃ substrate, or InGaO ₃ substrate can be used. As the oxide substrate, a substrate having a low specific resistance is preferably used. The specific resistance of the substrate is preferably less than 1 Ωcm, more preferably less than 0.1 Ωcm, even more preferably less than 0.01 Ωcm, and particularly preferably less than 0.001 Ωcm. In the case where an oxide semiconductor layer is formed by epitaxial growth on an oxide substrate, an epitaxial film with few defects can be easily obtained by epitaxially growing the oxide semiconductor layer after treating the surface of the oxide substrate with oxygen plasma. .

As the oxide semiconductor layer, an n-type doped β-Ga ₂ O ₃ layer, α-Ga ₂ O ₃ layer, InGaO ₃ layer, an undoped β-Ga ₂ O ₃ layer, α-Ga _{A 2} O ₃ layer, an InGaO ₃ layer, or the like can be used. The specific resistance is preferably 1 Ωcm or more and 1E + 6 (1 × 10 ⁶ ) Ωcm or less, more preferably 1 Ωcm or more and 1E + 4 (1 × 10 ⁴ ) Ωcm or less, and further preferably 10 Ωcm or more and 1E + 4 (1 × 10 ⁴ ) Ωcm or less.

An α-Ga ₂ O ₃ film or the like is formed by epitaxial growth on an n-type doped α-Ga ₂ O ₃ layer (oxide substrate) formed on sapphire and then peeled off to form an n-type oxide semiconductor Can be used as a membrane. Preferred n-type oxide semiconductors from the standpoint of easy performance are β-Ga ₂ O ₃ and α-Ga ₂ O ₃ doped with an n-type having a large band gap, and InGaO ₃ . These n-type oxide semiconductor layers are advantageous for forming an n-type oxide semiconductor layer having good crystallinity and few defects.

  The thickness of the oxide substrate is usually 200 to 2,000 μm.

<Contact resistance reduction layer>
The contact resistance reducing layer is a layer for reducing the contact resistance between the oxide substrate and the solder.
The contact resistance reducing layer is preferably a metal (including alloy) layer containing at least one selected from Ti, Mo, In, Sn, V, Cr, W, Pd, and Co. By providing the contact resistance reducing layer, an ohmic junction can be formed and the contact resistance value can be kept small.
The contact resistance reducing layer is more preferably a metal layer containing one or more selected from Ti, Mo, In and Sn, and more preferably an In metal layer doped with Sn.

  In addition, when the oxide substrate is an n-type doped oxide substrate, the contact resistance reducing layer has conductivity even when the metal itself is oxidized into a metal oxide by contact with the oxide substrate. It is preferable.

  The thickness of the contact resistance reducing layer is usually 20 nm to 1 μm. If it is less than 20 nm, a portion that is too thin to become a metal film is formed, and the contact resistance value may increase. On the other hand, if the thickness exceeds 1 μm, the contact resistance reducing layer itself may become a resistance layer, and it may take a long time to form a film, leading to an increase in production cost. Preferably they are 30 nm-500 nm, More preferably, they are 40 nm-400 nm, More preferably, they are 50 nm-300 nm.

<Solder erosion prevention layer>
The solder erosion prevention layer is a layer for suppressing the contact resistance reduction layer from deteriorating due to the solder component fixedly mounted on the frame and increasing the contact resistance value or reacting with the solder component to change into the resistance layer. . By suppressing the erosion of the solder, the solder does not enter the ohmic contact portion between the oxide layer and the metal, or the solder and the metal in the contact resistance reducing layer do not react to increase the resistance.

  The solder erosion preventing layer is a metal layer containing at least one selected from Ni, Ni alloys (Ni—V alloys, etc.), Cr, and Cr alloys (Cr—Cu alloys, etc.). A metal layer containing at least one selected from Ni and Ni alloys is preferable, and a Ni metal layer is more preferable.

  The thickness of the solder erosion preventing layer is usually 50 nm to 10 μm. If the thickness is less than 50 nm, a portion that is too thin to become a solder erosion preventing layer is formed, and the contact resistance value may increase. On the other hand, when the thickness exceeds 10 μm, the solder erosion preventing layer itself may become a resistance layer, and it takes a long time to form the film, which may increase the production cost. Preferably they are 100 nm-5 micrometers, More preferably, they are 300 nm-3 micrometers, More preferably, they are 500 nm-2 micrometers.

<Adhesive strength improvement and / or contact resistance reduction layer>
Adhesion strength improvement and / or contact resistance reduction layer (adhesion strength improvement / contact resistance reduction layer) may change contact resistance reduction layer and solder erosion prevention layer due to solder components fixedly mounted on the frame and increase contact resistance value. , Suppresses the change to the resistance layer by reacting with the solder component, suppresses the solder erosion prevention layer itself from being oxidized and loses the ability to prevent solder erosion before bonding to the solder, and further prevents the solder erosion prevention layer. It is a layer for reducing the contact resistance between the solder and the solder and / or keeping the adhesive strength large.

  The adhesive strength improving / contact resistance reducing layer may be a layer mainly having an adhesive strength improving action, a layer mainly having a contact resistance reducing action, or a layer having both an adhesive strength improving action and a contact resistance reducing action.

  The adhesion strength improving / contact resistance reducing layer is preferably a metal (including alloy) layer containing at least one selected from Au, Ag, Pt and Pd. More preferably, it is a metal layer containing at least one selected from Au and Ag from the viewpoint of productivity and price.

  The thickness of the adhesive strength improving / contact resistance reducing layer is usually 20 nm to 1 μm. If it is less than 20 nm, a portion that is too thin to become a metal film is formed, and the contact resistance value may increase. On the other hand, if the thickness exceeds 1 μm, the adhesive strength improving / contact resistance reducing layer itself may become a resistance layer, and it takes too much time for film formation, which may increase the production cost. Preferably they are 30 nm-500 nm, More preferably, they are 40 nm-400 nm, More preferably, they are 50 nm-300 nm.

<Solder layer>
The solder layer is a layer for fixing the adhesive strength improving / contact resistance reducing layer to the frame. The solder layer can be composed of solder used in the technical field, for example, Sn—Pb, Sn—Sb, Sn—Cu, Sn—Ag, Sn—Bi, Sn—Ag—Cu, Sn—Ag, Cu—. It consists of Sb (Bi) or the like.
The thickness of the solder layer is usually 50 μm to 5 mm.

<Oxide semiconductor layer>
The oxide semiconductor layer preferably contains one or more selected from indium oxide and gallium oxide. An n-type oxide semiconductor layer is preferable.

Specifically, it is preferably made of β-Ga ₂ O ₃ , α-Ga ₂ O ₃ or InGaO ₃ .
Examples of the composition for forming a single crystal phase include Ga / (In + Ga) = 90 to 100 atomic%, or Ga / (In + Ga) = 45 to 55 atomic%. In the case of Ga / (In + Ga) = 90 to 100 atomic%, β-Ga ₂ O ₃ or α-Ga ₂ O ₃ doped with In or not doped can be formed. Β-Ga ₂ O ₃ and α-Ga ₂ O ₃ can be formed depending on the selection of the substrate, film formation conditions, the crystallization temperature, and the like. When β-Ga ₂ O ₃ is formed, an n-type doped β-Ga ₂ O ₃ substrate doped with Si, Sn, Ge or the like can be used. On the other hand, in the case of forming α-Ga ₂ O ₃ , a Ga ₂ O ₃ film doped with n-type such as mist CVD, ion plating, sputtering or the like is formed on a sapphire substrate under heating, or heated after formation. Can be formed by crystallization, and can be peeled from the sapphire substrate and used as a substrate. When the composition is Ga / (In + Ga) = 45 to 55 atomic%, an InGaO ₃ phase can be formed.

  Although the thickness of an oxide semiconductor layer is not specifically limited, Usually, they are 0.1 micrometer or more and 100 micrometers or less, Preferably they are 0.5 micrometer or more and 50 micrometers or less.

<Schottky electrode layer>
As a Schottky electrode layer, a laminate in which two or more metal layers made of a metal having a high work function are stacked, or a metal oxide layer made of a metal layer made of a metal having a high work function and an oxide of a metal having a high work function A laminate can be used. When using a laminate of a metal layer and a metal oxide layer, after forming a metal layer having a large work function, the metal oxide layer is in contact with the oxide semiconductor layer by heat treatment or the like to oxidize the metal oxide layer. In addition, a portion of the metal layer that is not oxidized can be used as the metal layer. The work function is usually 4.4 eV or more, preferably 4.5 eV or more. The upper limit of the work function is usually 6.5 eV. Specific metals include Au, Pt, Pd, Ni, Ru, Mo, Ti, and the like, and Ni, Ru, Mo, Ti, and the like are preferably used.
When a metal having a high work function is an expensive metal, the metal is used as a very thin layer in contact with an oxide semiconductor, and a layer formed using another metal is preferably stacked.
The work function can be measured by photoelectron spectroscopy.

  The thickness of the Schottky electrode layer is not particularly limited, but is usually 0.02 μm or more and 10 μm or less, preferably 0.05 μm or more and 5 μm or less. In FIG. 1, the first Schottky layer 21 is usually 0.02 μm or more and 1 μm or less. The second Schottky layer 22 is usually 0.02 μm or more and 1 μm or less.

<Insulating film>
An insulating film is preferably formed in part between the oxide semiconductor layer and the Schottky electrode layer. With the insulating film, the concentration of power on the Schottky electrode layer can be relaxed, and the withstand voltage can be improved.

  The thickness of the insulating film is preferably 0.1 μm to 30 μm in order to withstand a high voltage. More preferably, it is 0.5 μm to 15 μm, and further preferably 1 μm to 10 μm.

In the boundary region between the insulating film intervening region and the insulating film non-intervening region, the insulating film is preferably tapered. By taper processing, rapid fluctuations in the film thickness in the boundary region can be suppressed, and the withstand voltage of the element is not lowered. The taper angle is preferably 15 to 70 degrees. More preferably, it is 20 to 60 degrees, and further preferably 25 to 50 degrees.
For etching the tapered insulating film, a commonly used method such as dry etching or wet etching can be used.

  The insulating film is preferably a single film or a stacked film of one or more selected from silicon oxide, aluminum oxide, and silicon nitride. The insulating film in contact with the oxide semiconductor layer is preferably an oxide. This is because in the case where a nitride film is formed, the oxide semiconductor layer may be reduced and carriers may be generated. When silicon oxide and aluminum oxide are compared, aluminum oxide is preferable as an insulating film because it has an action as an oxygen nonconductor.

[Semiconductor elements, electrical equipment]
The laminate of the present invention can be used for a Schottky barrier diode, and can constitute a semiconductor element such as a discrete element. In particular, the present invention can be suitably applied to a discrete element in which a semiconductor element using an oxide semiconductor is fixedly mounted on a frame. Such a semiconductor element can be used for electrical equipment such as a power converter.

The discrete element shown in FIGS. 2 and 3 was manufactured.
A Schottky barrier diode element in which an oxide semiconductor layer is formed on an oxide substrate is formed, and on the opposite side, as a back contact layer, a contact resistance reducing layer, a solder erosion preventing layer, an adhesion strength improving and / or a contact resistance reducing layer Were formed in this order.

It should be noted that a β-Ga ₂ O ₃ substrate is used as the oxide substrate, an In metal layer containing 10 wt% Sn as the contact resistance reducing layer is 100 nm, a Ni metal layer is 700 nm as the solder erosion preventing layer, and adhesion strength is improved and / or contact resistance is increased. An Au layer was formed as a reduction layer by a 100 nm sputtering method. An InGaO ₃ film was used as the oxide semiconductor layer.

  This is diced by a wafer dicing device to form individual elements, and then set in a vacuum trough with a sheet solder M705 (Sn-3.0Ag-0.5Cu) thickness of 70 μm installed on the frame, and the formic acid atmosphere Then, after heating and bonding, it was cooled and soldered. Thereafter, wirings of 150 μm were respectively provided on the cathode side and the anode side by wire bonding. It was confirmed that the junction resistance value was small and the fixing strength was strong.

  Although the embodiments and examples of the present invention have been described above, those skilled in the art can easily make many changes to the illustrated embodiments and examples without substantially departing from the features of the present invention. is there. These modifications are included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Schottky barrier diode 2 Frame 3 Bonding wire 4 Anode and cathode part 10 Oxide semiconductor layer 20 Schottky electrode layer 21 First Schottky layer 22 Second Schottky layer 30 Insulating film 40 Aluminum layer 54 Oxide substrate 541 First surface of oxide substrate 542 Second surface of oxide substrate 60 Back surface contact layer 61 Contact resistance reduction layer 62 Solder erosion prevention layer 63 Adhesion strength improvement and / or contact resistance reduction layer 70 Solder layer 100 Discrete element θ Taper Corner

Claims (8)

An oxide substrate having opposing first and second surfaces;
On the first surface side of the oxide substrate, it has a contact resistance reducing layer, a solder erosion preventing layer, an adhesion strength improving and / or a contact resistance reducing layer in this order,
The adhesive strength improving and / or contact resistance reducing layer is fixed to the frame with solder,
A stacked body including at least an oxide semiconductor layer and a Schottky electrode layer on a second surface side of the oxide substrate.   The laminated layer according to claim 1, wherein the contact resistance reducing layer is a metal layer containing one or more selected from Ti, Mo, In, Sn, V, Cr, W, Pd, and Co. body.   The laminate according to claim 1 or 2, wherein the solder erosion preventing layer is a metal layer containing one or more selected from Ni, Ni alloy, Cr and Cr alloy.   The adhesion strength improving and / or contact resistance reducing layer is a metal layer containing at least one selected from Au, Ag, Pt and Pd. Laminated body. The laminate according to any one of claims 1 to 4, wherein the oxide substrate, characterized by comprising the β-Ga ₂ O _3.   A semiconductor device comprising the laminate according to claim 1.   The semiconductor device according to claim 6, wherein the semiconductor device is a discrete device. An electric device comprising the semiconductor element according to claim 6.

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