JP2016096232A - Semiconductor integrated circuit device and manufacturing method of the same, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and a manufacturing method of the same, and an electronic apparatus, which uses COF wiring for achieving low impedance of IC wiring to reduce noise current or a flow of heat in an IC or an LSI.SOLUTION: A semiconductor integrated circuit device 8 comprises: a COF substrate 10; a metal layer 22which is formed on the COF substrate 10 and connected to the outside; a semiconductor integrated circuit 12 mounted on the metal layer 22; and bumps 34, 34, 34..34arranged between the semiconductor integrated circuit 12 and the metal layer 22, for connecting the semiconductor integrated circuit 12 and the meta layer 22. The bumps 34, 34, 34..34are arranged at a bump pitch L3 where the metal layer 22does not contact the semiconductor integrated circuit 12 when the metal layer 22is thermally deformed.SELECTED DRAWING: Figure 6

Description

  The present embodiment relates to a semiconductor integrated circuit device, a manufacturing method thereof, and an electronic apparatus.

  Conventionally, as a liquid crystal driving module for driving a thin film transistor (TFT) type liquid crystal display device, a source driver circuit, a timing controller, a power supply circuit, a light emitting diode (LED) driver circuit, etc. on a printed circuit board A configuration in which the semiconductor integrated circuits are individually mounted is used.

  On the other hand, a liquid crystal driving module in which a semiconductor integrated circuit such as a source driver circuit is sealed in a package of a chip on film (COF) structure using a flexible film-like substrate has been developed.

  A semiconductor integrated circuit device and an electronic device that can be mounted on a COF structure because the low voltage circuit portion and the high voltage circuit portion are integrated into a single chip to improve mounting efficiency and heat can be efficiently radiated from the high voltage circuit portion. It is disclosed.

JP 2008-166460 A JP 2014-093432 A

  In the present embodiment, in a semiconductor integrated circuit (IC: Integrated Circuit or LSI: Large Scale Integrated Circuit) in which a COF package is used, the COF wiring is used for reducing the impedance of the IC wiring, and the noise current in the IC or LSI is used. A semiconductor integrated circuit device that reduces heat flow and a manufacturing method thereof, and an electronic device are provided.

  According to one aspect of the present embodiment, a COF substrate, a metal layer formed on the COF substrate and connected to the outside, a semiconductor integrated circuit mounted on the metal layer, and the semiconductor integrated circuit The bump is disposed between the circuit and the metal layer and connects the semiconductor integrated circuit and the metal layer, and the bump is formed when the metal layer is thermally deformed. Provided is a semiconductor integrated circuit device arranged at a bump pitch that does not contact the semiconductor integrated circuit.

  According to another aspect of the present embodiment, a step of forming a bump made of Au on the semiconductor integrated circuit that serves both as an electrical connection and a heat dissipation path, and a Sn layer and a copper wiring layer on the COF substrate Forming a metal layer, and applying heat to the metal layer through the semiconductor integrated circuit, melting Sn of the Sn layer and alloying with the Au of the bump, And a step of thermocompression bonding the semiconductor integrated circuit and the COF substrate, and the bumps are arranged at a bump pitch that does not contact the semiconductor integrated circuit when the metal layer is thermally deformed. A method of manufacturing an integrated circuit device is provided.

  According to another aspect of the present embodiment, an electronic apparatus including the above semiconductor integrated circuit device is provided.

  According to the present embodiment, in an IC or LSI in which a COF package is used, a semiconductor integrated circuit device that uses a COF wiring to reduce the impedance of the IC wiring and reduces noise current and heat flow in the IC or LSI, and its A manufacturing method and an electronic device can be provided.

1 is a schematic plan configuration diagram of a film on which a plurality of semiconductor integrated circuit devices according to an embodiment are mounted. 1 is a schematic plan configuration diagram of a semiconductor integrated circuit device according to an embodiment. FIG. FIG. 3 is a schematic sectional view taken along the line II of FIG. 2. In a semiconductor integrated circuit device according to a comparative example, (a) a schematic cross-sectional structure diagram for explaining a crimping process between a semiconductor integrated circuit (LSI) and a COF substrate, and (b) a schematic cross-sectional structure of a metal layer portion on the COF substrate. Figure. FIG. 5 is a schematic cross-sectional structure diagram illustrating a crimping process between an LSI and a COF substrate in the semiconductor integrated circuit device according to the embodiment. FIG. 3 is a schematic plan view illustrating a connection relationship between a bump disposed on an LSI and a copper wiring in the semiconductor integrated circuit device according to the embodiment. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a method for manufacturing a semiconductor integrated circuit device according to an embodiment, in which (a) a schematic cross-sectional structure diagram illustrating a step of forming a bump on an LSI, and (b) a schematic diagram illustrating a step of preparing a COF substrate. FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a method for manufacturing a semiconductor integrated circuit device according to an embodiment, in which (a) a schematic cross-sectional structure diagram illustrating a crimping process between an LSI and a COF substrate; Structural drawing. In the semiconductor integrated circuit device concerning the modification 1 of an embodiment, the typical plane structure figure explaining the connecting / disconnecting relation between the arrangement composition of a bump and a dummy bump arranged on LSI, and a bump and a metal layer. FIG. 10 is a schematic sectional view taken along line II-II in FIG. 9. FIG. 10 is a schematic plan view illustrating a configuration of bumps and dummy bumps arranged on an LSI in a semiconductor integrated circuit device according to Modification 2 of the embodiment. In a semiconductor integrated circuit device according to Modification 1 and Modification 2 of the embodiment, (a) a schematic cross-sectional structure diagram explaining a connection relationship between a bump disposed on an LSI and an embedded wiring layer, and (b) an LSI. The typical cross-section figure explaining the non-connection relation of the dummy bump arrange | positioned above and a buried wiring layer.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of this embodiment, and the embodiment of this embodiment includes the material of the component, The shape, structure, arrangement, etc. are not specified below. This embodiment can be modified in various ways within the scope of the claims.

[Embodiment]
(Semiconductor integrated circuit device)
A schematic planar configuration of a film 100 on which a plurality of semiconductor integrated circuit devices 8 (8 ₁ , 8 ₂ , 8 ₃ ...) According to the embodiment are mounted is expressed as shown in FIG. A schematic planar configuration of the semiconductor integrated circuit device 8 according to the embodiment is expressed as shown in FIG. A schematic cross-sectional structure taken along line II in FIG. 2 is expressed as shown in FIG.

As illustrated in FIG. 1, film holes 100 </ b> H are formed at both ends of the film 100 along the length direction of the film 100 used as a flexible circuit board. The semiconductor integrated circuit device 8 (8 ₁ , 8 ₂ , 8 _3, ...) Is a semiconductor integrated circuit mounted on a portion of the film 100 that is used as the COF substrate 10 (10 ₁ , 10 ₂ , 10 ₃ ,. A circuit (LSI or IC) 12 (12 ₁ , 12 ₂ , 12 ₃ ,...) Is provided.

In the semiconductor integrated circuit device 8 according to the present embodiment, the COF is designed to emit noise current and heat flow generated in the semiconductor integrated circuit device 8 to an external substrate or the like with low thermal resistance (low thermal impedance) of the LSI wiring. Utilizing wiring. That is, in order to reduce noise and heat generated in the semiconductor integrated circuit device 8 (8 ₁ , 8 ₂ , 8 _3, ...), A COF copper wiring as shown in FIG. ing. In this case, bumps (BUMP: generally gold) for connecting the copper wiring layer 22C under the LSI 12 chip and the LSI 12 chip are formed between the LSI 12 and the metal layer 22 (22S / 22C).

More specifically, as illustrated in FIGS. 2 and 3, the power wiring layers 16 ₁ and 16 ₂ connecting the LSI 12 and the power terminals 15 ₁ and 15 ₂ , the LSI 12 and the input signal terminal group. An input signal wiring group 17 that connects between the LSI 12 and an output signal wiring group 19 that connects between the LSI 12 and the output signal terminal group 20 are formed on a metal layer on the COF substrate 10 below the chip of the LSI 12. 22 is formed. Between the LSI 12 and the metal layer 22 (22S / 22C), bumps (30 ₁ , 30 ₂ , 30 ₃ ,..., 30 _n ) connecting the LSI 12 and the power wiring layers 16 ₁ , 16 ₂ , (32 ₁ , 32 ₂ , 32 ₃ ,... 32 _n ), (34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n ), micro bumps 37 that connect the LSI 12 and the input signal terminal group 18, and the LSI 12 Micro bumps 38 for connecting the output signal terminal group 20 are formed. Specifically, the power wiring layers 16 ₁ and 16 ₂ include a V _DD power metal layer 22 ₁ , a V _CC power metal layer 22 _2, and a GND power metal layer 22 ₃ , respectively. The bumps 30 ₁ , 30 ₂ , 30 ₃ ,..., 30 _n are connected to the GND power metal layer 22 ₃ . The bumps 32 ₁ , 32 ₂ , 32 ₃ ,..., 32 _n are connected to the V _CC power metal layer 22 ₂ . The bumps 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n are connected to the V _DD power metal layer 22 ₁ . In the following description, bumps 30 ₁ , 30 ₂ , 30 ₃ ,..., 30 _n connected to GND power metal layer 22 ₃ are simply bumps 30 and bumps connected to V _CC power metal layer 22 _2. 32 is referred to as _{1 · 32 2 · 32 3 ·} ... · 32 n simply a bump 32, V _DD bump _{34 1 · 34 2 · 34 3} · ... · 34 n simply bumps 34 connected to the power metal layer 22 ₁ There is a case. Further, the V _DD power metal layer 22 ₁ , the V _CC power metal layer 22 _2, and the GND power metal layer 22 ₃ may be simply referred to as the metal layer 22. The bumps 30, 32, 34, 37, and 38 serve both as an electrical connection and a heat dissipation path.

  As described above, in the semiconductor integrated circuit device 8 according to the embodiment, the bumps 30, 32, 34, 37, and 38 that connect the LSI 12 and the metal layer 22 are provided, so that the COF copper wiring is reduced in impedance of the IC wiring. The noise and heat generated particularly in the LSI 12 of the semiconductor integrated circuit device 8 can be discharged from the bumps 30, 32, 34, 37, and 38 to an external substrate or the like via the COF wiring. Therefore, noise and heat generated in the semiconductor integrated circuit device 8 can be reduced.

(Comparative example)
In the semiconductor integrated circuit device according to the comparative example, a schematic cross-sectional structure for explaining the crimping process between the semiconductor integrated circuit (LSI) and the COF substrate is expressed as shown in FIG. The schematic cross-sectional structure of the part is expressed as shown in FIG. The metal layer 22 ₁ includes a copper wiring layer 22C formed on the COF substrate 10 and a metal layer (Sn) 22S formed on the copper wiring layer 22C.

In the pressure bonding process between the LSI 12 and the COF substrate 10, as shown in FIG. 4A, heat is applied to the copper wiring layer 22C through the LSI 12 using the heater 40, and the metal layer 22S on the copper wiring layer 22C. Then, tin (Sn) is melted, and bonding layers (Sn—Au alloy layers) 35 ₁ and 35 ₂ are formed by alloying the metal layer 22S on the copper wiring layer 22C and the gold bumps 34 ₁ and 34 ₂ .

  Heating by the heater 40 is performed to melt Sn of the metal layer 22S, but this heat is also applied to the entire copper wiring layer 22C. For this reason, as the copper wiring layer 22C itself thermally expands, as shown in FIG. 4, the metal layer 22 including the metal layer (Sn) 22S and the copper wiring layer 22C is curved. As a result, adverse effects such as contact of the copper wiring layer 22C itself with the surface of the LSI 12 occur.

(Bump pitch value setting)
In the semiconductor integrated circuit device 8 according to the embodiment, a schematic cross-sectional structure for explaining the crimping process between the LSI 12 and the COF substrate 10 is expressed as shown in FIG. In the example shown in FIG. 5, the bumps 34 ₁ and 34 ₂ connected to the V _DD power wiring layer are shown, but the present invention can be similarly applied to the other bumps 30, 32, 37, and 38. The bonding layers (Sn—Au alloy layers) 35 ₁ and 35 ₂ are not shown.

Based on the calculation of the coefficient of thermal expansion of copper (Cu) used for the copper wiring layer 22C, the design / manufacturing conditions in which the metal layer 22 ₁ (22S · 22C) is not in direct contact with the LSI 12 without the bumps (COF wiring thermal expansion) Suppression layout) is provided in the configuration of the LSI 12 / COF substrate 10. The metal layers 22 ₁ (22S and 22C) are arranged with a bump pitch set so as not to directly contact the semiconductor integrated circuit without passing through the bumps.

Necessary parameters are the pitch between the bumps 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _{n made} of Au (bump pitch L), and the bumps 34 ₁ , 34 ₂ , 34 ₃ ,. The height is 34 _n (bump height H), and on the COF substrate 10 side, the temperature of the heater 40 (heater temperature T).

Of these, the heater temperature T affects the crimping conditions, and the bump height H affects the material cost. Therefore, the bump temperature H is determined based on the design value of the bump pitch L3 obtained from equations (1) to (3) described later. If 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n are arranged, bending damage of the metal layer 22 including the copper wiring layer 22C can be avoided.

In the semiconductor integrated circuit device 8 using a general COF package, the values of the above parameters (bump pitch L, bump height H, heater temperature T) are limited. For example, the heater temperature T is about 400 ° C. The heater temperature T in order to bind the Au bump _{34 1 · 34 2 · 34 3} · ... · 34 n of the copper wiring pattern and LSI12 copper wire layer 22C of the COF, are formed on the copper wiring pattern COF It is determined from the temperature at which Sn of the metal layer 22S is melted.

The bump height H is, for example, about 15 μm. If the bump height H is too high, the amount of Au used increases and the cost increases. On the other hand, if the bump height H is too low, the coupling between the metal layer 22S and the bumps 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n becomes insufficient, and the mounting of the LSI 12 becomes a problem.

As illustrated in FIG. 5, the thermal expansion coefficient α of copper (Cu) of the copper wiring layer 22C constituting the curved metal layer 22 is α = 16.6 × 10 ⁻⁶ / ° C., and depends on the heater temperature T. The wiring length L2 after thermal expansion of the copper wiring layer 22C (wiring length L1) can be obtained by the following equation (1).

L2 = L + L × α × (T−T _a ) (1)

Here, T _a is the ambient temperature, for example, about 27 ° C..

  The bending height W of the wiring of the copper wiring layer 22C that is expanded and curved to the length L2 can be obtained by the following equation (2).

W = √ [(L2 / 2) ² − (L1 / 2) ² ] (2)

When the height of the bumps 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n is the bump height H, the bumps 34 ₁ , 34 ₂ , 34 made of Au with the bump pitch L3 satisfying the following expression (3) ₃ ... 34 _n may be disposed on the metal layer 22 (22S 22C).

H> W (3)

That is, the bump pitch L3 satisfying the bump height H> the curved height W in the expression (3) is a condition for avoiding contact of the thermally expanded copper wiring layer 22C with the LSI 12. The bump height H is also a distance (interval) between the LSI 12 and the metal layer 22 (22S / 22C).

As described above, the heater temperature T and the bump height H are uniquely determined, and if the COF wiring pattern is a copper wiring pattern, the thermal expansion coefficient α of copper is also uniquely determined. Therefore, in order to use the COF wiring as the wiring of the LSI 12, as illustrated in FIG. 6, by arranging the Au bumps 34 ₁ , 34 ₂ , 34 ₃ ... 34 _n with a bump pitch L 3 of about 250 μm, suppressing thermal deformation of the metal layer 22 ₁ comprises a wiring layer 22C, it is possible to improve the reliability.

More specifically, using Equations (1) to (3), H = 15 μm, α = 16.6 × 10 ⁻⁶ / ° C., T = 400 ° C., T _a = 27 ° C. When the bump pitch L3 that satisfies the conditions is calculated, a value of 250 μm> L3 is obtained. In order to use the COF wiring as the wiring of the LSI 12, by arranging the bumps 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n at a pitch of about 250 μm, thermal deformation of the copper wiring is suppressed and reliability is improved. Can be improved.

In this way, the bumps 34 ₁ , 34 ₂ , 34 ₃ ,..., 34 _n made of Au may be arranged with the bump pitch L3 derived from the equations (1) to (3). If the copper wiring layer 22C on the COF substrate 10 side and the chip of the LSI 12 come into contact at a place other than the bumps 34 ₁ , 34 ₂ , 34 ₃ ... 34 _n made of Au, the surface of the LSI 12 may be mechanically damaged, Malfunctions may occur due to incorrect electrical connection. In the semiconductor integrated circuit device 8 according to the present embodiment, as illustrated in FIG. 6, the bumps 34 ₁ , 34 ₂ , 34 _{3 ,.} By arranging this, it is possible to achieve improvement in design quality and cost reduction with a minimum amount of Au used.

(Method for manufacturing semiconductor integrated circuit device)
In the method for manufacturing the semiconductor integrated circuit device 8 according to the embodiment, a schematic cross-sectional structure for explaining the process of forming the bumps 34 ₁ ... 34 _n on the LSI 12 is as shown in FIG. A schematic cross-sectional structure shown and explaining the process of preparing the COF substrate 10 is expressed as shown in FIG. A schematic cross-sectional structure for explaining the crimping process between the LSI 12 and the COF substrate 10 is expressed as shown in FIG. 8A, and the process for sealing the COF substrate 10 and the LSI 12 with the resin layer 13 will be explained. A schematic cross-sectional structure is expressed as shown in FIG.

The bumps 34 ₁ ,..., 34 _n are arranged on the LSI 12 with a bump pitch L3 derived from the equations (1) to (3). The bumps 34 ₁ ,..., 34 _n are formed of a material (for example, Au) smaller than the thermal conductivity of Cu constituting the COF wiring pattern.

  On the other hand, as shown in FIG. 7B, a COF substrate 10 is prepared. More specifically, a metal layer 22 composed of a metal layer (Sn) 22S and a copper wiring layer 22C is formed on the COF substrate 10. The copper wiring layer 22C is formed on the COF substrate 10, and the metal layer (Sn) 22S is formed on the copper wiring layer 22C.

Next, the LSI 12 is mounted on the COF substrate 10 so that the bumps 34 ₁ ... 34 _n on the LSI 12 are connected to the metal layer (Sn) 22S. More specifically, as shown in FIG. 8A, the heater 40 is used to apply heat to the metal layer 22 (22S / 22C) via the LSI 12, and the metal layer 22S on the copper wiring layer 22C. by melting of Sn, by alloying the Au bump 34 ₁ · ... · 34 _n and Sn, an alloy of the metal layer 22S gold bump 34 ₁ · ... · 34 _n on the copper wiring layer 22C Bonding layers (Sn—Au alloy layers) 35 ₁ ... 35 _n are formed. As a result, the LSI 12 and the COF substrate 10 are thermocompression bonded.

  Next, as shown in FIG. 8B, the heater 40 used for heating is removed, and the COF substrate 10 and the LSI 12 are sealed with a resin layer 13.

  According to the embodiment, in an IC or LSI in which a COF package is used, a semiconductor integrated circuit device that uses a COF wiring to reduce the impedance of the IC wiring and reduces noise current and heat flow in the IC or LSI, and its manufacture A method can be provided.

(Modification 1)
In the semiconductor integrated circuit device 8 according to a modification 1 of the embodiment, the connection of the grounding bump GBMP and dummy bumps DB1 · DB2 · DB3 · DB4 · ... · arrangement of DBn bumps and the metal layer 22 ₃ is disposed LSI12 A schematic planar structure for explaining the non-connection relationship is expressed as shown in FIG. 9, and a schematic cross-sectional structure along the line II-II in FIG. 9 is expressed as shown in FIG.

  For example, when COF wiring is used for the purpose of reducing the impedance of GND power wiring, the distance between the ground bumps GBMP cannot be shortened due to the layout restrictions of the GND terminal of the LSI 12, as shown in FIGS. There is. In this case, in order to suppress bending of the COF wiring, dummy bumps DB1, DB2, DB3, DB4,. The distance between the ground bump GBMP, the dummy bumps DB1, DB2, DB3, DB4,..., DBn, and the ground bump GBMP is arranged at the bump pitch L3.

Dummy bumps DB1 · DB2 · DB3 · DB4 · ... · DBn , in order to dissipate heat generated from the LSI 12 to the outside through the metal layer 22 _3, although in contact with the surface and the metal layer 22 ₃ of LSI 12, LSI internal electrode It is not connected to the layer (Al layer) 50.

On the other hand, the grounding bump GBMP, together are arranged in connection to the metal layer 22 ₃ which connects the LSI 12 and the GND terminal, LSI internal electrode layers via the contact layer 50C formed in the LSI 12 (Al Layer) 50.

Thus, even when the distance between the ground bumps GBMP cannot be shortened, the distance between the ground bumps GBMP, the dummy bumps DB1, DB2, DB3, DB4,. by arranging, as a result suppresses the contact between the metal layer 22 ₃ and LSI 12, it is possible to improve the reliability.

  According to the semiconductor integrated circuit device according to the first modification of the embodiment, it is possible to provide a semiconductor integrated circuit device that uses a COF copper wiring to reduce the impedance of the IC wiring and reduces noise current and heat flow in the IC and LSI. Can do.

(Modification 2)
In the semiconductor integrated circuit device 8 according to the second modification of the embodiment, the schematic planar structure for explaining the arrangement configuration of the bumps BMP1, BMP2, BMP3, BMPn-1, BMPn and the dummy bump DB arranged on the LSI 12 is shown in FIG. Represented as shown.

  In the example shown in FIG. 11, a plurality of dummy bumps DB are interposed between the bumps BMP1 and BMP2, between the bumps BMP2 and BMP3, and between the bumps BMPn-1 and BMPn. Has been. However, in the example shown in FIG. 11, three dummy bumps DB are arranged between the bumps BMP, but the number of dummy bumps DB interposed between the bumps BMP may be two or less, or four or more. Further, the same number of dummy bumps DB may not be arranged between the bumps BMP.

  As described above, in the semiconductor integrated circuit device according to the second modification of the embodiment, by arranging a plurality of dummy bumps between the bumps, the contact between the metal layer between the bumps and the LSI is suppressed, and the reliability is improved. can do.

  Further, in the semiconductor integrated circuit device 8 according to the first and second modifications, a schematic cross-sectional structure for explaining the connection relationship between the bump BMP1 arranged on the LSI 12 and the LSI built-in electrode layer (Al layer) 50 is shown in FIG. A schematic cross-sectional structure, which is represented as shown in (a) and explains the non-connection relationship between the dummy bump DB disposed on the LSI 12 and the LSI built-in electrode layer (Al layer) 50, is as shown in FIG. expressed.

  As shown in FIG. 12A, the bump BMP1 is connected to an LSI built-in electrode layer (Al layer) 50 formed inside the LSI 12 through an opening of the insulating layer 60 formed on the LSI 12. The bump BMP1 may be connected to the LSI built-in electrode layer (Al layer) 50 via the contact layer 50C as shown in FIG.

  On the other hand, the dummy bump DB is in contact with the LSI 12 through the opening of the insulating layer 60 formed on the LSI 12 as shown in FIG. 12B, but is connected to the LSI built-in electrode layer (Al layer) 50. It has not been. That is, the dummy bump DB connects the LSI 12 and the metal layer without connecting to the LSI built-in electrode layer (Al layer) 50.

  According to the semiconductor integrated circuit device according to the second modification of the embodiment, it is possible to provide a semiconductor integrated circuit device that uses a COF copper wiring to reduce the impedance of the IC wiring and reduces noise current and heat flow in the IC and LSI. Can do.

(Electronics)
The semiconductor integrated circuit device according to the embodiment and its modifications 1 and 2 can be applied to various electronic devices. A semiconductor integrated circuit device according to an embodiment is built in an electronic device such as a mobile phone, a digital camera, a video camera, a tablet terminal, a desktop computer, a printer, a television receiver, a notebook computer, an electronic toy, and various display devices. May be.

  In the above-described embodiment, the semiconductor power device may be a MOSFET that can be easily integrated. For example, other power devices such as an insulated gate bipolar transistor (IBGT), a thyristor, and a triac may be used. Applicable. In addition, other power devices such as SiC power devices, GaN power devices, heterojunction bipolar transistors, and SiGe devices are also applicable.

  As described above, according to the present embodiment, in an IC or LSI in which a COF package is used, the COF wiring is used to reduce the impedance of the IC wiring, and noise current and heat flow in the IC or LSI are reduced. A semiconductor integrated circuit device, a manufacturing method thereof, and an electronic apparatus can be provided.

[Other embodiments]
Although the embodiment has been described as described above, it should be understood that the discussion and the drawings that form a part of this disclosure are illustrative and do not limit the embodiment. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, this embodiment includes various embodiments not described here.

  Since the semiconductor integrated circuit device of the present embodiment is a semiconductor integrated circuit device having a COF structure, a liquid crystal display device, a backlight control device, a liquid crystal display device (source driver, gate driver), a printing device (printer driver, piezo) It can be applied to electronic devices such as drivers), and can be applied to a wide range of application fields such as the flexible electronics field and the transparent electronics field.

8, 8 ₁ , 8 ₂ , 8 ₃ ... Semiconductor integrated circuit device 10, 10 ₁ , 10 ₂ , 10 ₃ ... COF substrate 12, 12 ₁ , 12 ₂ , 12 ₃ ... Semiconductor integrated circuit (LSI)
13 ... resin layer 15 _1, 15 ₂ ... power terminal 16 _1, 16 ₂ ... power wiring layer 17 ... input signal wiring group 18 ... input signal terminals 19 ... output signal wiring group 20 ... output signal terminals 22 ... Metal layer (22S / 22C)
22S ... Metal layer (Sn)
22C ... Copper wiring layer 22 ₁ ... V _DD power metal layer 22 ₂ ... V _CC power metal layer 22 ₃ ... GND power metal layers 30, 30 ₁ , 30 ₂ , 30 ₃ , ..., 30 _n , 32, 32 _{1, 32 2, 32 3,} ..., 32 n, 34,34 1, 34 2, 34 3, ..., 34 n, BMP, BMP1, BMP2, BMP3, BMPn-1, BMPn ... bumps 35 _1, 35 ₂ ,..., 35 _n ... Bonding layer (Sn—Au alloy layer)
37, 38 ... micro bump 40 ... heater 50 ... LSI built-in electrode layer (Al layer)
50C ... Contact layer 60 ... Insulating layer 100 ... Film 100H ... Film hole GBMP ... Ground bump DB, DB1, DB2, DB3, DB4, ..., DBn ... Dummy bumps L1, L2 ... Wiring length L3 ... Bump pitch

Claims (19)

A COF substrate;
A metal layer formed on the COF substrate and connected to the outside;
A semiconductor integrated circuit mounted on the metal layer;
A bump disposed between the semiconductor integrated circuit and the metal layer, and connecting the semiconductor integrated circuit and the metal layer;
The semiconductor integrated circuit device according to claim 1, wherein the bumps are arranged at a bump pitch that prevents the metal layer from contacting the semiconductor integrated circuit when the metal layer is thermally deformed.   The semiconductor integrated circuit device according to claim 1, wherein the metal layer includes a copper wiring layer formed on the COF substrate and an Sn layer formed on the copper wiring layer.   The semiconductor integrated circuit device according to claim 1, wherein the metal layer includes a power wiring that connects the semiconductor integrated circuit and a power terminal.   The semiconductor integrated circuit device according to claim 1, wherein the metal layer includes an output signal wiring that connects the semiconductor integrated circuit and an output signal terminal.   The semiconductor integrated circuit device according to claim 1, wherein the metal layer includes an input signal wiring that connects the semiconductor integrated circuit and an input signal terminal.   The bump pitch is set so that a curve height after thermal expansion of the copper wiring layer is less than a distance between the semiconductor integrated circuit and the metal layer. Semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 1, wherein the bump includes Au.   8. The semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit and the metal layer are connected by alloying the Sn layer and the bump with Au. An LSI built-in electrode layer is provided in the semiconductor integrated circuit,
2. The semiconductor integrated circuit device according to claim 1, wherein the bump is connected to the metal layer and is connected to the LSI built-in electrode layer.   The semiconductor integrated circuit device according to claim 9, wherein the bump is connected to the LSI built-in electrode layer through a contact layer.   11. The semiconductor integrated circuit device according to claim 9, wherein the bump is connected to the LSI built-in electrode layer through an opening of an insulating layer formed on the semiconductor integrated circuit.   The semiconductor device further comprises a dummy bump that is disposed between the semiconductor integrated circuit and the metal layer and connects the semiconductor integrated circuit and the metal layer without being connected to the LSI built-in electrode layer. Item 12. The semiconductor integrated circuit device according to any one of Items 9 to 11.   13. The semiconductor integrated circuit device according to claim 12, wherein the dummy bumps are arranged at a bump pitch at which the metal layer does not contact the semiconductor integrated circuit when the metal layer is thermally deformed.   The semiconductor integrated circuit device according to claim 1, wherein the bump serves as both an electrical connection and a heat dissipation path.   The semiconductor integrated circuit device according to claim 12, wherein the dummy bump is a heat dissipation path.   The semiconductor integrated circuit device according to claim 1, further comprising a resin layer that seals the COF substrate and the semiconductor integrated circuit. Forming a bump made of Au on a semiconductor integrated circuit;
Forming a metal layer composed of an Sn layer and a copper wiring layer on the COF substrate;
Heat is applied to the metal layer through the semiconductor integrated circuit to melt the Sn of the Sn layer, and the Au of the bump and Sn of the Sn layer are alloyed to form the semiconductor integrated circuit And thermocompression bonding the COF substrate and
The method of manufacturing a semiconductor integrated circuit device, wherein the bumps are arranged at a bump pitch that does not contact the semiconductor integrated circuit when the metal layer is thermally deformed.   18. The method of manufacturing a semiconductor integrated circuit device according to claim 17, further comprising a step of sealing the COF substrate and the semiconductor integrated circuit with a resin layer.   An electronic apparatus comprising the semiconductor integrated circuit device according to claim 1.

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