JP2005259924A - Semiconductor device, mounting structure thereof, electronic equipment and display apparatus equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve electric reliability having a structure where a bare chip semiconductor device is face-down mounted on a circuit board. <P>SOLUTION: A semiconductor device 10 is the bare chip semiconductor device face-down mounted on the circuit board via an anisotropic conductive layer. The semiconductor device 10 comprises a semiconductor substrate 1 having a principal surface including four sides 1a to 1d; a plurality of bump electrodes 2 provided in a peripheral region of the principal surface of the semiconductor substrate and arranged in the vicinity of at least one side among the four sides along the at least the one side; and at least one dummy bump 3 provided to face at least one side while sandwiching at least partial bump electrodes 2 among the plurality of the bump electrodes 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, a mounting structure of the semiconductor device, an electronic apparatus including the semiconductor device, and a display device.

  In recent years, thin display devices such as liquid crystal display devices and organic EL display devices have been widely used as display devices such as mobile phones. These thin display devices include a display panel and a drive circuit (typically a drive IC) for supplying drive signals to the display panel. The display panel has at least one transparent substrate, and the drive IC is often configured to be mounted on the transparent substrate.

  For example, a TFT-type liquid crystal display device includes a pixel electrode provided for each pixel on a transparent substrate, at least one TFT provided for each pixel electrode, and a signal line (source bus) connected to the pixel electrode via the TFT. Line) and a scanning IC (gate bus line) connected to the TFT to control the switching of the TFT, and a driving IC for supplying a predetermined signal (data signal or scanning signal) to the signal line or the scanning line Is mounted on a transparent substrate.

  Conventionally, a structure using a TCP (Tape Carrier package) has been widely used as a mounting structure of a driver IC. However, in recent years, from the viewpoint of low cost, high reliability, thinning, and the like, a glass substrate of a liquid crystal panel In addition, a COG (Chip On Glass) system in which a driver IC is mounted on a bare chip has been used.

  Even in the COG method, a bump electrode is formed on a surface (circuit formation surface) on which a circuit of a semiconductor substrate of a driving IC is formed, and the bump electrode is formed on a pad (scanning line or A so-called face-down mounting structure that is connected to a terminal electrode of a signal line or a bonding pad is generally used.

  In addition, as a specific connection method of the COG method, a bump electrode of a driving IC is formed by solder, and this is melted and connected to a pad on a glass substrate, or a bump electrode is formed of a metal such as Au. In addition, there is a method of connecting to a pad through a conductive resin layer. In particular, an anisotropic conductive layer as a conductive resin layer has conductivity in the thickness direction, but does not have conductivity in the in-layer direction, so there is no need to pattern the conductive layer, and anisotropic conductive layer. The bump electrode and the pad facing each other can be electrically connected to each other through the layer. Further, since the resin material (adhesive) is filled between adjacent connections, the insulation reliability is excellent. The anisotropic conductive layer is formed using an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

  The face-down mounting structure in the liquid crystal display device will be described with reference to FIGS. 4 is the liquid crystal display device 100 according to the embodiment of the present invention including the semiconductor device 10 according to the present invention, but a conventional semiconductor device (for example, the semiconductor of FIG. 6) is used instead of the semiconductor device 10. When the device 70) is mounted, it is substantially the same as a conventional liquid crystal display device, and will be described here with reference to FIGS.

  As schematically shown in FIG. 4, the liquid crystal display device 100 includes a liquid crystal panel (display panel) 20 and a driving IC 10 mounted on a frame region 20 b (region where the TFT substrate 23 is exposed) of the liquid crystal panel 20. The driver IC 10 includes an FPC 15 for supplying predetermined signals (such as a data signal and a scanning signal) and a power supply voltage.

  As described above, the TFT substrate 23 has pixel electrodes, TFTs, signal lines, scanning lines (all not shown), and pads 22 (FIG. 5) in an area corresponding to the display area 20a of the liquid crystal panel 20. In accordance with a signal input from the pad 22, a predetermined voltage is applied to a liquid crystal layer (not shown) at a predetermined timing.

  The liquid crystal layer is provided between a TFT substrate 23 and a counter substrate (not shown) disposed so as to face the TFT substrate 23. The liquid crystal layer is formed on the counter substrate so as to face the pixel electrode through the liquid crystal layer. A counter electrode (not shown) is formed. The counter electrode is connected to a common wiring on the TFT substrate via a transfer electrode called transfer, and a common voltage is also supplied from the driving IC 10.

  FIG. 5 is a diagram schematically showing a part of a cross section taken along line 5A-5A 'in FIG.

  The drive IC 10 is fiss-down mounted on the TFT substrate 23 via the anisotropic conductive layer 30. The drive IC 10 has bump electrodes 2 on the circuit formation surface of the semiconductor substrate 1, and the TFT substrate 3 has pads 22 formed on the glass substrate 21. The bump electrode 2 and the pad 22 are electrically connected to each other by sandwiching the conductive particles 32 in the anisotropic conductive layer 30. The resin material (adhesive) in the anisotropic conductive layer 30 mechanically joins the driving IC 10 to the TFT substrate 23 and also makes an adjacent electrical connection (electrical connection between the pair of bump electrodes 2 and the pad 22). Isolate the connections).

  In recent years, the arrangement pitch has been reduced (narrow pitch) in order to cope with the increase in output and size of semiconductor devices. The arrangement of bump electrodes of a conventional driver IC with a narrow pitch will be described with reference to FIG.

  In the conventional drive IC 70 (semiconductor device) shown in FIG. 6, the bump electrode 72 is arranged in a peripheral region where a circuit (not shown) on the circuit formation surface (main surface) of the semiconductor substrate 71 is not formed. That is, a circuit is formed in the central portion where the bump electrode 72 is not formed, and the first side 71a, the second side 71b, and the third side 71c of the main surface of the substrate 71 are avoided, avoiding the region where the circuit is formed. , And a bump electrode 72 is formed in each peripheral region near the fourth side 71d.

  The face-down mounting structure described above is formed using ACF as follows, for example.

  As shown in FIG. 7, first, the ACF 30 is pressure-bonded to a region on the TFT substrate 91 where the pad 92 is formed. Next, the pad 92 of the TFT substrate 91 and the bump electrode 82 of the driving IC 80 are aligned, and thereafter, the thermocompression bonding is performed by the crimping tool 60 from the driving IC 80 side.

By being thermocompression bonded, the conductive particles 32 sandwiched between the pad 92 and the bump electrode 82 are elastically deformed (flattened) in the thickness direction, and the surrounding insulating adhesive 34 is cured, It will be fixed while maintaining the deformed state. As a result, the pad 92 and the bump electrode 82 are electrically connected. The cured insulating adhesive 34 also realizes mechanical connection between the TFT substrate 90 and the driving IC 80. A method of electrically connecting the pad 92 and the bump electrode 82 by elastically deforming the conductive particles 32 as described above is described in Patent Document 1, for example.
JP-A-10-206874

  However, when the above mounting method using an anisotropic conductive layer is employed, a short circuit may occur between adjacent bump electrodes.

  The mechanism by which this short circuit occurs will be described with reference to FIGS.

  The mounting method includes a step of bonding the driving IC 70 to the anisotropic conductive layer after the anisotropic conductive layer is attached to the region where the pad 92 is formed on the TFT substrate 91. If bubbles exist in the anisotropic conductive layer in the step of thermocompression bonding the driving IC 70 to the anisotropic conductive layer, the bubbles in the anisotropic conductive layer (not shown) move as shown in FIG. The bubble 5 moves from the central portion of the circuit formation surface toward the peripheral region (towards the sides 71a, 71b, 71c, and 71d of the circuit formation surface).

  The bubbles 5 may be generated between the TFT substrate and the anisotropic conductive layer 30 when the anisotropic conductive layer 30 is attached to a predetermined region of the TFT substrate, for example. In some cases, the insulating adhesive 34 is originally contained.

  FIG. 9 is a diagram schematically showing a part 9A of FIG. When the bubbles 5 move, the conductive particles 32 aggregate at the interface between the insulating adhesive 34 and the bubbles 5, and when the bubbles 5 reach between the adjacent bump electrodes 72 as shown in FIG. The bump electrodes 72 adjacent to each other through the conductive particles 32 may be electrically connected and may be short-circuited. This short circuit is more likely to occur as the arrangement pitch of the bump electrodes 72 is further reduced. Moreover, even if a short circuit does not occur, electrical reliability may be caused.

  Here, the mounting structure of the driving IC and the TFT substrate in the liquid crystal display device is illustrated, but in recent years, regardless of the liquid crystal display device, high definition is required for the display device in general, and this high definition is supported. For this reason, the pitch of the bump electrode 82 and the pad 92 is being reduced. Therefore, the above problem is a common problem when face-down mounting a bare chip semiconductor device (for example, an IC chip or an LED chip) on a circuit board.

  The present invention has been made in view of the above-described points, and its main object is to improve the electrical reliability of a structure in which a bare chip type semiconductor device is mounted face-down on a circuit board.

  A semiconductor device of the present invention is a bare chip type semiconductor device mounted face-down on a circuit board via an anisotropic conductive layer, the semiconductor substrate having a main surface including at least four sides, and the semiconductor substrate A plurality of bump electrodes provided in a peripheral region of the main surface and arranged along the at least one side in the vicinity of at least one of the at least four sides; And at least one dummy bump provided so as to face the at least one side with at least a part of the bump electrode interposed therebetween.

  In one embodiment, the at least some of the bump electrodes include a first bump electrode group including bump electrodes arranged with an adjacent interval of 0.1 mm or less.

  It is preferable that at least a surface of the at least one dummy bump is formed of an insulating material.

  The distance between the at least one dummy bump and the bump electrode closest to the at least one dummy bump among the plurality of bump electrodes is preferably in the range of 10 μm to 100 μm.

  The height of the at least one dummy bump from the main surface of the semiconductor substrate is preferably substantially equal to the height of the plurality of bump electrodes from the main surface.

  In one embodiment, the plurality of bump electrodes includes a second bump electrode group including bump electrodes arranged with an adjacent interval exceeding 0.1 mm, and the at least some bump electrodes include the second bump electrode group. Not included.

  In one embodiment, the at least one side includes four sides, the at least one dummy bump includes four dummy bumps provided to face the four sides, and the four dummy bumps are integrally formed. And surrounds the central region of the main surface.

  According to another aspect of the present invention, there is provided a mounting structure for a semiconductor device including the semiconductor device and a circuit board, wherein the semiconductor device is mounted face down on the circuit board through the anisotropic conductive layer. .

  An electronic apparatus according to the present invention includes the mounting structure of the semiconductor device.

  A display device according to the present invention includes the above semiconductor device mounting structure, and the circuit board is a transparent substrate.

  The semiconductor device of the present invention is a bare chip type semiconductor device that is mounted face-down on a circuit board via an anisotropic conductive layer, and is arranged along a side of the main surface in a peripheral region of the main surface of the semiconductor substrate. Since it has a bump electrode and a dummy bump provided so as to face the side of the main surface across the bump electrode, bubbles generated in the central portion of the main surface in the anisotropic conductive layer are dammed by the dummy bump. It is stopped and does not move to the peripheral area where the bump electrode is formed. Therefore, a short circuit between adjacent bump electrodes can be prevented, and the electrical reliability of the mounting structure can be increased.

  According to the present invention, a semiconductor device having a high electrical connection reliability when mounted face down on a circuit board and a mounting structure of the semiconductor device are provided. Furthermore, by applying the mounting structure according to the present invention to a display device, it is possible to obtain a display device having high electrical reliability and a small frame area and high added value. Needless to say, the present invention is not limited to a display device such as a liquid crystal display device, and the size and reliability of various electronic devices can be improved.

  A mounting structure in a liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.

  The liquid crystal display device 100 shown in FIGS. 4 and 5 is different from the conventional liquid crystal display device in that it includes the semiconductor device 10 according to the embodiment shown in FIG. Since the basic configuration of the liquid crystal display device 100 has been described above, redundant description is omitted here.

  The configuration of the semiconductor device 10 will be described with reference to FIG. FIG. 1 is a plan view schematically showing a circuit formation surface (also referred to as a main surface) of the semiconductor device 10.

  As shown in FIG. 1, the semiconductor device 10 is a bare chip semiconductor device having a plurality of bump electrodes 2 on a circuit formation surface of a semiconductor substrate 1. The configuration of the bump electrode 2 and the arrangement of the bump electrode 2 on the circuit formation surface are the same as those of the conventional semiconductor device 70 shown in FIG. The semiconductor device 10 of this embodiment is characterized by having dummy bumps 3 provided so as to face the sides 1a, 1b, 1c and 1d of the circuit formation surface with the bump electrode 2 interposed therebetween.

  The operation of the present invention will be described below with reference to FIG. FIG. 2 is a diagram schematically showing a part 2A of the circuit formation surface of the semiconductor device 10 shown in FIG.

  In the step of thermocompression bonding the semiconductor device 10 to the anisotropic conductive layer 30 (see FIG. 7), the bubbles 5 present in the central portion of the circuit forming surface in the anisotropic conductive layer 30 are directed from the central portion toward the peripheral region. Move. However, since the semiconductor device 10 has the dummy bumps 3, the bubbles 5 are blocked by the dummy bumps 3 as shown in FIG. 2 and do not move to the peripheral region where the bump electrodes 2 are formed. For this reason, since the bubbles 5 can hardly reach between the adjacent bump electrodes 2, the aggregation of the conductive particles 32 between the adjacent bump electrodes 2 can be suppressed, and the electrical reliability of the mounting structure can be improved as compared with the conventional case. Can increase the sex. Moreover, since a short circuit can be prevented, the yield can be increased.

  Hereinafter, the semiconductor device 10 will be described more specifically with reference to FIG.

  The circuit formation surface of the semiconductor substrate 1 is substantially rectangular, for example, and has a first side 1a, a second side 1b, a third side 1d, and a fourth side 1e. The bump electrode 2 is arranged along each side in each peripheral region provided in the vicinity of each side from the first side 1a to the fourth side 1e. For example, bump electrodes 2a are arranged along the first side 1a in the peripheral region provided in the vicinity of the first side 1a. Here, the bump electrode 2a arranged along the first side 1a may be referred to as a first bump electrode. Similarly, the bump electrodes 2 arranged along the second side 1b are referred to as second bump electrodes 2b, the bump electrodes 2 arranged along the third side 1c are referred to as third bump electrodes 2c, The bump electrodes 2 arranged along the four sides 1d may be referred to as fourth bump electrodes 2d.

  A dummy bump 2 is formed inside each of the first bump electrode 2a, the second bump electrode 2b, the third bump electrode 2c, and the fourth bump electrode 2d. The dummy bumps corresponding to the first bump electrode 2a, the second bump electrode 2b, the third bump electrode 2c, and the fourth bump electrode 2d are respectively the first dummy bump 3a, the second dummy bump 3b, the third dummy bump 3c, and the fourth dummy bump 3d. Called. The first dummy bump 3a is provided so as to face the first side 1a with the first bump electrode 2a interposed therebetween, and the second dummy bump 3b is made to face the second side 1b with the second bump electrode 2a interposed therebetween. Is provided. Similarly, the third dummy bump 3c and the fourth dummy bump 3d are provided so as to face the third side 1c and the fourth side 1d, respectively, with the third dummy bump 3c and the fourth dummy bump 3d interposed therebetween.

  As shown in FIG. 1, if the first dummy bump 3a, the second dummy bump 3b, the third dummy bump 3c, and the fourth dummy bump 3d are integrally formed to surround the central region of the main surface of the substrate 1, the bubbles 5 are formed by dummy bumps. Since it can be confined in the enclosed region, it is possible to more effectively suppress the bubbles 5 from moving to the peripheral region where the bump electrode 2 is formed.

  It is preferable that at least the surface of the dummy bump 3 is formed of an insulating material. This is because the adjacent bump electrodes 2 are prevented from being short-circuited via the dummy bumps 2 and the conductive particles 32. The dummy bump 3 can be formed, for example, by using the same conductive material as the bump electrode 2 and forming a convex portion having a predetermined shape in the same process as the bump electrode 2 and then coating the surface of the convex portion with a resin or the like. . Of course, it may be formed of a single insulating layer.

  The distance d (FIG. 2) between the dummy bump 3 and the bump electrode 2 is preferably 10 μm or more and 100 μm or less. If the distance d is 10 μm or more, even if the dummy bump 3 does not have sufficient insulation, the dummy bump 3 and the bump electrode 2 are short-circuited via the conductive particles 32 aggregated in a daisy chain. This can be sufficiently prevented. In order to prevent bubbles from being generated between the dummy bump 3 and the bump electrode 2, it is preferable to set the distance d to 100 μm or less.

  The height of the dummy bump 3 from the main surface of the semiconductor substrate 1 is preferably substantially the same as the height of the bump electrode 2 from the main surface of the semiconductor substrate 1. If the height of the dummy bump 3 is smaller than the height of the bump electrode 2, the bubbles 5 generated at the central portion of the main surface of the substrate 71 of the anisotropic conductive layer 30 are not sufficiently blocked by the dummy bump 3, and the bump electrode 2 is This is because there is a risk of moving to the formed peripheral region. Specifically, the height of the bump electrode 2 is, for example, about 12 μm to 15 μm, and the height of the dummy bump 3 is equal to or less than the height of the bump electrode 2. The width W (FIG. 2) of the dummy bump 3 is preferably 15 μm or less because air bubbles are likely to be generated from the location when the width of W is increased.

  When the pitch P between adjacent bump electrodes 2 is reduced to 0.1 mm or less, a short circuit is likely to occur. The semiconductor device 10 of this embodiment is particularly effective for short-circuiting a semiconductor device with a narrow pitch.

  For example, when bump electrodes 2 having different adjacent intervals P are formed on the main surface of the substrate 1 of the semiconductor device 10, dummy bumps are selectively formed on the bump electrodes 2 having an adjacent interval P of 0.1 mm or less. Also good. Hereinafter, a description will be given with reference to FIGS. 3 (a), (b) and (c).

  In the semiconductor device 10a shown in FIG. 3A, for example, the first bump electrode 2a having an adjacent interval P1a of 0.05 mm and an adjacent interval P1b (P1b> P1a) of 0.05 mm is formed on the first side 1a of the substrate 1. A second bump electrode 2b having a peripheral region and a second bump electrode 2b having an adjacent interval P2 of 0.08 mm in a peripheral region of the second side 1b of the substrate 1 and a third bump electrode 2c having an adjacent interval P3 of 0.2 mm being a substrate 1 And a fourth bump electrode 2d having an adjacent interval P4 of 0.2 mm in the peripheral region of the fourth side 1d. That is, bump electrodes having an adjacent interval of 0.1 mm or less are provided in the peripheral region of the first side 1a, the second side 1b, and the third side 1c, but are not provided in the peripheral region of the fourth side 1c.

  The semiconductor device 10a includes dummy bumps provided along the first side 1a, the second side 1b, and the third side 1c corresponding to the first bump electrode 2a, the second bump electrode 2, and the third bump electrode 2c, respectively. 3 but no dummy bump 3 corresponding to the fourth bump electrode 2d. That is, the dummy bumps are selectively arranged along the sides having the bump electrodes having an adjacent interval of 0.1 mm or less.

  The semiconductor device 10b shown in FIG. 3B is shown in that the adjacent interval P3 of the third bump electrode 2c is 0.2 mm (≧ 0.1 mm), and there is no dummy bump 3 corresponding to the third bump electrode 2c. Different from the semiconductor device 10a shown in FIG.

  The dummy bumps 3 do not have to be integrally formed along one side of the substrate 1, and a plurality of dummy bumps may be provided along one side.

  In the semiconductor device 10c shown in FIG. 3C, when the adjacent distance between the first bump electrodes 2a is 0.05 mm (P1a) and 0.3 mm (P1b), the adjacent distance is P1a in the vicinity of the first side 1a. The dummy bumps 3 are selectively arranged so as to correspond only to the first bump electrode 2a (≦ 0.1 mm).

  As illustrated in FIGS. 3A to 3C, dummy bumps may be provided corresponding to bump electrodes that may cause a short circuit due to at least aggregated fine particles, and the shape, size, and arrangement of dummy bumps are designed. Has a high degree of freedom. Further, connection reliability can be improved by appropriately changing the shape, size and arrangement of the dummy bumps.

  In general, if the configuration of the bonding surface is not uniform, the bonding reliability may be reduced. For example, if the total area of the bump electrodes formed along one side of the substrate 1 is different from the total area of the bump electrodes formed along the other side, a difference occurs in the adhesive strength and the connection reliability. May decrease. In such a case, by changing the shape, size, and arrangement of the dummy bumps as appropriate, the uniformity of the surface configuration of the substrate 1 can be improved and the connection reliability can be improved. Here, the difference in the area of the bump electrode is illustrated, but the size, pitch, etc. of the bump electrode may affect the connection reliability. Therefore, the shape, size, and arrangement of the dummy bump should be designed in consideration of these. That's fine.

  If the dummy bumps 3 are formed as shown in FIG. 1, there is an advantage that the design is easy.

  In the above description, the case where the main surface of the semiconductor substrate 1 is rectangular has been described, but the shape of the main surface is not limited thereto. The anisotropic conductive layer 30 is formed using an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

  The drive IC of this embodiment can be mounted by the process described with reference to FIG.

  First, the ACF 30 is pressure-bonded on the TFT substrate 23, and then the TFT substrate 23 and the driving IC 10 are aligned. Thereafter, heat pressure bonding is performed by the pressure bonding tool 60 from the drive IC 10 side. The pressure bonding conditions are, for example, a temperature of 170 ° C. to 190 ° C., a pressing force of 70 MpPa to 90 MPa, and a pressing time of 8 seconds to 12 seconds. As a result, the ACF 10 is cured (thermal curing), and the drive IC 10 is mounted on the TFT substrate 23.

  The conductive particles 32 sandwiched between the pad electrode 92 and the bump electrode 82 are elastically deformed (flattened) in the thickness direction by being heat-pressed, and the surrounding insulating adhesive 34 is cured. Thus, it is fixed while maintaining the deformed state. As a result, an electrical connection between the pad electrode 92 and the bump electrode 82 is formed, and a mechanical connection between the TFT substrate 23 and the driving IC 10 is also realized by the cured insulating adhesive 34.

  When the semiconductor device 10 according to the embodiment of the present invention is used, even if the bubbles 5 are present in the anisotropic conductive layer 30 in the central portion of the main surface of the substrate 1, as shown in FIG. Since the dummy bumps 3 are arranged corresponding to the bump electrodes 2 provided in the region, the bubbles 5 are blocked by the dummy bumps 3 and do not move to the bump electrodes 2 in the peripheral region. Therefore, an electrical short circuit between adjacent terminals caused by the presence of the bubbles 5 can be prevented. For this reason, it is possible to efficiently arrange a large number of bump electrodes while ensuring the reliability of electrical connection.

  In the above embodiment, the present invention has been described by taking the mounting structure in the liquid crystal display device as an example. However, the present invention is not limited to the above-described example, and a bare chip semiconductor device (for example, an IC chip or an LED chip) is mounted on the circuit board. This can be widely applied to down-mounted structures, and has the effect of improving connection reliability.

  In JP-A-11-354564, the number of conductive particles existing between a bump electrode and a pad by making the bump electrode a predetermined shape in a mounting structure using an anisotropic conductive layer. Discloses a semiconductor device that increases the number of. However, the invention disclosed in the above-mentioned patent document does not even mention that bubbles existing in the anisotropic conductive layer affect the electrical reliability.

  The semiconductor device of the present invention can be widely used in display devices such as liquid crystal display devices and other various electronic devices.

It is the top view which showed typically the circuit formation surface of the semiconductor device 10 of embodiment by this invention. FIG. 2 is a diagram schematically showing a part 2A of a circuit formation surface of the semiconductor device 10 shown in FIG. (A), (b) and (c) are the top views which showed typically the circuit formation surface of the semiconductor device of other embodiment by this invention. It is a top view which shows typically the mounting structure in the liquid crystal display device 100 of embodiment by this invention. It is sectional drawing of the liquid crystal display device 100 of FIG. It is the top view which showed typically the circuit formation surface of the conventional semiconductor device 70. FIG. It is typical sectional drawing for demonstrating the process which mounts drive IC in a liquid crystal panel. It is the top view which showed typically the circuit formation surface of the conventional semiconductor device 70. FIG. FIG. 9 is a diagram schematically showing a part 9A of a circuit formation surface of the semiconductor device 70 shown in FIG.

Explanation of symbols

1 semiconductor substrate 1a first side 1b second side 1c third side 1d fourth side 2 bump electrode 2a first bump electrode 2b second bump electrode 2c third bump electrode 2d fourth bump electrode 3 dummy bump 5 bubble 10 semiconductor substrate 10a Semiconductor substrate 10b Semiconductor substrate 10c Semiconductor substrate 21 Glass substrate 22 Pad 22
30 Anisotropic Conductive Layer 32 Conductive Particles 34 Insulating Adhesive 100 Liquid Crystal Display Device

Claims (10)

A bare chip type semiconductor device mounted face-down on a circuit board via an anisotropic conductive layer,
A semiconductor substrate having a major surface including at least four sides;
A plurality of bump electrodes arranged in a peripheral region of the main surface of the semiconductor substrate and arranged along the at least one side in the vicinity of at least one of the at least four sides;
A semiconductor device comprising: at least one dummy bump provided so as to face the at least one side across at least a part of the bump electrodes of the plurality of bump electrodes.   2. The semiconductor device according to claim 1, wherein the at least part of the bump electrodes includes a first bump electrode group including bump electrodes arranged with an adjacent interval of 0.1 mm or less.   The semiconductor device according to claim 1, wherein at least a surface of the at least one dummy bump is formed of an insulating material.   4. The distance between the at least one dummy bump and a bump electrode closest to the at least one dummy bump among the plurality of bump electrodes is in a range of 10 μm to 100 μm. 5. Semiconductor device.   5. The semiconductor device according to claim 1, wherein a height of the at least one dummy bump from the main surface of the semiconductor substrate is substantially equal to a height of the plurality of bump electrodes from the main surface.   The plurality of bump electrodes includes a second bump electrode group including a bump electrode arranged with an adjacent interval exceeding 0.1 mm, and the at least some of the bump electrodes do not include the second bump electrode group. Item 6. The semiconductor device according to any one of Items 1 to 5. The at least one side includes four sides;
The at least one dummy bump includes four dummy bumps provided to face the four sides,
The semiconductor device according to claim 1, wherein the four dummy bumps are integrally formed and surround a central region of the main surface. A semiconductor device according to any one of claims 1 to 7 and a circuit board,
The semiconductor device mounting structure, wherein the semiconductor device is mounted face-down on the circuit board via the anisotropic conductive layer.   An electronic apparatus comprising the mounting structure for a semiconductor device according to claim 8. A display device comprising the mounting structure for a semiconductor device according to claim 8, wherein the circuit board is a transparent substrate.

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