KR20170038301A - Display apparatus - Google Patents

Display apparatus Download PDF

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Publication number
KR20170038301A
KR20170038301A KR1020150137463A KR20150137463A KR20170038301A KR 20170038301 A KR20170038301 A KR 20170038301A KR 1020150137463 A KR1020150137463 A KR 1020150137463A KR 20150137463 A KR20150137463 A KR 20150137463A KR 20170038301 A KR20170038301 A KR 20170038301A
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KR
South Korea
Prior art keywords
dummy pattern
signal
integrated circuit
pad
gate
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Application number
KR1020150137463A
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Korean (ko)
Inventor
정수민
Original Assignee
엘지디스플레이 주식회사
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Priority to KR1020150137463A priority Critical patent/KR20170038301A/en
Publication of KR20170038301A publication Critical patent/KR20170038301A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes

Abstract

The present invention provides a semiconductor device comprising: a substrate including a display region having signal lines, a non-display region provided around the display region, and a chip mounting region having a signal input pad and a signal output pad connected to the signal line; A drive integrated circuit having an input bump electrically coupled to the signal input pad and an output bump electrically coupled to the signal output pad; And a level compensating unit provided between the substrate and the driving integrated circuit.

Description

Display device {DISPLAY APPARATUS}

The present invention relates to a display device.

2. Description of the Related Art In recent years, various portable electronic devices such as a mobile communication terminal, a notebook computer, and the like have been developed, and a demand for a flat panel display device that can be applied thereto is gradually increasing. As such a flat panel display device, a liquid crystal display device, a plasma display panel (PDP), a field emission display device, a light emitting diode display device However, liquid crystal display devices are attracting attention due to advantages such as mass production technology, ease of driving means, and realization of high image quality.

2. Description of the Related Art Recently, in order to secure a low cost, light weight, low power consumption and high reliability of a liquid crystal display device, there has been proposed a chip on glass type liquid crystal display device in which a plurality of gate driver integrated circuits and a plurality of data driver integrated circuits are bonded to a display panel Liquid crystal display devices have been developed and mass-produced.

1 is a schematic view for explaining a pad portion of a general chip on glass type liquid crystal display device.

1, a pad portion of a general chip-on-glass type liquid crystal display device generates a driving signal for driving a pad portion 20 formed on a substrate 10 and a liquid crystal display device, And a driving integrated circuit (30) for supplying the driving current.

The pad unit 20 includes an output pad 25 for outputting a signal to the liquid crystal display device and an input pad 27 for transmitting a signal transmitted from the outside to the output pad 25. An insulating layer 21 and a protective layer 23 are formed on the upper surface of the pad portion 20.

The driving integrated circuit 30 generates a gate signal, supplies it to the gate signal line, generates a data signal synchronized with the gate signal, and supplies the data signal to the data signal line. The driving integrated circuit 30 includes an output bump 31 electrically connected to the output pad 25 and an input bump 33 electrically connected to the input pad 27. Each of the output bump 31 and the input bump 33 is electrically connected to the output pad 25 and the input pad 27 via an ACF (Anisotropic Conductive Film) according to a TAB (Tape Automated Bonding) do.

Such a general chip-on-glass type liquid crystal display device has a gate signal and data (data) supplied from the drive integrated circuit 30 electrically connected to the pad portion 20 to the gate and data signal lines via the conductive balls of the ACF, A predetermined image is displayed according to the signal.

The stepped portion between the region where the output bump 31 and the input bump 33 of the driving integrated circuit 30 are formed and the adjacent region is generated in the structure of the pad portion as described above. Accordingly, in the conventional chip-on-glass type liquid crystal display device, the output bumps 31 and the input bumps 33 are formed in the process of bonding the drive integrated circuit 30 to the chip mounting area formed on the display panel. There is a problem that a difference in the joining force with respect to the total area occurs due to the step difference between the region and the adjacent region.

In the conventional chip-on-glass type liquid crystal display device, since the pressure for bonding is applied to the driving integrated circuit 30, a step between the region where the output bumps 31 and the input bumps 33 are formed and the step between the adjacent regions There is a problem that the driving integrated circuit 30 is damaged in the region where the driving circuit 30 is generated.

SUMMARY OF THE INVENTION It is a general object of the present invention to provide a display device capable of reducing a step between an area where an output bump and an input bump are formed and an adjacent area of the driving integrated circuit.

According to an aspect of the present invention, there is provided a display device including a display region having a signal line, a non-display region provided around the display region, a chip mounting region having a signal input pad and a signal output pad connected to the signal line, A substrate; A drive integrated circuit having an input bump electrically coupled to the signal input pad and an output bump electrically coupled to the signal output pad; And a step difference compensator provided between the substrate and the drive integrated circuit.

The display device according to the present invention has the following effects.

First, by reducing the step between the region where the output bump and the input bump of the driving integrated circuit are formed and the adjacent region, the bonding force between the substrate and the driving integrated circuit can be increased at the time of bonding the driving integrated circuit.

Secondly, by reducing the step between the region where the output bump and the input bump of the driving integrated circuit are formed and the adjacent region, it is possible to prevent the driving integrated circuit from being damaged in the region where the step is formed at the time of bonding the driving integrated circuit.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

1 is a schematic view for explaining a pad portion of a general chip on glass type liquid crystal display device.
2 is a schematic view for explaining a display device according to the present invention.
3 is a schematic view for explaining a driving integrated circuit according to the present invention.
4 to 6 are cross-sectional views showing a cross section of the line II 'shown in Fig.
7 and 8 are views for schematically explaining a display device according to a modification of the present invention.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of the display device according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 2 is a view for schematically explaining a display device according to the present invention, FIG. 3 is a view for schematically explaining a driving integrated circuit according to the present invention, and FIGS. 4 to 6 are cross- Fig.

2 and 3, a display device according to an exemplary embodiment of the present invention includes a substrate 100, a driving integrated circuit 120, and a level compensator 130.

The substrate 100 includes a display area AA for displaying an image, a non-display area NA corresponding to a remaining area except the display area AA, and a pad area PA.

The display area AA includes a plurality of gate signal lines GL and a plurality of data signal lines DL and a plurality of gate signal lines GL and a plurality of data signal lines DL And a plurality of pixels formed for each region defined by the intersection.

The pixel includes a thin film transistor connected to one gate signal line (GL) and one data signal line (DL). The pixel displays an image corresponding to the data signal supplied from the data signal line DL through the thin film transistor. For example, the pixel may be configured as a part of a liquid crystal cell that displays an image by adjusting the light transmittance of the liquid crystal in accordance with the data signal supplied from the data signal line DL through the thin film transistor. As another example, the pixel may be configured as a part of a light emitting cell that emits light according to a current corresponding to a data signal supplied from a data signal line DL through a thin film transistor to display an image.

In which the drive integrated circuit 120 for supplying a gate signal to the gate signal line GL and supplying a data signal synchronized with the gate signal to the data signal line DL is bonded to the non-display area NA, A region CA may be provided.

The pad region PA is provided on one side of the substrate 100. The driving integrated circuit 120, the flexible circuit film 200 and pad electrodes to be connected to various lines arranged on the substrate 100 may be disposed in the pad region PA.

The chip mounting area CA includes a signal output pad part OPP and a signal input pad part IPP as shown in FIG.

The signal output pad unit OPP includes first and second gate output pad units GOP1 and GOP2 and a data output pad unit DOP.

The first and second gate output pad portions GOP1 and GOP2 are formed with a data output pad portion DOP therebetween and include a plurality of signal output pads 101 electrically connected to the gate signal line GL, And a plurality of gate connection portions (GCP).

The data output pad unit DOP includes a plurality of signal output pads 101 electrically connected to the data signal lines DL.

The signal input pad unit IPP is electrically connected to the flexible circuit film 200 bonded to the substrate 100 through the input link line ILL to supply driving power, And a plurality of signal input pads 103 to which image data is supplied. The signal input pad 103 may have the same structure as the signal output pad 101 described above.

The driving integrated circuit 120 is bonded to the chip mounting area CA of the substrate 100 by an ACF (Anisotropic Conductive Film) according to a TAB (Tape Automated Bonding) (Not shown).

To this end, the driving integrated circuit 120 includes a plurality of output bumps 123 and a plurality of input bumps 121.

Each of the plurality of output bumps 123 is electrically connected to the plurality of signal output pads 101 via the conductive balls of the ACF 105. The plurality of output bumps 123 may include a plurality of gate output terminals and a plurality of data output terminals.

Each of the plurality of gate output terminals is electrically connected to a plurality of signal output pads 101 via a conductive ball of the ACF 105. At this time, the conductive balls of the ACF 105 are scattered on the contact holes and the output pad electrodes 127 by heat press according to the TAB method, so that the gate output terminals and the output pad electrodes 127 are electrically connected to each other.

Each of the plurality of data output terminals is electrically connected to the plurality of signal output pads 101 via the conductive balls of the ACF 105. At this time, the conductive balls of the ACF 105 are dispersed in the contact holes and the output pad electrodes 127 by heat press according to the TAB method, so that the data output terminals and the output pad electrodes 127 are electrically connected to each other.

Each of the plurality of input bumps 121 is electrically connected to a plurality of signal input pads 103 via conductive balls of the ACF 105. At this time, the conductive balls of the ACF 105 are scattered on the contact holes and the input pad electrodes 125 by heat press according to the TAB method, so that the input pad 101 and the input pad electrode 127 are electrically connected to each other.

The driving integrated circuit 120 drives the substrate 100 based on the driving power, the timing synchronization signal, and the image data input from the flexible circuit film 200 to the plurality of input terminals through the plurality of signal input pads 103, And generates a gate signal and a data signal for displaying an image. The driving integrated circuit 120 sequentially supplies the gate signal generated through the plurality of gate output terminals to the signal output pad 101 to drive the gate signal line GL of the substrate 100, To the plurality of signal output pads 101 connected to the data signal lines DL at the same time so as to be synchronized with the gate signal of the data signal line DL.

The step compensator 130 is provided between the substrate 100 and the driving integrated circuit 120. The step difference compensating unit 130 may be provided between the output bump 123 and the input bump 121. The step compensator 130 may be formed of at least one material selected from among Cu, Al, Mo, Ti, and Mo-Ti. The step difference compensating unit 130 compensates the height of the output bump 123, the output pad electrode 127, the input bump 121, and the input pad electrode 125, The wiring step can be compensated. The display device according to the present invention reduces the wiring level difference between the region where the output bump 123 of the driving integrated circuit 120 and the region where the input bump 121 is formed and the adjacent region, The pressing force difference due to the wiring step difference can be reduced even when pressing is performed with the same force in the process of bonding to the chip mounting area CA. Therefore, the display device according to the present invention has the effect of increasing the combined force between the substrate 100 and the driving integrated circuit 120 when the driving integrated circuit 120 is bonded.

The display device according to the present invention reduces the wiring level difference between the region where the output bump 123 and the input bump 121 of the driving integrated circuit 120 are formed and the adjacent region, It is possible to prevent the drive integrated circuit 120 from being depressed in a region where the wiring step is generated. Therefore, the display device according to the present invention has the effect of preventing the driving integrated circuit 120 from being damaged in the region where the wiring step is formed when the driving integrated circuit 120 is bonded.

As shown in FIG. 4, the level difference compensation unit 130 may include a first dummy pattern 131 and a second dummy pattern 133.

The first dummy pattern 131 is provided in a region other than a region where the signal input pad 103 and the signal output pad 101 are provided in the chip mounting area CA. For example, the first dummy pattern 131 may be provided between the signal output pad 101 and the signal input pad 103, as shown in FIG.

The second dummy pattern 133 may be formed to overlap with the first dummy pattern 131. For example, the second dummy pattern 133 may be provided on the upper side of the first dummy pattern 131. Accordingly, the display device according to the present invention can selectively form the first dummy patterns 131 and the second dummy patterns 133 in accordance with the wiring step as well as the above-described effects, The versatility can be improved.

5, the driving integrated circuit 120 may further include a signal transfer wiring 129 provided between the signal input pad 103 and the signal output pad 101.

The signal transfer wiring 129 is a wiring for processing the signals transferred from the bonding pad 201 of the flexible circuit film 200 to the signal input pad 103 in the driving integrated circuit 120, And a wiring for transferring the signal processed in the driving integrated circuit 120 to the pad of the signal output 103. The signal transfer wiring 129 may be provided between the signal input pad 103 and the signal output pad 101.

In this case, the level difference compensating unit 130 compensates the wiring level difference between the lower surface of the driving integrated circuit 120 facing the substrate 100 and the signal transfer wiring 129 facing the substrate 100 can do. For example, the level difference compensating unit 130 may compensate the wiring level difference using only the first dummy pattern 131 or may use the first dummy pattern 131 and the second dummy pattern 133, It can be implemented to compensate the wiring step difference. The first dummy pattern 131 may have the same height as the signal transfer wiring 129 when the wiring step difference is compensated using only the first dummy pattern 131. [

6, when the wiring step difference is compensated for by using both the first dummy pattern 131 and the second dummy pattern 133, the first dummy pattern 131 and the second dummy pattern 133 are formed, The sum of the thicknesses or heights D1 and D2 of each of the patterns 133 may be formed to be equal to the sum of the thickness or the height of the signal transfer wiring 129. The first dummy pattern 131 and the second dummy pattern 133 compensate the wiring step difference between the output bump 123 and the input bump 121 and the signal transfer wiring 129 .

The display device according to the present invention reduces the wiring level difference formed between the output bumps 123 of the driving integrated circuit 120 and the input bumps 121 and the signal transfer wiring 129, The pressing force difference due to the wiring step can be reduced even when the circuit 120 is pressed by the same force in the process of bonding to the chip mounting area CA. Therefore, the display device according to the present invention has the effect of increasing the combined force between the substrate 100 and the driving integrated circuit 120 when the driving integrated circuit 120 is bonded.

The display device according to the present invention further reduces the wiring step difference formed between the output bump 123 of the driving integrated circuit 120 and the signal transfer wiring 129 and the input bump 121, It is possible to prevent the driving integrated circuit 120 from being depressed in a region where the wiring step is generated upon bonding of the driving integrated circuit 120. Therefore, the display device according to the present invention has the effect of preventing the driving integrated circuit 120 from being damaged in the region where the wiring step is formed when the driving integrated circuit 120 is bonded.

Here, the insulating layer 109 and the passivation layer 107 may be formed on the pad region PA and the display region AA, and the gate electrode 111, the first and second A thin film transistor composed of the electrodes 113a and 113b and the semiconductor layer 115 may be formed.

The gate electrode 111 is connected to the gate signal line GL for each pixel. The insulating layer 109 is formed on the gate electrode 111.

The semiconductor layer 115 is formed on the upper surface of the insulating film 109.

The first electrode 113a is connected to the data signal line DL for each pixel.

The second electrode 113b is connected to the pixel electrode of each pixel. The second electrode 113b is formed on the semiconductor layer 115 at a predetermined distance from the first electrode 113a. The first and second electrodes 113a and 113b are formed by forming a source / drain electrode material on the entire surface of the insulating layer 109 and then selectively removing the source / drain electrode material formed on the non- .

In this case, the first dummy pattern 131 may be formed of the same material as the gate electrode 111. The first dummy pattern 131 may be formed of the same material as the gate electrode 111 in the process of forming the gate electrode 111 in the display area AA. The first dummy pattern 131 may be provided on the substrate 100.

The second dummy patterns 133 may be formed of the same material as the first and second electrodes 113a and 113b. The second dummy patterns 133 may be formed of the same material as the first and second electrodes 113a and 113b in the process of forming the first and second electrodes 113a and 113b in the display area AA Can be formed together.

Accordingly, the display device according to the present invention can form the insulating layer 109 and the protective layer 107 and then etch the insulating layer 109 and the protective layer 107 to form different materials, 130, it is possible to contribute to reducing the airflow.

The insulating layer 109 is formed on the pad region PA and the display region AA of the substrate 100 so as to cover the first dummy pattern 131 and the gate electrode 111. The insulating layer 109 may be formed between the first dummy pattern 131 and the second dummy pattern 133.

The protective film 107 is formed on the pad region PA and the display region AA of the substrate 100 so as to cover the second dummy pattern 133 and the first and second electrodes 113a and 113b .

7 and 8 are views for schematically explaining a display device according to a modification of the present invention.

Referring to FIG. 7, a display device according to a modification of the present invention includes at least one gate driving integrated circuit 310, a plurality of driving integrated circuits 120, and a flexible circuit film 200.

The substrate 100 includes a display area AA for displaying an image and a non-display area NA corresponding to a remaining area except for the display area AA.

The display area AA includes a plurality of pixels formed in regions defined by intersections of a plurality of gate signal lines GL and a plurality of data signal lines DL formed at regular intervals so as to intersect with each other.

The pixel includes a thin film transistor connected to one gate signal line (GL) and one data signal line (DL).

At least one gate driving integrated circuit 310 for supplying a gate signal to the gate line GL is bonded to the non-display area NA, and a data signal synchronized with the gate signal is supplied to the data signal line DL A plurality of driving integrated circuits 200 are bonded.

At least one gate driving integrated circuit 310 is connected to one side non-display area NA of the substrate 100 corresponding to one side of the gate signal line GL and sequentially supplies a gate signal to the gate signal line GL do. To this end, at least one gate integrated circuit bonding portion (not shown) is provided on one side non-display area NA of the substrate 100, and at least one gate integrated circuit bonding portion includes a gate input pad portion (not shown) And a gate output pad unit (not shown).

The gate input pad portion includes a plurality of gate output pads (not shown) electrically connected to the flexible circuit board 200 through a gate signal input line (not shown) formed on one side non-display area NA of the substrate 100 .

The gate input pad and the gate output pad are formed to have the same structure as that of the signal input pad 103 and the signal output pad 101 shown in FIGS. 4 to 6, so that a detailed description thereof will be substituted with the above description .

In each of the at least one gate integrated circuit bonding portion, the terminals of the gate driving integrated circuit 310 are bonded by the conductive balls of the ACF (not shown) according to the TAB method

The plurality of driving integrated circuits 120 are bonded to the upper non-display area NA of the substrate 100 corresponding to one side of the data signal line DL and supply the data signal to the data signal line DL. To this end, a plurality of data integration circuit bonding portions (not shown) are provided in the upper non-display area NA of the substrate 100, and each of the plurality of data integration circuit bonding portions includes a data input pad portion (not shown) And a data output pad unit (not shown).

The data input pad unit includes a plurality of data input pads (not shown) electrically connected to the flexible circuit board 200 through a data signal input line (not shown) formed in the upper non-display area NA of the substrate 100 .

The data output pad portion includes a plurality of data output pads (not shown) electrically connected to the data signal lines DL.

Since the data input pad and the data output pad are formed to have the same structure as the signal input pad 103 and the signal output pad 101 shown in FIGS. 4 to 6, the detailed description thereof will be replaced with the above description .

In each of the plurality of data-integrated circuit bonding portions, the terminals of the driving integrated circuit 120 are bonded by the conductive balls of the ACF according to the TAB method.

The flexible circuit board 200 is bonded to a plurality of printed circuit bonding pads (not shown) provided on the upper non-display area NA of the substrate 100 by the conductive balls of the ACF according to the TAB method.

The plurality of printed circuit bonding pads are electrically connected to the data input pad portions of each of the plurality of data integration circuit bonding portions via a data signal input line (not shown) formed in the upper non-display area NA of the substrate 100, And is electrically connected to the gate signal input line.

Referring to FIG. 8, a display device according to a modification of the present invention includes a substrate 100, at least one gate circuit film 410 on which the gate driving integrated circuit 310 is mounted, a data driving integrated circuit 320, A plurality of data circuit films 420, a printed circuit board 500, and a timing control unit 510. [

The substrate 100 includes a display area AA for displaying an image and a non-display area NA corresponding to the remaining area except for the display area AA.

The display area AA includes a plurality of gate signal lines GL and a plurality of data signal lines DL which are formed at regular intervals so as to intersect with each other and a plurality of gate signal lines GL and a plurality of data signal lines DL And a plurality of pixels formed for each region defined by the pixels.

The pixel includes a thin film transistor T connected to one gate signal line GL and one data signal line DL as shown in FIG.

In the non-display area NA, at least one gate driving integrated circuit 310 for supplying a gate signal to the gate signal line GL is bonded, and a data signal synchronized with the gate signal is supplied to the data signal line DL A plurality of data driving integrated circuits 320 are bonded.

The gate drive integrated circuit 310 is mounted on the gate circuit film 410 and generates and outputs a gate signal for driving the gate signal line GL under the control of the timing control unit 510. [

At least one gate circuit film 410 is bonded to a gate pad portion (not shown) formed at one side non-display area NA of the substrate 100 corresponding to one side of the gate signal line GL, 310 to the gate signal line GL. At this time, the terminal of at least one gate circuit film 410 is bonded to the gate pad portion by the conductive balls of the ACF according to the TAB method. Here, the gate circuit film 410 may be a TCP (Tape Carrier Package) or a COF (Chip On Film).

The gate pad portion includes a plurality of gate pads (not shown) formed to have the same structure as the signal output pad 101 and electrically connected to the gate signal line GL.

The data driving integrated circuit 320 is mounted on the data circuit film 420 and generates and outputs a data signal for driving the data signal line DL under the control of the timing controller 510.

Each of the plurality of data circuit films 420 is bonded to a data pad portion (not shown) formed on one side non-display area NA of the substrate 100 corresponding to one side of the data signal line DL, 320 to the data signal line GL. At this time, the terminals of each of the plurality of data circuit films 410 are bonded to the data pad portion by the conductive balls of the ACF according to the TAB method. Here, the data circuit film 420 may be TCP or COF.

The data pad unit includes a plurality of data pads (not shown) formed to have the same structure as the signal output pad 101 and electrically connected to the data signal lines DL.

The printed circuit board 500 is electrically connected to the plurality of data circuit films 420 by the conductive balls of the ACF according to the TAB method.

The timing control unit 510 generates image data corresponding to an input image that is mounted on the printed circuit board 500 and supplied from the outside and transmits the generated image data to the printed circuit board 500 and the data circuit film 420 And supplies it to the data driving integrated circuit 320.

In addition, the timing controller 510 controls driving of the gate drive integrated circuit 310 and the data drive integrated circuit 320 based on a timing synchronization signal supplied from the outside.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of. Therefore, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

AA: display area NA: non-display area
PA: pad area CA: chip mounting area
100: substrate 110: signal line
120: driving integrated circuit 130: step difference compensation unit
200: Flexible circuit board

Claims (9)

A substrate including a display region having a signal line, a non-display region provided around the display region, and a chip mounting region having a signal input pad and a signal output pad connected to the signal line;
A drive integrated circuit having an input bump electrically coupled to the signal input pad and an output bump electrically coupled to the signal output pad; And
And a step difference compensating section provided between the substrate and the drive integrated circuit. The method according to claim 1,
The step-
A first dummy pattern provided in a region other than a region where the signal input pad and the signal output pad are provided in the chip mounting region; And
And a second dummy pattern overlapping the first dummy pattern. 3. The method of claim 2,
And a gate electrode formed in the display region,
Wherein the first dummy pattern is made of the same material as the gate electrode. 3. The method of claim 2,
Further comprising first and second electrodes formed in the display region,
And the second dummy pattern is made of the same material as the first and second electrodes. 3. The method of claim 2,
An insulating film provided between the first dummy pattern and the second dummy pattern; And
And a protective film covering the second dummy pattern. 3. The method of claim 2,
The driving integrated circuit further includes a signal transfer wiring provided between the signal input pad and the signal output pad,
Wherein the step compensating unit compensates a wiring step between a lower surface of the drive integrated circuit facing the substrate and a lower surface of a signal transfer wiring facing the substrate. The method of claim 3,
Wherein the first dummy pattern is made of a metal material,
Wherein the metal material is at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and titanium (Ti). 5. The method of claim 4,
Wherein the second dummy pattern is made of a metal material,
Wherein the metal material is at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and titanium (Ti). The method according to claim 6,
The sum of the thickness of the first dummy pattern and the thickness of the second dummy pattern is the same as the wiring step,
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190051373A (en) * 2017-11-06 2019-05-15 엘지디스플레이 주식회사 Display device
KR20190070617A (en) * 2017-12-13 2019-06-21 엘지디스플레이 주식회사 Display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190051373A (en) * 2017-11-06 2019-05-15 엘지디스플레이 주식회사 Display device
KR20190070617A (en) * 2017-12-13 2019-06-21 엘지디스플레이 주식회사 Display device

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