JP2016092305A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- JP2016092305A JP2016092305A JP2014227329A JP2014227329A JP2016092305A JP 2016092305 A JP2016092305 A JP 2016092305A JP 2014227329 A JP2014227329 A JP 2014227329A JP 2014227329 A JP2014227329 A JP 2014227329A JP 2016092305 A JP2016092305 A JP 2016092305A
- Authority
- JP
- Japan
- Prior art keywords
- insulating member
- wiring
- opening
- electrode pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 253
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 79
- 239000013039 cover film Substances 0.000 claims abstract description 85
- 239000000523 sample Substances 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims description 109
- 238000000034 method Methods 0.000 claims description 87
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 35
- 238000010438 heat treatment Methods 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 2
- 230000008707 rearrangement Effects 0.000 abstract description 107
- 239000010410 layer Substances 0.000 description 65
- 230000004048 modification Effects 0.000 description 59
- 238000012986 modification Methods 0.000 description 59
- 230000008569 process Effects 0.000 description 45
- 239000010949 copper Substances 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 19
- 239000000758 substrate Substances 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 16
- 230000002093 peripheral effect Effects 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 230000001681 protective effect Effects 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 102100029952 Double-strand-break repair protein rad21 homolog Human genes 0.000 description 6
- 101000584942 Homo sapiens Double-strand-break repair protein rad21 homolog Proteins 0.000 description 6
- 101001024120 Homo sapiens Nipped-B-like protein Proteins 0.000 description 6
- 102100035377 Nipped-B-like protein Human genes 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000005336 cracking Methods 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000012216 screening Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000003864 humus Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本発明は半導体装置の製造技術に関し、例えば半導体チップの電極パッドに配線が接続される半導体装置の製造に好適に利用できるものである。 The present invention relates to a manufacturing technique of a semiconductor device, and can be suitably used for manufacturing a semiconductor device in which wiring is connected to an electrode pad of a semiconductor chip, for example.
本技術分野であるウエハプロセスパッケージ（Wafer Process Package：ＷＰＰ）またはウエハレベルパッケージ（Wafer Level Package：ＷＬＰ）の背景技術として、特開２００９−２４６２１８号公報、特開２００８−０２１９３６号公報および特開２００７−１５７８７９号公報がある。 As a background technology of a wafer process package (WPP) or a wafer level package (WLP) which is this technical field, JP2009-246218A, JP2008-021936A, and JP2007. No. 157879.
特開２００９−２４６２１８号公報（特許文献１）には、半導体チップ上にプローブ領域および接続領域を有するパッドが設けられ、接続領域より半導体チップの外周部側に設けられたプローブ領域のパッドにプローブ痕が存在し、接続領域から半導体チップの中央部側に延びて再配線が存在する半導体装置およびその製造方法が記載されている。 In JP 2009-246218 A (Patent Document 1), a pad having a probe region and a connection region is provided on a semiconductor chip, and a probe is connected to the pad in the probe region provided on the outer peripheral portion side of the semiconductor chip from the connection region. A semiconductor device having a trace and extending from the connection region to the center of the semiconductor chip and having rewiring and a method for manufacturing the same are described.
また、特開２００８−０２１９３６号公報（特許文献２）には、線状部およびポスト電極搭載部を有する配線パターンを含む再配線層と、ポスト電極搭載部上に設けられ、ポスト電極搭載部の上面の輪郭に対して最小でも２点で交わる輪郭を有する底面を有するポスト電極と、ポスト電極の頂面上に搭載された外部端子とを備えた半導体装置およびその製造方法が記載されている。 Japanese Patent Laid-Open No. 2008-021936 (Patent Document 2) discloses a rewiring layer including a wiring pattern having a linear portion and a post electrode mounting portion, and a post electrode mounting portion provided on the post electrode mounting portion. A semiconductor device including a post electrode having a bottom surface having a contour that intersects at least two points with respect to the contour of the upper surface, and an external terminal mounted on the top surface of the post electrode, and a method for manufacturing the semiconductor device are described.
また、特開２００７−１５７８７９号公報（特許文献３）には、端子電極に接合して、無電解めっきによって形成されためっき下地層が設けられており、端子電極のめっき下地層に接合する再配線層の少なくとも一部がめっき層からなる半導体装置およびその製造方法が記載されている。 Japanese Patent Laid-Open No. 2007-157879 (Patent Document 3) is provided with a plating base layer formed by electroless plating bonded to a terminal electrode. A semiconductor device in which at least a part of a wiring layer is made of a plating layer and a method for manufacturing the same are described.
近年では、半導体装置の高機能化および高速化に伴い、半導体チップに設けられる電極パッドの数は増加する傾向にある。一方、半導体装置の小型化の要求もあり、互いに隣り合う電極パッドのピッチ（間隔）は狭くなる傾向にある。 In recent years, the number of electrode pads provided on a semiconductor chip tends to increase as the performance and speed of semiconductor devices increase. On the other hand, there is a demand for miniaturization of semiconductor devices, and the pitch (interval) between electrode pads adjacent to each other tends to be narrow.
この対策として、前記特許文献１乃至３に示すように、半導体チップに設けられた電極パッドに、新たに別の配線（再配置配線、再配線）を接続することが有効とされているが、使用する半導体チップ、すなわち、製品の仕様によっては、信頼性を確保する上で、様々な課題が生じる恐れがあることを、本発明者らは見出した。 As a countermeasure against this, as shown in Patent Documents 1 to 3, it is effective to newly connect another wiring (rearrangement wiring, rewiring) to the electrode pad provided on the semiconductor chip. The present inventors have found that various problems may occur in securing reliability depending on the semiconductor chip to be used, that is, the specifications of the product.
その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.
一実施の形態による半導体装置の製造方法は、まず、第１電極パッド、平面視において第１電極パッドの隣に配置された第２電極パッド、および第１電極パッドの上面が露出する第１開口部および第２電極パッドの上面が露出する第２開口部が形成された第１絶縁部材をその上面に有する半導体ウエハを準備する。続いて、半導体ウエハの第１絶縁部材上に第２絶縁部材を形成した後、第１電極パッドの上面が露出する第３開口部および第２電極パッドの上面が露出する第４開口部を第２絶縁部材に形成する。続いて、第１電極パッドの上面および第２電極パッドの上面を第１カバー膜および第２カバー膜でそれぞれ覆った後、第１カバー膜の表面および第２カバー膜の表面に第１配線および第２配線をそれぞれ形成する。続いて、第１カバー膜の表面、第２カバー膜の表面、第１配線および第２配線を第３絶縁部材で覆った後、第１配線の一部が露出する第５開口部および第２配線の一部が露出する第６開口部を第３絶縁部材に形成する。ここで、第１電極パッドおよび第２電極パッドは、平面視において第１方向に沿って配置されており、第１カバー膜および第２カバー膜のそれぞれは導電性部材からなり、第１方向における第１配線の幅は第２絶縁部材に形成された第３開口部の幅よりも小さい、または同じであり、第１方向における第２配線の幅は第２絶縁部材に形成された第４開口部の幅よりも小さい、または同じである。 In a method of manufacturing a semiconductor device according to an embodiment, first, a first electrode pad, a second electrode pad arranged next to the first electrode pad in plan view, and a first opening from which an upper surface of the first electrode pad is exposed. A semiconductor wafer having a first insulating member formed with a second opening in which the upper surface of the first electrode pad and the second electrode pad are exposed is prepared. Subsequently, after forming the second insulating member on the first insulating member of the semiconductor wafer, the third opening that exposes the upper surface of the first electrode pad and the fourth opening that exposes the upper surface of the second electrode pad are formed. Two insulating members are formed. Subsequently, after covering the upper surface of the first electrode pad and the upper surface of the second electrode pad with the first cover film and the second cover film, respectively, the first wiring and the surface of the first cover film and the surface of the second cover film Second wirings are formed respectively. Subsequently, after covering the surface of the first cover film, the surface of the second cover film, the first wiring, and the second wiring with the third insulating member, the fifth opening portion and the second opening in which a part of the first wiring is exposed. A sixth opening from which a part of the wiring is exposed is formed in the third insulating member. Here, the first electrode pad and the second electrode pad are arranged along the first direction in a plan view, and each of the first cover film and the second cover film is made of a conductive member, and is arranged in the first direction. The width of the first wiring is smaller than or the same as the width of the third opening formed in the second insulating member, and the width of the second wiring in the first direction is the fourth opening formed in the second insulating member. It is smaller than or the same as the width of the part.
一実施の形態によれば、半導体装置の信頼性を向上し、かつ、半導体装置の小型化を実現することができる。 According to one embodiment, it is possible to improve the reliability of the semiconductor device and to reduce the size of the semiconductor device.
以下の実施の形態において、便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。 In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.
また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。 Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.
また、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。 Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
また、「Ａからなる」、「Ａよりなる」、「Ａを有する」、「Ａを含む」と言うときは、特にその要素のみである旨明示した場合等を除き、それ以外の要素を排除するものでないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
また、以下の実施の形態で用いる図面においては、平面図であっても図面を見やすくするためにハッチングを付す場合もある。また、以下の実施の形態を説明するための全図において、同一機能を有するものは原則として同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、電極パッドの直上で再配置配線が延在する方向を「Ｘ方向」とし、Ｘ方向と半導体ウエハの主面（特に、電極パッドの直上）で交差する方向を「Ｙ方向」とする。 In the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. In the following embodiments, the direction in which the rearrangement wiring extends immediately above the electrode pad is defined as the “X direction”, and the direction intersecting the X direction with the main surface of the semiconductor wafer (particularly immediately above the electrode pad) “Y direction”.
以下、本実施の形態を図面に基づいて詳細に説明する。 Hereinafter, the present embodiment will be described in detail with reference to the drawings.
（課題の詳細な説明）
本実施の形態による半導体装置の製造方法がより明確となると思われるため、本発明者らによって見いだされたウエハプロセスパッケージ技術における解決しようとする課題について詳細に説明する。
(Detailed description of the issue)
Since the manufacturing method of the semiconductor device according to the present embodiment is considered to be clearer, problems to be solved in the wafer process package technology found by the present inventors will be described in detail.
半導体装置の狭ピッチ化への対応策として、ウエハプロセスパッケージ技術により電極パッドのピッチ変換を行うことが有効である。ウエハプロセスパッケージ技術は、通常のウエハプロセス（前工程）とパッケージプロセス（後工程）とを一体化した技術であり、半導体ウエハの状態でパッケージまで完了した後、半導体チップごとに個片化するものである。ウエハプロセスパッケージ技術では、半導体ウエハの主面上に狭ピッチの電極パッドを形成し、さらに電極パッドと電気的に接続された再配置配線（配線、再配線）を形成することにより、電極パッドの狭ピッチを広いピッチへ変換することができる。 As a countermeasure for narrowing the pitch of semiconductor devices, it is effective to perform pitch conversion of electrode pads by wafer process package technology. Wafer process packaging technology is a technology that integrates a normal wafer process (pre-process) and a package process (post-process), and completes a package in the state of a semiconductor wafer, and then separates each semiconductor chip. It is. In the wafer process package technology, an electrode pad with a narrow pitch is formed on the main surface of a semiconductor wafer, and a rearrangement wiring (wiring, rewiring) electrically connected to the electrode pad is formed. A narrow pitch can be converted into a wide pitch.
本発明者らは、半導体ウエハの主面に形成されたメモリ回路にデータを書き込んだ後、半導体ウエハの主面上に再配置配線を形成することを検討している。 The inventors of the present invention are considering forming a rearrangement wiring on the main surface of the semiconductor wafer after writing data in a memory circuit formed on the main surface of the semiconductor wafer.
（１）まず、本発明者らは、その主面が無機絶縁膜（例えば酸化シリコン（ＳｉＯ２）膜または窒化シリコン（Ｓｉ３Ｎ４）膜など）で覆われた半導体ウエハについて検討した。この半導体ウエハは、メモリ回路と電気的に接続された電極パッドを有し、その電極パッドの上面（後に、プローブ針が接触する面）は無機絶縁膜に形成された開口部の開口端の内側において露出している。 (1) First, the present inventors examined a semiconductor wafer whose main surface was covered with an inorganic insulating film (for example, a silicon oxide (SiO 2 ) film or a silicon nitride (Si 3 N 4 ) film). This semiconductor wafer has an electrode pad electrically connected to the memory circuit, and the upper surface of the electrode pad (the surface on which the probe needle contacts later) is inside the opening end of the opening formed in the inorganic insulating film. Is exposed.
しかし、このような半導体ウエハにおいて、電極パッドと電気的に接続する再配置配線を形成する場合、無機絶縁膜上に直接再配置配線を形成すると、実装（組み立て）時または実使用環境におけるストレスなどにより、再配置配線またはこの再配置配線よりも下側（下層）に位置する層（配線層または上記無機絶縁膜を含む絶縁層など）にダメージ（例えば断線または亀裂など）が発生する恐れがある。他にも、形成する無機絶縁膜の厚さが薄い場合には、この無機絶縁膜の下側（下層）に位置する配線と、無機絶縁膜上に形成された再配置配線との間で容量を持たせることが困難となり、ノイズの影響で所望の電気特性が得られなくなる恐れもある。これらを抑制するためには、例えば前記特許文献１に記載されているように、有機絶縁膜（例えばポリイミド膜など）を介して無機絶縁膜上に再配置配線を形成することが望ましい。 However, when forming a rearrangement wiring electrically connected to the electrode pad in such a semiconductor wafer, forming the rearrangement wiring directly on the inorganic insulating film may cause stress during mounting (assembly) or actual use environment. May cause damage (for example, disconnection or cracking) to the rearrangement wiring or a layer (a wiring layer or an insulating layer including the inorganic insulating film) located below (lower layer) the rearrangement wiring. . In addition, when the thickness of the inorganic insulating film to be formed is thin, the capacitance between the wiring located on the lower side (lower layer) of the inorganic insulating film and the rearranged wiring formed on the inorganic insulating film It may be difficult to provide the desired electrical characteristics due to the influence of noise. In order to suppress these, for example, as described in Patent Document 1, it is desirable to form rearrangement wiring on the inorganic insulating film via an organic insulating film (for example, a polyimide film).
（２）そこで、本発明者らは、無機絶縁膜が形成された半導体ウエハに対して、メモリ回路にデータを書き込み、その後、その無機絶縁膜上に有機絶縁膜を形成し、その有機絶縁膜上に再配置配線を形成することを検討した。ところが、その結果、メモリ回路に書き込んだデータが消失することが明らかとなった。本発明者が検討したところ、この原因は、有機絶縁膜を硬化する際の熱処理における加熱温度（例えば３００℃〜４００℃程度）の影響によるものであることが分かった。 (2) Therefore, the present inventors write data to the memory circuit on the semiconductor wafer on which the inorganic insulating film is formed, and then form an organic insulating film on the inorganic insulating film, and the organic insulating film We considered the formation of relocation wiring on top. However, as a result, it has become clear that the data written in the memory circuit is lost. When this inventor examined, it turned out that this cause is based on the influence of the heating temperature (for example, about 300 to 400 degreeC) in the heat processing at the time of hardening an organic insulating film.
（３）そこで、本発明者らは、無機絶縁膜が形成された半導体ウエハの主面上に有機絶縁膜を形成し、有機絶縁膜を熱処理によって硬化させた後に、メモリ回路にデータを書き込み、さらに、その有機絶縁膜上に再配置配線を形成することを検討した。 (3) Therefore, the present inventors formed an organic insulating film on the main surface of the semiconductor wafer on which the inorganic insulating film is formed, and after curing the organic insulating film by heat treatment, write data to the memory circuit, Furthermore, the formation of relocation wiring on the organic insulating film was examined.
図３０（ａ）および（ｂ）はそれぞれ、本発明者らが検討した半導体装置の要部平面図および要部断面図である。図３０（ａ）は、半導体ウエハの主面側から見た、再配置配線を覆う絶縁部材（第３絶縁部材）を透かした透過平面図である。また、図３０（ｂ）は、図３０（ａ）に示すＢ−Ｂ線に沿った断面図である。 30 (a) and 30 (b) are a plan view and a cross-sectional view of relevant parts of a semiconductor device studied by the present inventors, respectively. FIG. 30A is a transparent plan view through the insulating member (third insulating member) covering the rearrangement wiring, as viewed from the main surface side of the semiconductor wafer. FIG. 30B is a cross-sectional view along the line BB shown in FIG.
第１絶縁部材ＩＯＬが形成された半導体ウエハＳＷの主面上に第２絶縁部材ＯＬを形成し、第２絶縁部材ＯＬを熱処理によって硬化させた後に、メモリ回路にデータを書き込むことにより、データの消失を回避することができる。 The second insulating member OL is formed on the main surface of the semiconductor wafer SW on which the first insulating member IOL is formed, and after the second insulating member OL is cured by heat treatment, the data is written into the memory circuit. Disappearance can be avoided.
ところで、データの書き込みは、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側および第２絶縁部材ＯＬに形成された開口部ＯＰ２の開口端の内側に露出する電極パッドＥＰの上面にプローブ針を接触させることによって行われる。第２絶縁部材ＯＬは半透明であるため、第２絶縁部材ＯＬの開口部ＯＰ２の開口端を、第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端の内側に配置した場合、プローブ針を接触する位置を特定することが難しくなる。 By the way, data writing is performed on the upper surface of the electrode pad EP exposed to the inside of the opening end of the opening OP1 formed in the first insulating member IOL and the inside of the opening end of the opening OP2 formed in the second insulating member OL. By contacting the probe needle with the probe needle. Since the second insulating member OL is translucent, when the opening end of the opening OP2 of the second insulating member OL is arranged inside the opening end of the opening OP1 of the first insulating member IOL, the probe needle is brought into contact. It becomes difficult to specify the position.
そのため、データの書き込みを考慮した場合、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の開口端の内側が確実に露出するように、第２絶縁部材ＯＬに形成される開口部ＯＰ２を第１絶縁部材ＩＯＬに形成される開口部ＯＰ１よりも大きく形成することが好ましい。すなわち、第２絶縁部材ＯＬの開口部ＯＰ２の開口端を、第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端と同じか、または第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端の外側に配置することが好ましい。 Therefore, when data writing is considered, the opening OP2 formed in the second insulating member OL is formed in the first insulating member OL so that the inside of the opening end of the opening OP1 formed in the first insulating member IOL is reliably exposed. It is preferable that the opening is formed larger than the opening OP1 formed in the insulating member IOL. In other words, the opening end of the opening OP2 of the second insulating member OL is arranged to be the same as the opening end of the opening OP1 of the first insulating member IOL or outside the opening end of the opening OP1 of the first insulating member IOL. It is preferable.
しかし、第２絶縁部材ＯＬの開口部ＯＰ２の開口端を、第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端と同じか、または第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端の外側に配置すると、再配置配線ＲＷの幅ＬＲＷが大きくなってしまう。 However, if the opening end of the opening OP2 of the second insulating member OL is the same as the opening end of the opening OP1 of the first insulating member IOL or outside the opening end of the opening OP1 of the first insulating member IOL. the width L RW relocation wiring RW increases.
詳細に説明すると、電極パッドＥＰが、例えばアルミニウム（Ａｌ）からなる場合、電極パッドＥＰの上面が露出していると、ウエットエッチング法またはドライエッチング法などを用いて再配置配線ＲＷを形成する際、具体的には、エッチング液を用いてシード層のうち不要な部分を除去する際、電極パッドＥＰが変質（腐食、形状変化など）しやすい。また、例えばアルミニウム（Ａｌ）からなる電極パッドＥＰの上面が露出していると、後に形成する、再配置配線ＲＷを覆う第３絶縁部材ＳＲが電極パッドＥＰと直接、接触（接着）することになり、完成した製品（半導体チップ）が例えば高温・高湿の環境下に晒されると、電極パッドＥＰが変質（腐食など）し、電気特性不良を引き起こす恐れがある。 More specifically, when the electrode pad EP is made of, for example, aluminum (Al), when the upper surface of the electrode pad EP is exposed, the rearrangement wiring RW is formed using a wet etching method or a dry etching method. Specifically, when an unnecessary portion of the seed layer is removed using an etching solution, the electrode pad EP is likely to be altered (corrosion, shape change, etc.). Further, when the upper surface of the electrode pad EP made of, for example, aluminum (Al) is exposed, the third insulating member SR that covers the rearrangement wiring RW, which will be formed later, is in direct contact (adhesion) with the electrode pad EP. Thus, when the finished product (semiconductor chip) is exposed to, for example, an environment of high temperature and high humidity, the electrode pad EP may be altered (corrosion, etc.), which may cause poor electrical characteristics.
（４）そこで、本発明者らは、電極パッドＥＰが露出しないように、再配置配線ＲＷの幅ＬＲＷが、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＬＯＰ１および第２絶縁部材ＯＬに形成される開口部ＯＰ２の幅ＬＯＰ２よりも大きくなるように、再配置配線ＲＷを形成した。しかし、この場合、互いに隣り合う電極パッドＥＰのピッチ（間隔）を小さくすること、すなわち、狭ピッチ化が困難となる。これにより、半導体装置の小型化または多ピン化に対応することができない。 (4) Therefore, the present inventors set the width L RW of the rearrangement wiring RW to the width L OP1 and the second insulation of the opening OP1 formed in the first insulating member IOL so that the electrode pad EP is not exposed. to be greater than the width L OP2 of the opening OP2 formed in the member OL, to form a rearrangement wiring RW. However, in this case, it is difficult to reduce the pitch (interval) between the electrode pads EP adjacent to each other, that is, to narrow the pitch. As a result, the semiconductor device cannot be reduced in size or increased in number of pins.
なお、互いに隣り合う電極パッドＥＰのピッチ（間隔）を小さくするには、例えば前記特許文献２に記載されているように、電極パッドＥＰ上における再配置配線ＲＷの幅ＬＲＷを、電極パッドＥＰの幅ＬＥＰよりも小さくすればよい。しかし、この場合、前述したように、電極パッドＥＰの上面の一部が露出した状態となり、例えばエッチング液を用いて再配置配線ＲＷを形成すると、電極パッドＥＰが変質（腐食、形状変化など）し、再配置配線ＲＷを覆う絶縁部材、すなわち、第３絶縁部材ＳＲが電極パッドＥＰの表面から剥離する、といった問題が生じる恐れがある。 In order to reduce the pitch (interval) between adjacent electrode pads EP, for example, as described in Patent Document 2, the width L RW of the rearrangement wiring RW on the electrode pad EP is set to the electrode pad EP. The width LEP may be made smaller. However, in this case, as described above, a part of the upper surface of the electrode pad EP is exposed. For example, when the rearrangement wiring RW is formed using an etching solution, the electrode pad EP is altered (corrosion, shape change, etc.). However, there is a possibility that the insulating member covering the rearrangement wiring RW, that is, the third insulating member SR peels off from the surface of the electrode pad EP.
（実施の形態）
≪半導体装置≫
本実施の形態による半導体装置の構成について図１および図２を用いて説明する。図１は、本実施の形態による半導体装置の平面を示す概略図である。図２（ａ）および（ｂ）はそれぞれ、本実施の形態による半導体装置の一部を拡大して示す要部平面図および要部断面図である。図２（ｂ）は、図２（ａ）に示すＡ−Ａ線に沿った断面図である。
(Embodiment)
≪Semiconductor device≫
The structure of the semiconductor device according to this embodiment will be described with reference to FIGS. FIG. 1 is a schematic view showing a plane of a semiconductor device according to the present embodiment. FIGS. 2A and 2B are an essential part plan view and an essential part cross-sectional view, respectively, showing an enlarged part of the semiconductor device according to the present embodiment. FIG.2 (b) is sectional drawing along the AA line shown to Fig.2 (a).
本実施の形態では、図１に示すように、半導体装置（半導体チップ）ＳＣの中央部には、行列状に配置されたボール状の複数のバンプ電極（はんだボール）ＳＢが設けられている。複数のバンプ電極ＳＢは、半導体装置ＳＣの外部端子として、表面保護膜となる絶縁部材から突起するように設けられている。 In the present embodiment, as shown in FIG. 1, a plurality of ball-shaped bump electrodes (solder balls) SB arranged in a matrix are provided at the center of the semiconductor device (semiconductor chip) SC. The plurality of bump electrodes SB are provided as external terminals of the semiconductor device SC so as to protrude from an insulating member serving as a surface protective film.
また、半導体装置ＳＣの外周部には、半導体回路を構成する配線と電気的に接続された複数の電極パッド（表面電極）ＥＰが設けられている。さらに、複数の電極パッドＥＰのそれぞれは、複数のバンプ電極ＳＢのそれぞれと再配置配線（図示は省略）を介して電気的に接続されている。複数の電極パッドＥＰおよび複数の再配置配線は、絶縁部材により覆われている。実際には、複数の電極パッドＥＰは、この絶縁部材により覆われているので、図１では複数の電極パッドＥＰを点線で示している。 In addition, a plurality of electrode pads (surface electrodes) EP that are electrically connected to the wiring configuring the semiconductor circuit are provided on the outer peripheral portion of the semiconductor device SC. Further, each of the plurality of electrode pads EP is electrically connected to each of the plurality of bump electrodes SB via a rearrangement wiring (not shown). The plurality of electrode pads EP and the plurality of rearrangement wirings are covered with an insulating member. Actually, since the plurality of electrode pads EP are covered with this insulating member, the plurality of electrode pads EP are indicated by dotted lines in FIG.
矩形状の半導体装置ＳＣの主面（素子形成面）には半導体回路（図示は省略）が設けられている。半導体回路は、いわゆる前工程（通常のウエハプロセス）において周知技術によって形成され、例えば上記主面に形成された電界効果トランジスタ、抵抗および容量などの種々の半導体素子、並びに上記主面上に形成され、かつ、これらを電気的に接続する配線（配線層）、さらには、この配線（配線層）の間または上下に位置する絶縁層などから構成されている。なお、絶縁層の材料は、例えば炭素を添加した酸化シリコン（ＳｉＯＣ（silicon oxcarbide））膜のような低誘電率膜である。 A semiconductor circuit (not shown) is provided on the main surface (element formation surface) of the rectangular semiconductor device SC. The semiconductor circuit is formed by a well-known technique in a so-called pre-process (ordinary wafer process), and is formed on the main surface, for example, various semiconductor elements such as field effect transistors, resistors and capacitors formed on the main surface. In addition, a wiring (wiring layer) that electrically connects them, and an insulating layer positioned between or above and below the wiring (wiring layer). The material of the insulating layer is a low dielectric constant film such as a silicon oxide (SiOC (silicon oxcarbide)) film to which carbon is added.
次に、図２（ａ）および（ｂ）を用いて、バンプ電極、電極パッドおよび再配置配線の構成について詳細に説明する。なお、図２（ａ）には、複数の電極パッドのうち、互いに隣り合う２つの電極パッド（図１に示す二点破線で囲んだ領域）のみを例示している。また、複数の電極パッドの周縁は絶縁部材によって覆われているが、半導体ウエハの主面側から見た複数の電極パッドの平面図では、複数の電極パッドの周縁を実線で記載している。また、図２（ａ）は、半導体ウエハの主面側から見た、再配置配線を覆う絶縁部材（第３絶縁部材）およびバンプ電極を透かした透過平面図である。また、図２（ｂ）に符号ＩＤで示す層は、複数の電極パッド下に設けられた層間絶縁膜を示している。 Next, the configuration of the bump electrode, electrode pad, and rearrangement wiring will be described in detail with reference to FIGS. FIG. 2A illustrates only two electrode pads adjacent to each other (a region surrounded by a two-dot broken line shown in FIG. 1) among the plurality of electrode pads. The peripheral edges of the plurality of electrode pads are covered with an insulating member. However, in the plan view of the plurality of electrode pads viewed from the main surface side of the semiconductor wafer, the peripheral edges of the plurality of electrode pads are indicated by solid lines. FIG. 2A is a transparent plan view through the insulating member (third insulating member) covering the rearrangement wiring and the bump electrode as seen from the main surface side of the semiconductor wafer. Further, the layer indicated by reference numeral ID in FIG. 2B indicates an interlayer insulating film provided under a plurality of electrode pads.
電極パッドＥＰの直上で再配置配線（配線、再配線）ＲＷが延在する方向（以下、本実施の形態では、例えば「Ｘ方向」と言う）において電極パッドＥＰの幅ＷＥＰは、例えば１０２μｍ程度である。また、平面視（半導体基板ＳＵＢの主面側から見た平面状態）において、上記Ｘ方向と交差する方向（以下、本実施の形態では、例えば「Ｙ方向」と言う）における電極パッドＥＰの幅ＬＥＰは、例えば４７μｍ程度であり、互いに隣り合う２つの電極パッドＥＰの間隔ＤＥＰは、例えば３μ程度である。なお、本実施の形態では、複数の電極パッドＥＰが半導体チップの辺（最も近い辺）に沿って配置（配列）されている。また、再配置配線ＲＷを基準にしてみた場合は、上記したＹ方向に沿って複数の電極パッドＥＰが配置（配列）されているとも言える。また、本実施の形態では、Ｘ方向とＹ方向は、互いに直交している。さらに、上記したＸ方向とは、電極パッドＥＰの直上における再配置配線ＲＷの延在方向である。 The width W EP of the electrode pad EP is, for example, 102 μm in the direction in which the rearrangement wiring (wiring, rewiring) RW extends immediately above the electrode pad EP (hereinafter referred to as “X direction” in the present embodiment, for example). Degree. Further, the width of the electrode pad EP in a direction intersecting with the X direction (hereinafter referred to as “Y direction” in the present embodiment) in a plan view (planar state viewed from the main surface side of the semiconductor substrate SUB). L EP is, for example, about 47 [mu] m, the distance D EP of the two electrode pads EP mutually adjacent, for example, about 3.mu.. In the present embodiment, the plurality of electrode pads EP are arranged (arranged) along the side (closest side) of the semiconductor chip. Further, when viewed from the rearrangement wiring RW, it can be said that a plurality of electrode pads EP are arranged (arranged) along the Y direction. In the present embodiment, the X direction and the Y direction are orthogonal to each other. Furthermore, the above-described X direction is an extending direction of the rearrangement wiring RW immediately above the electrode pad EP.
これら電極パッドＥＰに、プローブ針を接触させて、半導体基板ＳＵＢの主面に形成されたメモリ回路へのデータの書き込み、またはメモリ回路の初期故障などを調べるスクリーニングテストなどを行う。 A probe needle is brought into contact with these electrode pads EP to perform data writing to a memory circuit formed on the main surface of the semiconductor substrate SUB or a screening test for examining an initial failure of the memory circuit.
電極パッドＥＰを覆うように、半導体基板ＳＵＢの主面上に第１絶縁部材（第１絶縁膜、第１弾性率を有する絶縁膜、第１パッシベーション膜）ＩＯＬが形成されている。第１絶縁部材ＩＯＬは、無機絶縁膜であり、例えば酸窒化シリコン（ＳｉＯＮ）膜、酸化シリコン（ＳｉＯ２）膜または窒化シリコン（Ｓｉ３Ｎ４）膜などからなる。第１絶縁部材ＩＯＬの厚さは、例えば０．６μｍ〜０．８μｍ程度である。また、例えば窒化シリコン（Ｓｉ３Ｎ４）膜のヤング率は、２５０ＧＰａ〜３００ＧＰａ程度である。 A first insulating member (a first insulating film, an insulating film having a first elastic modulus, a first passivation film) IOL is formed on the main surface of the semiconductor substrate SUB so as to cover the electrode pad EP. The first insulating member IOL is an inorganic insulating film, and is made of, for example, a silicon oxynitride (SiON) film, a silicon oxide (SiO 2 ) film, a silicon nitride (Si 3 N 4 ) film, or the like. The thickness of the first insulating member IOL is, for example, about 0.6 μm to 0.8 μm. For example, the Young's modulus of a silicon nitride (Si 3 N 4 ) film is about 250 GPa to 300 GPa.
この第１絶縁部材ＩＯＬには、電極パッドＥＰの上面を露出する開口部ＯＰ１が形成されている。Ｘ方向において開口部ＯＰ１の幅ＷＯＰ１は、例えば１００μｍ程度である。また、Ｙ方向において開口部ＯＰ１の幅ＬＯＰ１は、例えば４５μｍ程度であり、開口部ＯＰ１の間隔ＤＯＰ１は、例えば５μ程度である。 In the first insulating member IOL, an opening OP1 exposing the upper surface of the electrode pad EP is formed. The width W OP1 of the opening OP1 in the X direction is, for example, about 100 μm. Further, the width L OP1 of the opening OP1 in the Y direction is, for example, about 45 μm, and the interval D OP1 of the opening OP1 is, for example, about 5 μm.
また、第１絶縁部材ＩＯＬ上に第２絶縁部材（第２絶縁膜、第２弾性率を有する絶縁膜、第２パッシベーション膜）ＯＬが形成されている。第２絶縁部材ＯＬは、有機絶縁膜であり、例えばポリイミド膜などからなる。第２絶縁部材ＯＬの厚さは、例えば５μｍ程度である。また、第２絶縁部材ＯＬの弾性率は、第１絶縁部材ＩＯＬの弾性率よりも低く、例えばポリイミド膜のヤング率は、３ＧＰａ〜７ＧＰａ程度である。 A second insulating member (second insulating film, insulating film having a second elastic modulus, second passivation film) OL is formed on the first insulating member IOL. The second insulating member OL is an organic insulating film, and is made of, for example, a polyimide film. The thickness of the second insulating member OL is, for example, about 5 μm. The elastic modulus of the second insulating member OL is lower than the elastic modulus of the first insulating member IOL. For example, the Young's modulus of the polyimide film is about 3 GPa to 7 GPa.
この第２絶縁部材ＯＬには、電極パッドＥＰの上面を露出する開口部ＯＰ２が形成されている。Ｘ方向において第２絶縁部材ＯＬに形成される開口部ＯＰ２の幅ＷＯＰ２は、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＷＯＰ１と同じか、それよりも大きく、Ｙ方向において開口部ＯＰ２の幅ＬＯＰ２は、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＬＯＰ１と同じか、それよりも大きい。 The second insulating member OL is formed with an opening OP2 that exposes the upper surface of the electrode pad EP. The width W OP2 of the opening OP2 formed in the second insulating member OL in the X direction is the same as or larger than the width W OP1 of the opening OP1 formed in the first insulating member IOL. The width L OP2 of the part OP2 is the same as or larger than the width L OP1 of the opening OP1 formed in the first insulating member IOL.
また、本実施の形態では、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側を埋め込むように、カバー膜（導電性部材）ＣＦが形成されている。なお、カバー膜ＣＦの形成箇所はこれに限るものではなく、例えば第２絶縁部材ＯＬに形成された開口部ＯＰ２の内側を埋め込むように形成してもよい。但し、カバー膜ＣＦが第２絶縁部材ＯＬ上にまで形成されると、本発明者らが検討した図３０のように、互いに隣り合う電極パッドＥＰのピッチ（間隔）を小さくすることが困難となる。また、互いに隣り合う電極パッドＥＰ間に位置する第２絶縁部材ＯＬの厚さ（Ｙ方向における長さ）が薄く、かつ、互いに異なる信号（または電流）が各電極パッドＥＰに流れる場合には、ノイズの影響を受ける恐れもある。これらのことから、電極パッドＥＰのピッチを小さくすることを考慮する場合には、図２（ａ）および（ｂ）に示すように、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側にカバー膜ＣＦが位置するように、カバー膜ＣＦを形成することが好ましい。 In the present embodiment, the cover film (conductive member) CF is formed so as to embed the inside of the opening end of the opening OP1 formed in the first insulating member IOL. Note that the position where the cover film CF is formed is not limited to this, and the cover film CF may be formed so as to be embedded inside the opening OP2 formed in the second insulating member OL, for example. However, if the cover film CF is formed even on the second insulating member OL, it is difficult to reduce the pitch (interval) between the electrode pads EP adjacent to each other as shown in FIG. 30 examined by the present inventors. Become. In addition, when the thickness (the length in the Y direction) of the second insulating member OL located between the electrode pads EP adjacent to each other is thin and different signals (or currents) flow through the electrode pads EP, There is also a risk of being affected by noise. Therefore, when considering reducing the pitch of the electrode pads EP, as shown in FIGS. 2A and 2B, the opening end of the opening OP1 formed in the first insulating member IOL is shown. It is preferable to form the cover film CF so that the cover film CF is located inside.
また、本実施の形態では、第２絶縁部材ＯＬ上に再配置配線ＲＷが形成されている。再配置配線ＲＷの一端部は、カバー膜ＣＦと電気的に接続し、再配置配線ＲＷの他端部（バンプランド、ボンディングパッド）は、半導体装置ＳＣの中央部側に引き出されている。再配置配線ＲＷ下には、再配置配線ＲＷを形成する際にシード（Seed）としての役割を担うシード層ＳＬが形成されている。再配置配線ＲＷは、例えば銅（Ｃｕ）からなり、その厚さは、例えば５μｍ程度である。シード層ＳＬは、例えばチタン（Ｔｉ）膜および銅（Ｃｕ）膜が下層から順次形成された積層膜からなり、その厚さ（総厚）は、例えば０．３μｍ程度である。詳しくは、チタン（Ｔｉ）膜の厚さが０．２μｍ程度、銅（Ｃｕ）の厚さが０．１μｍ程度である。 In the present embodiment, the rearrangement wiring RW is formed on the second insulating member OL. One end portion of the rearrangement wiring RW is electrically connected to the cover film CF, and the other end portion (bump land, bonding pad) of the rearrangement wiring RW is drawn out to the central portion side of the semiconductor device SC. Under the rearrangement wiring RW, a seed layer SL that serves as a seed when the rearrangement wiring RW is formed is formed. The rearrangement wiring RW is made of, for example, copper (Cu) and has a thickness of, for example, about 5 μm. The seed layer SL is composed of a laminated film in which, for example, a titanium (Ti) film and a copper (Cu) film are sequentially formed from the lower layer, and the thickness (total thickness) is, for example, about 0.3 μm. Specifically, the thickness of the titanium (Ti) film is about 0.2 μm, and the thickness of copper (Cu) is about 0.1 μm.
Ｘ方向において、電極パッドＥＰの直上に形成された再配置配線ＲＷの幅ＷＲＷは、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＷＯＰ１、またはカバー膜ＣＦの幅（長さ）と同じか、それよりも小さい。また、Ｙ方向において、電極パッドＥＰの直上に形成された再配置配線ＲＷの幅ＬＲＷは、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１、またはカバー膜ＣＦの幅（長さ）と同じか、それよりも小さい。 In the X direction, the width W RW of the rearrangement wiring RW formed immediately above the electrode pad EP is equal to the width W OP1 of the opening OP1 formed in the first insulating member IOL or the width (length) of the cover film CF. Less than or equal to. Further, in the Y direction, the width L RW relocation wiring RW formed directly on the electrode pads EP, the width L OP1 of the first insulating member opening OP1 formed in IOL or cover film width CF, (long Is the same as or smaller than
このように、Ｙ方向（複数の電極パッドＥＰが配列されている方向、半導体チップの辺に沿った方向）において、電極パッドＥＰの直上に形成された再配置配線ＲＷの幅ＬＲＷを、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１、またはカバー膜ＣＦの幅（長さ）と同じか、それよりも小さくしているので、Ｙ方向に互いに隣り合う再配置配線ＲＷの接触を防ぐことができる。これにより、複数の電極パッドＥＰの狭ピッチ化を実現することが可能となり、半導体装置の小型化を実現することができる。 Thus, Y-direction (the direction in which the plurality of electrode pads EP are arranged, along the sides of the semiconductor chip), the width L RW relocation wiring RW formed directly on the electrode pads EP, first 1 width L OP1 of the opening OP1 formed in the insulating member IOL or width of the cover film CF (length) and the same or, since the smaller than, the rearrangement wiring RW adjacent to each other in the Y-direction Contact can be prevented. As a result, it is possible to reduce the pitch of the plurality of electrode pads EP, and it is possible to reduce the size of the semiconductor device.
なお、本実施の形態では、前述のように、再配置配線ＲＷの幅ＬＲＷを、Ｙ方向において、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１、またはカバー膜ＣＦの幅（長さ）と同じか、それよりも小さくすることについて説明したが、再配置配線ＲＷの幅ＬＲＷを、第２絶縁部材ＯＬに形成された開口部ＯＰ２の幅ＬＯＰ２と同じか、それよりも小さくしてもよい。但し、再配置配線ＲＷが、所望の位置からずれて形成される恐れもある。さらには、再配置配線ＲＷを構成する材料として銅（Ｃｕ）を用いる場合は、互いに隣り合う再配置配線ＲＷの間隔（距離）が近いほど、マイグレーションの問題も発生しやすくなる。そのため、前述したような問題を考慮した場合は、本実施の形態のように、再配置配線ＲＷの幅ＬＲＷを、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１またはカバー膜ＣＦの幅（長さ）と同じか、それよりも小さく形成することが好ましい。 In the present embodiment, as described above, the width L RW relocation wiring RW, in the Y direction, the width L OP1 of the first insulating member opening OP1 formed in IOL or width of the cover film CF, or (length) and the same has been described to be smaller than the width L RW relocation wiring RW, the same as the width L OP2 of the second insulating member opening OP2 formed in OL, it It may be smaller. However, the rearrangement wiring RW may be formed out of the desired position. Furthermore, when copper (Cu) is used as a material constituting the rearrangement wiring RW, a migration problem is more likely to occur as the interval (distance) between the rearrangement wirings RW adjacent to each other is shorter. Therefore, when considering the problems as described above, as in the present embodiment, the width L RW relocation wiring RW, the width L OP1 of the first insulating member opening OP1 formed in IOL or cover film It is preferable to form the same as or smaller than the width (length) of CF.
また、再配置配線ＲＷを覆うように、半導体基板ＳＵＢの主面上に第３絶縁部材（第３絶縁膜、第３パッシベーション膜、有機材料、樹脂）ＳＲが形成されている。第３絶縁部材ＳＲは、有機絶縁膜であり、具体的な材料としては、例えばポリイミド膜などである。 Further, a third insulating member (third insulating film, third passivation film, organic material, resin) SR is formed on the main surface of the semiconductor substrate SUB so as to cover the rearrangement wiring RW. The third insulating member SR is an organic insulating film, and a specific material is, for example, a polyimide film.
この第３絶縁部材ＳＲには、半導体装置ＳＣの中央部側に引き出された再配置配線ＲＷの他端部の上面を露出する開口部ＯＰ３が形成されている。さらに、この開口部ＯＰ３に露出する再配置配線ＲＷの他端部には、電極層（電極）ＵＭを介してボール状のバンプ電極ＳＢが接続されている。すなわち、カバー膜ＣＦおよび再配置配線ＲＷを介して、電極パッドＥＰとバンプ電極ＳＢとが電気的に接続されている。バンプ電極ＳＢは、半導体装置ＳＣの外部端子として、第３絶縁部材ＳＲから突起するように設けられている。 The third insulating member SR is formed with an opening OP3 that exposes the upper surface of the other end portion of the rearrangement wiring RW drawn to the center side of the semiconductor device SC. Further, a ball-shaped bump electrode SB is connected to the other end of the rearrangement wiring RW exposed in the opening OP3 via an electrode layer (electrode) UM. That is, the electrode pad EP and the bump electrode SB are electrically connected through the cover film CF and the rearrangement wiring RW. The bump electrode SB is provided as an external terminal of the semiconductor device SC so as to protrude from the third insulating member SR.
≪半導体装置の製造方法≫
本実施の形態による半導体装置の製造方法について図３〜図１４を用いて工程順に説明する。図３は、本実施の形態による半導体装置の製造方法において、その製造工程の流れの一例を示す工程図である。図４（ａ）および（ｂ）はそれぞれ、本実施の形態による半導体ウエハを示す要部平面図および半導体ウエハ内の一の半導体チップを拡大して示す要部平面図である。図５〜図１３の各々の（ａ）および（ｂ）はそれぞれ、本実施の形態による半導体装置の製造工程中の半導体装置の一部を拡大して示す要部平面図および要部断面図である。図１４は、本実施の形態による半導体装置の製造工程中の半導体装置を示す要部断面図である。
≪Semiconductor device manufacturing method≫
A method for manufacturing a semiconductor device according to the present embodiment will be described in the order of steps with reference to FIGS. FIG. 3 is a process diagram showing an example of the flow of the manufacturing process in the manufacturing method of the semiconductor device according to the present embodiment. FIGS. 4A and 4B are a main part plan view showing a semiconductor wafer according to the present embodiment and a main part plan view showing one semiconductor chip in the semiconductor wafer in an enlarged manner. 5A to 13B are an essential part plan view and an essential part cross-sectional view showing an enlarged part of the semiconductor device during the manufacturing process of the semiconductor device according to the present embodiment, respectively. is there. FIG. 14 is a fragmentary cross-sectional view showing the semiconductor device during the manufacturing process of the semiconductor device according to the present embodiment.
なお、図５〜図１３の各々の（ａ）には、複数の電極パッドのうち、互いに隣り合う２つの電極パッド（図４（ｂ）に示す二点破線で囲んだＡ領域）のみを例示している。また、複数の電極パッドの周縁は絶縁部材によって覆われているが、半導体ウエハの主面側から見た複数の電極パッドの平面図では、複数の電極パッドの周縁を実線で記載している。 Each of FIG. 5 to FIG. 13A illustrates only two electrode pads adjacent to each other (A region surrounded by a two-dot broken line shown in FIG. 4B) among the plurality of electrode pads. doing. The peripheral edges of the plurality of electrode pads are covered with an insulating member. However, in the plan view of the plurality of electrode pads viewed from the main surface side of the semiconductor wafer, the peripheral edges of the plurality of electrode pads are indicated by solid lines.
１．半導体ウエハ準備（工程Ｓ１）
まず、図４（ａ）に示すように、種々の半導体回路が形成された複数のデバイス領域（チップ形成領域）ＤＲを有する半導体ウエハＳＷを準備する。半導体ウエハＳＷの主面には、例えば電界効果トランジスタ、抵抗および容量などの種々の半導体素子が形成されており、これらを、前述した配線（配線層）を介して電気的に接続することにより、メモリ回路などの種々の半導体回路が各々のデバイス領域ＤＲに形成されている。半導体ウエハＳＷは、例えば平面略円形状のシリコン（Ｓｉ）基板である。なお、半導体ウエハＳＷは、シリコン（Ｓｉ）基板に限らず、ガリウムヒ素（ＧａＡｓ）基板または炭化珪素（ＳｉＣ）基板などの化合物半導体基板であってもよい。
1. Semiconductor wafer preparation (step S1)
First, as shown in FIG. 4A, a semiconductor wafer SW having a plurality of device regions (chip forming regions) DR in which various semiconductor circuits are formed is prepared. Various semiconductor elements such as field effect transistors, resistors, and capacitors are formed on the main surface of the semiconductor wafer SW, and these are electrically connected via the wiring (wiring layer) described above. Various semiconductor circuits such as a memory circuit are formed in each device region DR. The semiconductor wafer SW is, for example, a planar substantially circular silicon (Si) substrate. The semiconductor wafer SW is not limited to a silicon (Si) substrate, but may be a compound semiconductor substrate such as a gallium arsenide (GaAs) substrate or a silicon carbide (SiC) substrate.
また、図４（ｂ）に示すように、各々のデバイス領域ＤＲには、複数の電極パッドＥＰが、デバイス領域ＤＲの外周部に形成されている。複数の電極パッドＥＰは、半導体ウエハＳＷの主面に形成されたメモリ回路などの種々の半導体回路と、配線を介して電気的に接続されている。複数の電極パッドＥＰは、例えばデバイス領域ＤＲの外周部側から中央部側に長辺を有する矩形状に形成される。また、複数の電極パッドＥＰは、例えば主導電層となるアルミニウム（Ａｌ）膜の上下をチタン（Ｔｉ）膜および窒化チタン（ＴｉＮ）膜の積層膜からなるバリア性を有する導電膜によって挟んだ構造からなる。複数の電極パッドＥＰの厚さは、例えば０．４μｍ〜６．０μｍ程度であり、代表的な厚さとしては１．０μｍ程度を例示することができる。 Further, as shown in FIG. 4B, in each device region DR, a plurality of electrode pads EP are formed on the outer periphery of the device region DR. The plurality of electrode pads EP are electrically connected to various semiconductor circuits such as a memory circuit formed on the main surface of the semiconductor wafer SW via wiring. The plurality of electrode pads EP are formed in a rectangular shape having long sides from the outer peripheral side to the central side of the device region DR, for example. In addition, the plurality of electrode pads EP are, for example, a structure in which an aluminum (Al) film serving as a main conductive layer is sandwiched between conductive films having barrier properties made of a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film. Consists of. The thickness of the plurality of electrode pads EP is, for example, about 0.4 μm to 6.0 μm, and a typical thickness is about 1.0 μm.
また、図４（ａ）には、スクライブ領域（ダイシング領域）ＬＲが示されている。この段階でスクライブ領域ＬＲに沿って半導体ウエハＳＷを切断することにより、半導体チップを取得することができる。本実施の形態では、さらに以下に説明する各工程を施してから個片化するため、半導体チップであると共に、半導体装置としても使用することができる。 FIG. 4A shows a scribe region (dicing region) LR. At this stage, the semiconductor chip can be obtained by cutting the semiconductor wafer SW along the scribe region LR. In this embodiment mode, the semiconductor chip is used as a semiconductor device because it is divided into individual pieces after each process described below is performed.
以下に、複数の電極パッドＥＰのうち、互いに隣り合う２つの電極パッドＥＰを例示して、本実施の形態における技術的特徴について説明する。 Hereinafter, technical features in the present embodiment will be described by exemplifying two electrode pads EP adjacent to each other among the plurality of electrode pads EP.
図５（ａ）は、複数の電極パッドＥＰのうち、互いに隣り合う２つの電極パッドＥＰを拡大して示す平面図である。Ｘ方向において電極パッドＥＰの幅ＷＥＰは、例えば１０２μｍ程度である。また、Ｙ方向において電極パッドＥＰの幅ＬＥＰは、例えば４７μｍ程度であり、互いに隣り合う電極パッドＥＰの間隔ＤＥＰは、例えば３μｍ程度である。 FIG. 5A is an enlarged plan view showing two electrode pads EP adjacent to each other among the plurality of electrode pads EP. The width W EP of the electrode pad EP in the X direction is, for example, about 102 μm. In addition, the width L EP of the electrode pads EP in the Y direction is, for example, about 47 μm, and the distance D EP between the electrode pads EP adjacent to each other is, for example, about 3 μm.
電極パッドＥＰは、半導体ウエハＳＷの主面に形成されたメモリ回路と、配線を介して電気的に接続されており、後の工程において、電極パッドＥＰの上面にプローブ針を接触させることにより、メモリ回路へのデータの書き込みが行われる。 The electrode pad EP is electrically connected to the memory circuit formed on the main surface of the semiconductor wafer SW via wiring, and in a later process, by contacting a probe needle with the upper surface of the electrode pad EP, Data is written to the memory circuit.
次に、図４（ｂ）、図５（ａ）および（ｂ）に示すように、電極パッドＥＰを覆うように、半導体ウエハＳＷの主面上に第１絶縁部材ＩＯＬを形成する。第１絶縁部材ＩＯＬは、無機絶縁膜であり、例えば酸窒化シリコン（ＳｉＯＮ）膜、酸化シリコン（ＳｉＯ２）膜または窒化シリコン（Ｓｉ３Ｎ４）膜などからなり、これらの膜は、例えばプラズマＣＶＤ（Chemical Vapor Deposition）法により形成される。第１絶縁部材ＩＯＬの厚さは、例えば０．６μｍ〜０．８μｍ程度である。また、例えば窒化シリコン（Ｓｉ３Ｎ４）膜のヤング率は、２５０ＧＰａ〜３００ＧＰａ程度である。 Next, as shown in FIGS. 4B, 5A, and 5B, a first insulating member IOL is formed on the main surface of the semiconductor wafer SW so as to cover the electrode pads EP. The first insulating member IOL is an inorganic insulating film, and is made of, for example, a silicon oxynitride (SiON) film, a silicon oxide (SiO 2 ) film, a silicon nitride (Si 3 N 4 ) film, or the like. It is formed by the CVD (Chemical Vapor Deposition) method. The thickness of the first insulating member IOL is, for example, about 0.6 μm to 0.8 μm. For example, the Young's modulus of a silicon nitride (Si 3 N 4 ) film is about 250 GPa to 300 GPa.
次に、リソグラフィ技術により形成されたレジストパターンをマスク（図示は省略）として、第１絶縁部材ＩＯＬをエッチングして、電極パッドＥＰの上面を露出させる開口部ＯＰ１を形成する。Ｘ方向において開口部ＯＰ１の幅ＷＯＰ１は、例えば１００μｍ程度である。また、Ｙ方向において開口部ＯＰ１の幅ＬＯＰ１は、例えば４５μｍ程度であり、互いに隣り合う開口部ＯＰ１の間隔ＤＯＰ１は、例えば５μｍ程度である。 Next, using the resist pattern formed by lithography as a mask (not shown), the first insulating member IOL is etched to form an opening OP1 that exposes the upper surface of the electrode pad EP. The width W OP1 of the opening OP1 in the X direction is, for example, about 100 μm. In addition, the width L OP1 of the opening OP1 in the Y direction is, for example, about 45 μm, and the interval D OP1 between the openings OP1 adjacent to each other is, for example, about 5 μm.
このように、第１絶縁部材ＩＯＬに開口部ＯＰ１を形成しても、電極パッドＥＰの周縁と開口部ＯＰ１の開口端との距離は１μｍ以上あることから、レジストパターンの合わせズレまたは第１絶縁部材ＩＯＬのオーバーエッチングなどが生じても、電極パッドＥＰの周縁が開口部ＯＰ１から露出しないようにすることができる。 Thus, even if the opening OP1 is formed in the first insulating member IOL, the distance between the peripheral edge of the electrode pad EP and the opening end of the opening OP1 is 1 μm or more. Even if overetching of the member IOL or the like occurs, the periphery of the electrode pad EP can be prevented from being exposed from the opening OP1.
２．第２絶縁部材形成（工程Ｓ２）
次に、図６（ａ）および（ｂ）に示すように、半導体ウエハＳＷの主面上に第２絶縁部材ＯＬを形成する。第２絶縁部材ＯＬは、有機絶縁膜であり、例えばポリイミド膜などからなり、この膜は、例えば回転塗布法により形成される。第２絶縁部材ＯＬの厚さは、例えば５μｍ程度である。また、第２絶縁部材ＯＬの弾性率は、第１絶縁部材ＩＯＬの弾性率よりも低く、例えばポリイミド膜のヤング率は、３ＧＰａ〜７ＧＰａ程度である。
2. Second insulating member formation (step S2)
Next, as shown in FIGS. 6A and 6B, a second insulating member OL is formed on the main surface of the semiconductor wafer SW. The second insulating member OL is an organic insulating film made of, for example, a polyimide film, and this film is formed by, for example, a spin coating method. The thickness of the second insulating member OL is, for example, about 5 μm. The elastic modulus of the second insulating member OL is lower than the elastic modulus of the first insulating member IOL. For example, the Young's modulus of the polyimide film is about 3 GPa to 7 GPa.
後の工程において、電極パッドＥＰと電気的に接続する再配置配線ＲＷを形成するが、第１絶縁部材ＩＯＬ上に直接再配置配線ＲＷを形成すると、実装（組み立て）時または実使用環境におけるストレスにより、再配置配線ＲＷまたはこの再配置配線ＲＷよりも下側（下層）に位置する層（配線層または第１絶縁部材ＩＯＬを含む絶縁層など）にダメージ（例えば断線または亀裂など）が発生する恐れがある。他にも、形成する第１絶縁部材ＩＯＬの厚さが薄い場合には、この第１絶縁部材ＩＯＬの下側（下層）に位置する配線と、第１絶縁部材ＩＯＬ上に形成された再配置配線ＲＷとの間で容量を持たせることが困難となり、ノイズの影響で所望の電気特性が得られなくなる恐れもある。そこで、これらを抑制するために、第１絶縁部材ＩＯＬ上に第２絶縁部材ＯＬを形成している。 In a later step, the rearrangement wiring RW that is electrically connected to the electrode pad EP is formed. However, if the rearrangement wiring RW is formed directly on the first insulating member IOL, stress in mounting (assembly) or in an actual use environment As a result, damage (for example, disconnection or cracking) occurs in the rearrangement wiring RW or a layer (an insulating layer including the first insulating member IOL or the like) located below (lower layer) the rearrangement wiring RW. There is a fear. In addition, when the thickness of the first insulating member IOL to be formed is thin, the wiring located on the lower side (lower layer) of the first insulating member IOL and the rearrangement formed on the first insulating member IOL It is difficult to provide a capacity with the wiring RW, and there is a possibility that desired electrical characteristics cannot be obtained due to the influence of noise. Therefore, in order to suppress these, the second insulating member OL is formed on the first insulating member IOL.
次に、リソグラフィ技術により形成されたレジストパターンをマスク（図示は省略）として、第２絶縁部材ＯＬをエッチングして、電極パッドＥＰの上面を露出させる開口部ＯＰ２を形成する。 Next, using the resist pattern formed by the lithography technique as a mask (not shown), the second insulating member OL is etched to form an opening OP2 that exposes the upper surface of the electrode pad EP.
第２絶縁部材ＯＬは半透明であるため、第２絶縁部材ＯＬに形成される開口部ＯＰ２の開口端を、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の開口端の内側に配置した場合、後の工程において、プローブ針を電極パッドＥＰに接触する際、プローブ針を接触する位置を特定することが難しくなる。そこで、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１が確実に露出するように、第２絶縁部材ＯＬに開口部ＯＰ２を形成する。すなわち、Ｘ方向において第２絶縁部材ＯＬに形成される開口部ＯＰ２の幅ＷＯＰ２は、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＷＯＰ１と同じか、それよりも大きく、Ｙ方向において第２絶縁部材ＯＬに形成される開口部ＯＰ２の幅ＬＯＰ２は、第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＬＯＰ１と同じか、それよりも大きくなるように、第２絶縁部材ＯＬに開口部ＯＰ２を形成する。 Since the second insulating member OL is translucent, the opening end of the opening OP2 formed in the second insulating member OL is disposed inside the opening end of the opening OP1 formed in the first insulating member IOL. In the subsequent process, when the probe needle is brought into contact with the electrode pad EP, it is difficult to specify the position where the probe needle is brought into contact. Therefore, the opening OP2 is formed in the second insulating member OL so that the opening OP1 formed in the first insulating member IOL is reliably exposed. That is, the width W OP2 of the opening OP2 formed in the second insulating member OL in the X direction is the same as or larger than the width W OP1 of the opening OP1 formed in the first insulating member IOL, and the Y direction In the second insulating member OL, the width L OP2 of the opening OP2 is equal to or larger than the width L OP1 of the opening OP1 formed in the first insulating member IOL. An opening OP2 is formed in the member OL.
その後、半導体ウエハＳＷに対して、例えば３００℃〜４００℃程度の温度で熱処理を行い、第２絶縁部材ＯＬを硬化する。 Thereafter, the semiconductor wafer SW is heat-treated at a temperature of about 300 ° C. to 400 ° C., for example, to cure the second insulating member OL.
３．データ書き込み（プロービング）（工程Ｓ３）
次に、図７（ａ）および（ｂ）に示すように、電極パッドＥＰにプローブ針ＰＮを接触させて、半導体ウエハＳＷの主面に形成されたメモリ回路にデータを書き込む。データの書き込み以外にも、メモリ回路の初期故障などを調べるスクリーニングテストなども行う。スクリーニングの結果を基に、不良メモリセルのいれかえ、情報の再書き込みなどを行うことができる。
3. Data writing (probing) (step S3)
Next, as shown in FIGS. 7A and 7B, the probe needle PN is brought into contact with the electrode pad EP, and data is written into the memory circuit formed on the main surface of the semiconductor wafer SW. In addition to data writing, screening tests are also conducted to check for initial failures in memory circuits. Based on the result of screening, replacement of a defective memory cell, rewriting of information, and the like can be performed.
このように、第２絶縁部材ＯＬを硬化する熱処理を行った後に、メモリ回路にデータを書き込んでいるので、メモリ回路に書き込んだデータの消失を回避することができる。 Thus, since the data is written in the memory circuit after the heat treatment for curing the second insulating member OL, it is possible to avoid the loss of the data written in the memory circuit.
プローブ針ＰＮは、例えばタングステン（Ｗ）のような硬い金属からなり、また先端が尖端となっているため、アルミニウム（Ａｌ）膜を主導電層とする電極パッドＥＰの上面には、プローブ痕が生じる。 Since the probe needle PN is made of a hard metal such as tungsten (W) and has a pointed tip, a probe mark is formed on the upper surface of the electrode pad EP having an aluminum (Al) film as a main conductive layer. Arise.
４．カバー膜形成（工程Ｓ４）
次に、図８（ａ）および（ｂ）に示すように、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側を埋め込むように、カバー膜ＣＦを形成する。これにより、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１から露出する電極パッドＥＰの上面をカバー膜ＣＦによって被覆する。
4). Cover film formation (step S4)
Next, as shown in FIGS. 8A and 8B, the cover film CF is formed so as to fill the inside of the opening end of the opening OP1 formed in the first insulating member IOL. Thus, the upper surface of the electrode pad EP exposed from the opening OP1 formed in the first insulating member IOL is covered with the cover film CF.
カバー膜ＣＦは、例えばニッケル（Ｎｉ）などからなり、例えばめっき法、特に無電解めっき法を用いて形成される。また、カバー膜ＣＦは、ニッケル（Ｎｉ）膜に限定されるものではない。例えばカバー膜ＣＦは、下層からニッケル（Ｎｉ）膜、パラジウム（Ｐｄ）膜および金（Ａｕ）膜の順に形成した積層膜（Ｎｉ／Ｐｄ／Ａｕ）、下層からニッケル（Ｎｉ）膜および金（Ａｕ）膜の順に形成した積層膜（Ｎｉ／Ａｕ）、または下層からニッケル（Ｎｉ）膜およびパラジウム（Ｐｄ）膜の順に形成した積層膜（Ｎｉ／Ｐｄ）であってもよい。また、本実施の形態のように、電極パッドＥＰが、アルミニウム（Ａｌ）膜を主成分とする材料からなる場合には、イオン化傾向の小さい金属（例えば亜鉛（Ｚｎ））を用いてジンケート処理（亜鉛（Ｚｎ）とアルミニウム（Ａｌ）との置換反応）を行ってから、ニッケル（Ｎｉ）膜を形成してもよい。 The cover film CF is made of, for example, nickel (Ni), and is formed by using, for example, a plating method, particularly an electroless plating method. Further, the cover film CF is not limited to a nickel (Ni) film. For example, the cover film CF is a laminated film (Ni / Pd / Au) formed in the order of a nickel (Ni) film, a palladium (Pd) film, and a gold (Au) film from the lower layer, and a nickel (Ni) film and gold (Au) from the lower layer. ) A laminated film (Ni / Au) formed in the order of the films, or a laminated film (Ni / Pd) formed in the order of the nickel (Ni) film and the palladium (Pd) film from the lower layer. Further, when the electrode pad EP is made of a material mainly composed of an aluminum (Al) film as in the present embodiment, a zincate treatment (for example, zinc (Zn)) using a metal having a low ionization tendency (for example, zinc (Zn)) A nickel (Ni) film may be formed after performing a substitution reaction between zinc (Zn) and aluminum (Al).
カバー膜ＣＦの厚さは、第１絶縁部材ＩＯＬの厚さ（例えば０．６μｍ〜０．８μｍ）とほぼ同じ厚さである。しかし、電極パッドＥＰの上面を覆っていればよいので、カバー膜ＣＦの厚さは、第１絶縁部材ＩＯＬの厚さよりも薄くてもよく（例えば０．１μｍ）、または厚くてもよい。しかし、カバー膜ＣＦの厚さが厚くなりすぎると、カバー膜ＣＦが第２絶縁部材ＯＬの上面にも形成されて、互いに隣り合う電極パッドＥＰのそれぞれの上面に形成されたカバー膜ＣＦが接続し、互いに隣り合う電極パッドＥＰが短絡する恐れがある。さらに、めっきに要する時間および材料費などを考慮すると、カバー膜ＣＦの厚い方の厚さは、第１絶縁部材ＩＯＬの厚さとほぼ同じ厚さが好ましい。 The thickness of the cover film CF is substantially the same as the thickness (for example, 0.6 μm to 0.8 μm) of the first insulating member IOL. However, since the upper surface of the electrode pad EP only needs to be covered, the thickness of the cover film CF may be thinner (for example, 0.1 μm) or thicker than the first insulating member IOL. However, if the cover film CF becomes too thick, the cover film CF is also formed on the upper surface of the second insulating member OL, and the cover films CF formed on the upper surfaces of the electrode pads EP adjacent to each other are connected. In addition, the electrode pads EP adjacent to each other may be short-circuited. Furthermore, in consideration of the time required for plating, material costs, and the like, it is preferable that the thickness of the cover film CF is substantially the same as the thickness of the first insulating member IOL.
５．再配置配線形成（工程Ｓ５）
次に、図９（ａ）および（ｂ）に示すように、第２絶縁部材ＯＬ上に、カバー膜ＣＦと電気的に接続するシード層ＳＬを形成する。シード層ＳＬは、後の工程において形成される再配置配線ＲＷに対するシード（Seed）としての役割を担う層であり、例えばスパッタリング法により形成される。シード層ＳＬは、例えばチタン（Ｔｉ）膜および銅（Ｃｕ）膜を順に形成した積層膜からなり、その厚さ（総厚）は、例えば０．３μｍ程度である。詳しくは、チタン（Ｔｉ）膜の厚さが０．２μｍ程度、銅（Ｃｕ）膜の厚さが０．１μｍ程度である。なお、シード層ＳＬは、無電解めっき法により形成してもよい。
5. Relocation wiring formation (step S5)
Next, as shown in FIGS. 9A and 9B, a seed layer SL that is electrically connected to the cover film CF is formed on the second insulating member OL. The seed layer SL is a layer that plays a role as a seed for the rearrangement wiring RW formed in a later step, and is formed by, for example, a sputtering method. The seed layer SL is composed of a laminated film in which, for example, a titanium (Ti) film and a copper (Cu) film are sequentially formed, and the thickness (total thickness) is, for example, about 0.3 μm. Specifically, the thickness of the titanium (Ti) film is about 0.2 μm, and the thickness of the copper (Cu) film is about 0.1 μm. Note that the seed layer SL may be formed by an electroless plating method.
続いて、半導体ウエハＳＷの主面上に、リソグラフィ技術によりレジストパターンＲＰを形成する。レジストパターンＲＰには、シード層ＳＬの一部を露出して、再配置配線形成用の開口部ＯＰ４が形成されている。図９（ａ）は、このレジストパターンＲＰが形成された後の状態を示している。 Subsequently, a resist pattern RP is formed on the main surface of the semiconductor wafer SW by a lithography technique. In the resist pattern RP, a part of the seed layer SL is exposed, and an opening OP4 for forming a rearrangement wiring is formed. FIG. 9A shows a state after the resist pattern RP is formed.
続いて、レジストパターンＲＰに形成された開口部ＯＰ４に露出するシード層ＳＬ上に、電解めっき法を用いて、再配置配線ＲＷを形成する。このとき、デバイス領域ＤＲの外側にまで延びているシード層ＳＬを給電用の配線として用いる。また、再配置配線ＲＷは、具体的には、第２絶縁部材ＯＬ上にカバー膜ＣＦと電気的に接続して形成され、デバイス領域（図４に示すデバイス領域ＤＲ）の中央部側に向かって這うように形成される。再配置配線ＲＷは、例えば銅（Ｃｕ）からなり、その厚さは、例えば５μｍ程度である。 Subsequently, the rearrangement wiring RW is formed on the seed layer SL exposed in the opening OP4 formed in the resist pattern RP using an electrolytic plating method. At this time, the seed layer SL extending to the outside of the device region DR is used as a power supply wiring. Further, the rearrangement wiring RW is specifically formed on the second insulating member OL so as to be electrically connected to the cover film CF, and is directed toward the center of the device region (device region DR shown in FIG. 4). It is formed to meet. The rearrangement wiring RW is made of, for example, copper (Cu) and has a thickness of, for example, about 5 μm.
次に、図１０（ａ）および（ｂ）に示すように、レジストパターンＲＰを除去した後、再配置配線ＲＷをマスクとして、露出しているシード層ＳＬを、ウエットエッチング法を用いて除去する。これにより、再配置配線ＲＷ下のシード層ＳＬを残し、それ以外のレジストパターンＲＰ下にあったシード層ＳＬを除去する。 Next, as shown in FIGS. 10A and 10B, after removing the resist pattern RP, the exposed seed layer SL is removed by wet etching using the rearrangement wiring RW as a mask. . Thereby, the seed layer SL under the rearrangement wiring RW is left, and the seed layer SL under the other resist pattern RP is removed.
再配置配線ＲＷは、デバイス領域の中央部側の第２絶縁部材ＯＬ上から、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側にかけて形成される。すなわち、再配置配線ＲＷの一端部は、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に位置し、他端部は、デバイス領域の中央部側の第２絶縁部材ＯＬ上に位置する。 The rearrangement wiring RW is formed from the second insulating member OL on the center side of the device region to the inside of the opening end of the opening OP1 formed in the first insulating member IOL. That is, one end portion of the rearrangement wiring RW is located inside the opening end of the opening portion OP1 formed in the first insulating member IOL, and the other end portion is on the second insulating member OL on the center side of the device region. Located in.
Ｘ方向においては、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側、または第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＸ方向に互いに対向する２つの開口端のうち、デバイス領域の外周部側の開口端上に、再配置配線ＲＷの一端部の端面が位置するように、再配置配線ＲＷは形成される。言い換えれば、再配置配線ＲＷのうち、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に配置される部分のＸ方向における幅ＷＲＷは、カバー膜ＣＦのＸ方向における幅（長さ）、または第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＸ方向における幅ＷＯＰ１と同じか、それよりも小さい。 In the X direction, the inside of the opening end of the opening OP1 formed in the first insulating member IOL or the two opening ends facing each other in the X direction of the opening OP1 formed in the first insulating member IOL, The rearrangement wiring RW is formed so that the end face of one end of the rearrangement wiring RW is positioned on the opening end on the outer peripheral side of the device region. In other words, of the rearrangement wiring RW, the width W RW in the X direction of the portion disposed inside the opening end of the opening OP1 formed in the first insulating member IOL is the width in the X direction of the cover film CF ( Length), or the width W OP1 in the X direction of the opening OP1 formed in the first insulating member IOL, or smaller than that.
Ｙ方向においては、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＹ方向に互いに対向する２つの開口端上から内側に、再配置配線ＲＷは形成される。言い換えれば、再配置配線ＲＷのうち、電極パッドＥＰの直上に配置される部分のＹ方向における幅ＬＲＷは、カバー膜ＣＦのＹ方向における幅（長さ）、または第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＹ方向における幅ＬＯＰ１と同じか、それよりも小さい。 In the Y direction, the rearrangement wiring RW is formed from above the two opening ends facing each other in the Y direction of the opening OP1 formed in the first insulating member IOL. In other words, the width LRW in the Y direction of the portion of the rearrangement wiring RW that is disposed immediately above the electrode pad EP is formed in the width (length) of the cover film CF in the Y direction or in the first insulating member IOL. The opening portion OP1 is equal to or smaller than the width L OP1 in the Y direction.
このように、Ｙ方向において再配置配線ＲＷの幅ＬＲＷの上限を、カバー膜ＣＦのＹ方向における幅（長さ）、または開口部ＯＰ１のＹ方向における幅ＬＯＰ１と同じとすることにより、互いに隣り合う電極パッドＥＰにそれぞれ電気的に接続する再配置配線ＲＷの間隔は、例えば５μｍ以上となる。また、Ｙ方向において再配置配線ＲＷの幅ＬＲＷの上限を、カバー膜ＣＦのＹ方向における幅（長さ）、または開口部ＯＰ１のＹ方向における幅ＬＯＰ１よりも小さくすることにより、互いに隣り合う電極パッドＥＰにそれぞれ電気的に接続する再配置配線ＲＷの間隔（距離）を、互いに隣り合うカバー膜ＣＦ同士の間隔（距離）よりも大きくとることができる。これらにより、互いに隣り合う再配置配線ＲＷの接触を防ぐことができる。 Thus, the upper limit of the width L RW relocation wiring RW in the Y direction, the width in the Y direction of the cover film CF (length), or by the same as the width L OP1 in the Y direction of the opening OP1, The interval between the rearrangement wirings RW electrically connected to the electrode pads EP adjacent to each other is, for example, 5 μm or more. Further, the upper limit of the width L RW relocation wiring RW in the Y direction, the width in the Y direction of the cover film CF (length), or to be smaller than the width L OP1 in the Y direction of the opening OP1, next to one another The interval (distance) between the rearrangement wirings RW electrically connected to the matching electrode pads EP can be made larger than the interval (distance) between the cover films CF adjacent to each other. Accordingly, it is possible to prevent the adjacent rearrangement wirings RW from contacting each other.
ところで、再配置配線ＲＷのＸ方向における幅ＷＲＷが、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＸ方向における幅ＷＯＰ１よりも小さい場合、または再配置配線ＲＷのＹ方向における幅ＬＲＷが、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＹ方向における幅ＬＯＰ１よりも小さい場合は、電極パッドＥＰの直上の一部領域は、再配置配線ＲＷによって覆われない。しかし、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に位置する電極パッドＥＰの上面は、カバー膜ＣＦで覆われているので、電極パッドＥＰの上面は露出しない。従って、後の工程において、再配置配線ＲＷを覆う第３絶縁部材ＳＲを形成しても、電極パッドＥＰと第３絶縁部材ＳＲとが直接接触しないので、前述した電極パッドＥＰの変質（腐食など）は解消される。 Incidentally, the width W RW in the X direction of the rearrangement wiring RW is smaller than the width W OP1 in the X direction of the opening OP1 formed in the first insulating member IOL, or the width L in the Y direction of the rearrangement wiring RW. When RW is smaller than the width L OP1 in the Y direction of the opening OP1 formed in the first insulating member IOL, a partial region directly above the electrode pad EP is not covered with the rearrangement wiring RW. However, since the upper surface of the electrode pad EP located inside the opening end of the opening OP1 formed in the first insulating member IOL is covered with the cover film CF, the upper surface of the electrode pad EP is not exposed. Therefore, even if the third insulating member SR that covers the rearrangement wiring RW is formed in the subsequent process, the electrode pad EP and the third insulating member SR are not in direct contact with each other. ) Is resolved.
さらに、不要なシード層ＳＬを除去する際には、例えばウエットエッチング法（または、ウエットエッチング法を適用した後にドライエッチング法）を用いるが、電極パッドＥＰをエッチング液に直接晒すと、電極パッドＥＰが変質（腐食、形状変化など）する。しかし、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に位置する電極パッドＥＰの上面は、カバー膜ＣＦで覆われているので、電極パッドＥＰの上面は露出しない。従って、ウエットエッチング法を用いて不要なシード層ＳＬを除去しても、電極パッドＥＰが変質（腐食、形状変化など）して、電気特性不良を引き起こすことはない。 Further, when removing the unnecessary seed layer SL, for example, a wet etching method (or a dry etching method after applying the wet etching method) is used. However, when the electrode pad EP is directly exposed to an etching solution, the electrode pad EP is used. Is altered (corrosion, shape change, etc.). However, since the upper surface of the electrode pad EP located inside the opening end of the opening OP1 formed in the first insulating member IOL is covered with the cover film CF, the upper surface of the electrode pad EP is not exposed. Therefore, even if the unnecessary seed layer SL is removed using the wet etching method, the electrode pad EP is not altered (corrosion, shape change, etc.), and electrical characteristics are not deteriorated.
また、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＸ方向に互いに対向する２つの開口端の一方の開口端から他方の開口端まで、および第１絶縁部材ＩＯＬに形成された開口部ＯＰ１のＹ方向に互いに対向する２つの開口端の一方の開口端から他方の開口端まで、すなわち、電極パッドＥＰの直上に、開口部ＯＰ１と同じ平面形状を有する再配置配線ＲＷを形成してもよい。この場合は、再配置配線ＲＷとカバー膜ＣＦとの接触面積が増えるので、接触抵抗をより低減することができる。 Also, from one opening end to the other opening end of two opening ends facing each other in the X direction of the opening OP1 formed in the first insulating member IOL and the opening OP1 formed in the first insulating member IOL. Even if the rearrangement wiring RW having the same planar shape as the opening OP1 is formed from one opening end of the two opening ends facing each other in the Y direction to the other opening end, that is, immediately above the electrode pad EP. Good. In this case, the contact area between the rearrangement wiring RW and the cover film CF increases, so that the contact resistance can be further reduced.
この場合、電極パッドＥＰと再配置配線ＲＷとの合わせずれが生じると、電極パッドＥＰの直上の一部領域は、再配置配線ＲＷによって覆われない。しかし、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に位置する電極パッドＥＰの上面は、カバー膜ＣＦで覆われているので、電極パッドＥＰの上面は露出しない。従って、前述したように、電極パッドＥＰの腐食、さらには、後の工程において形成する第３絶縁部材ＳＲが、電極パッドＥＰから剥離するなどの問題を回避することができる。 In this case, when a misalignment between the electrode pad EP and the rearrangement wiring RW occurs, a partial region immediately above the electrode pad EP is not covered with the rearrangement wiring RW. However, since the upper surface of the electrode pad EP located inside the opening end of the opening OP1 formed in the first insulating member IOL is covered with the cover film CF, the upper surface of the electrode pad EP is not exposed. Therefore, as described above, it is possible to avoid problems such as corrosion of the electrode pad EP and further peeling of the third insulating member SR formed in a later process from the electrode pad EP.
図１１（ａ）および（ｂ）に、再配置配線ＲＷの他の構成例を示す。デバイス領域の外周部側に形成される再配置配線ＲＷの一端部は、デバイス領域の外周部側の第２絶縁部材ＯＬ上に位置しており、デバイス領域の外周端まで接近してもよい。また、本実施の形態では、図１に示すように、複数の電極パッドＥＰがデバイス領域の外周部に設けられている構成について説明したが、複数の電極パッドＥＰはデバイス領域の中央部に配置されていてもよい。この場合、複数の再配置配線ＲＷのうちの幾つか、または全ては、デバイス領域ＤＲ（図４参照）の外周部側に向かって引き出される。 FIGS. 11A and 11B show another configuration example of the rearrangement wiring RW. One end portion of the rearrangement wiring RW formed on the outer peripheral portion side of the device region is located on the second insulating member OL on the outer peripheral portion side of the device region, and may approach the outer peripheral end of the device region. In the present embodiment, as shown in FIG. 1, the configuration in which the plurality of electrode pads EP are provided in the outer peripheral portion of the device region has been described. However, the plurality of electrode pads EP are arranged in the central portion of the device region. May be. In this case, some or all of the plurality of rearrangement wirings RW are drawn toward the outer peripheral side of the device region DR (see FIG. 4).
６．第３絶縁部材形成（工程Ｓ６）
次に、図１２（ａ）および（ｂ）に示すように、半導体ウエハＳＷの主面上に第３絶縁部材ＳＲを形成する。本実施の形態における第３絶縁部材ＳＲは、有機絶縁膜であり、具体的な材料としては、例えばポリイミド膜などである。本実施の形態では、この第３絶縁部材ＳＲが、最表面の保護膜となる。また、後の変形例においても説明するが、ポリイミド膜に代えて、フィラー（例えばシリカ）を含有するエポキシ樹脂を第３絶縁部材ＳＲとして用いてもよい。
6). Third insulation member formation (step S6)
Next, as shown in FIGS. 12A and 12B, a third insulating member SR is formed on the main surface of the semiconductor wafer SW. The third insulating member SR in the present embodiment is an organic insulating film, and a specific material is, for example, a polyimide film. In the present embodiment, this third insulating member SR becomes the outermost protective film. As will be described later, an epoxy resin containing a filler (for example, silica) may be used as the third insulating member SR instead of the polyimide film.
前述したように、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に位置する電極パッドＥＰの上面は、カバー膜ＣＦで覆われている。従って、Ｘ方向において、再配置配線ＲＷの幅ＷＲＷが、カバー膜ＣＦの幅（長さ）、または第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＷＯＰ１よりも小さく、Ｙ方向において、再配置配線ＲＷの幅ＬＲＷが、カバー膜ＣＦの幅（長さ）、または第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１よりも小さくても、電極パッドＥＰの上面は露出しない。これにより、再配置配線ＲＷを覆う第３絶縁部材ＳＲは、電極パッドＥＰと直接、接触しない状態となる。 As described above, the upper surface of the electrode pad EP located inside the opening end of the opening OP1 formed in the first insulating member IOL is covered with the cover film CF. Thus, in the X direction, the width W RW relocation wiring RW is, cover film width of CF (length), or smaller than the width W OP1 of the first insulating member opening OP1 formed in IOL, in the Y direction the width L RW relocation wiring RW is, the width of the cover film CF (length), or even smaller than the width L OP1 of the first insulating member opening OP1 formed in IOL, the upper surface of the electrode pad EP is Not exposed. Thereby, the third insulating member SR covering the rearrangement wiring RW is not in direct contact with the electrode pad EP.
次に、第３絶縁部材ＳＲ上にレジストパターンをリソグラフィ技術により形成し、このレジストパターンをマスク（図示は省略）として、第３絶縁部材ＳＲの一部を、例えばエッチングにより除去する。これにより、電極パッドＥＰと電気的に接続する再配置配線ＲＷの一端部（一部）とは反対側で、第２絶縁部材ＯＬ上に位置する再配置配線ＲＷの他端部（他部）を露出させる開口部ＯＰ３を形成する。 Next, a resist pattern is formed on the third insulating member SR by lithography, and a part of the third insulating member SR is removed by, for example, etching using the resist pattern as a mask (not shown). Accordingly, the other end (other part) of the rearrangement wiring RW located on the second insulating member OL on the opposite side to one end (part) of the rearrangement wiring RW electrically connected to the electrode pad EP. An opening OP3 that exposes the surface is formed.
７．バンプ電極形成（工程Ｓ７）
次に、図１３（ａ）および（ｂ）に示すように、開口部ＯＰ３の内部に、バンプ電極を形成するために必要な電極層（電極）ＵＭを形成する。電極層ＵＭは、例えば無電解めっき法を用いて形成された銅（Ｃｕ）またはニッケル（Ｎｉ）からなる。続いて、電極層ＵＭの上面に、フラックスまたははんだペーストを供給し、さらに、はんだボールを配置した後、リフロー処理を行う。はんだボールには、例えば鉛（Ｐｂ）を実質的に含まない鉛フリーはんだ組成を有するはんだが用いられる。上記リフロー処理を行うことにより、はんだボールの表面の酸化膜がフラックスによって除去されて、はんだボールが溶融する、または、はんだボールとはんだペーストとが溶融して一体化することにより、電極層ＵＭと電気的に、かつ、機械的に接続するバンプ電極ＳＢが形成される。
7). Bump electrode formation (step S7)
Next, as shown in FIGS. 13A and 13B, an electrode layer (electrode) UM necessary for forming a bump electrode is formed inside the opening OP3. The electrode layer UM is made of, for example, copper (Cu) or nickel (Ni) formed by using an electroless plating method. Subsequently, a flux or solder paste is supplied to the upper surface of the electrode layer UM, and further, solder balls are arranged, and then a reflow process is performed. For example, solder having a lead-free solder composition that does not substantially contain lead (Pb) is used for the solder balls. By performing the reflow process, the oxide film on the surface of the solder ball is removed by the flux, and the solder ball is melted, or the solder ball and the solder paste are melted and integrated to form the electrode layer UM. Bump electrodes SB that are electrically and mechanically connected are formed.
その後、半導体ウエハＳＷを区画されたデバイス領域の間のスクライブ領域（図４に示すスクライブ領域ＬＲ）に沿って切断（個片化）することにより、本実施の形態による半導体装置（半導体チップ）ＳＣが略完成する。 Thereafter, the semiconductor wafer SW is cut (separated) along a scribe region (the scribe region LR shown in FIG. 4) between the partitioned device regions, whereby the semiconductor device (semiconductor chip) SC according to the present embodiment. Is almost completed.
このように、本実施の形態によれば、以下の効果を得ることができる。 Thus, according to the present embodiment, the following effects can be obtained.
（１）第１絶縁部材ＩＯＬ上に第２絶縁部材ＯＬを介して再配置配線ＲＷを形成することにより、再配置配線（配線、再配線）ＲＷまたはこの再配置配線ＲＷよりも下側（下層）に位置する層（配線層または第１絶縁部材ＩＯＬを含む絶縁層など）にダメージ（例えば断線または亀裂など）が発生することを抑制することができる。 (1) By forming the rearrangement wiring RW on the first insulating member IOL via the second insulating member OL, the rearrangement wiring (wiring, rewiring) RW or the lower side (lower layer) of the rearrangement wiring RW It is possible to prevent damage (for example, disconnection or cracking) from occurring in a layer (such as a wiring layer or an insulating layer including the first insulating member IOL) located in ().
（２）さらに、第２絶縁部材ＯＬを、例えば３００℃〜４００℃程度の熱処理により硬化した後に、メモリ回路にデータを書き込むことにより、データの消失を回避することができる。 (2) Furthermore, after the second insulating member OL is cured by a heat treatment of, for example, about 300 ° C. to 400 ° C., data can be avoided by writing data to the memory circuit.
（３）さらに、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側に位置する電極パッドＥＰの上面には、カバー膜ＣＦが形成されている。そのため、狭ピッチ対策として、Ｙ方向において、再配置配線ＲＷの幅ＬＲＷを第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＬＯＰ１より小さくしても、電極パッドＥＰの表面は露出した状態とならない。従って、再配置配線ＲＷを形成する際、すなわち、シード層ＳＬを除去する際の工程（ウエットエッチング法またはドライエッチング法など）における電極パッドＥＰの表面の変質（腐植、形状変化など）の問題を回避することができる。 (3) Further, a cover film CF is formed on the upper surface of the electrode pad EP located inside the opening end of the opening OP1 formed in the first insulating member IOL. Therefore, as a narrow pitch countermeasure, in the Y direction, be smaller than the width L OP1 of the opening OP1 formed a width L RW relocation wiring RW on the first insulating member IOL, the surface of the electrode pad EP is exposed It does not become a state. Therefore, when the rearrangement wiring RW is formed, that is, in the process of removing the seed layer SL (wet etching method, dry etching method, etc.), the problem of alteration (humus, shape change, etc.) of the surface of the electrode pad EP occurs. It can be avoided.
（４）さらに、Ｙ方向において、再配置配線ＲＷの幅ＬＲＷを第１絶縁部材ＩＯＬに形成される開口部ＯＰ１の幅ＬＯＰ１と同じか、または小さくできるので、Ｙ方向に互いに隣り合う再配置配線ＲＷの接触を防ぐことができる。なお、再配置配線ＲＷを構成する材料として銅（Ｃｕ）を用いる場合は、互いに隣り合う配線の間隔（距離）が近いほど、マイグレーションの問題が発生しやすいため、再配置配線ＲＷを構成する材料として銅（Ｃｕ）を用いる場合には、本実施の形態は特に有効である。 (4) Further, in the Y direction, the width L RW relocation wiring RW or equal to the width L OP1 of the opening OP1 formed in the first insulating member IOL, or can be small, re-adjacent in the Y direction It is possible to prevent the placement wiring RW from touching. Note that when copper (Cu) is used as the material constituting the rearrangement wiring RW, the closer to the distance (distance) between adjacent wirings, the more likely the problem of migration occurs. Therefore, the material constituting the rearrangement wiring RW This embodiment is particularly effective when copper (Cu) is used.
これらの効果により、本実施の形態によれば、半導体装置の信頼性を向上することができる。また、半導体装置の小型化、特に、複数の電極パッドの狭ピッチ化を実現することができる。 With these effects, according to the present embodiment, the reliability of the semiconductor device can be improved. In addition, it is possible to reduce the size of the semiconductor device, in particular, to reduce the pitch of the plurality of electrode pads.
≪変形例≫
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
≪Modification≫
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
（変形例１）
変形例１による半導体装置の製造方法について図１５および図１６を用いて説明する。なお、前述の実施の形態で説明した内容と異なる点についてのみ、説明する。図１５は、変形例１による半導体装置の製造方法において、その製造工程の流れの一例を示す工程図である。図１６（ａ）および（ｂ）はそれぞれ、変形例１による半導体装置の製造工程を示す要部平面図および要部断面図である。
(Modification 1)
A method for manufacturing a semiconductor device according to Modification 1 will be described with reference to FIGS. Only differences from the contents described in the above embodiment will be described. FIG. 15 is a process diagram showing an example of the flow of the manufacturing process in the semiconductor device manufacturing method according to the first modification. FIGS. 16A and 16B are a main part plan view and a main part cross-sectional view showing the manufacturing process of the semiconductor device according to the modified example 1, respectively.
図３に示した本実施の形態による半導体装置の製造工程では、第２絶縁部材ＯＬを形成した後に、電極パッドＥＰにプローブ針ＰＮを接触させて、メモリ回路にデータを書き込む。 In the manufacturing process of the semiconductor device according to the present embodiment shown in FIG. 3, after the second insulating member OL is formed, the probe needle PN is brought into contact with the electrode pad EP, and data is written into the memory circuit.
これに対して、変形例１では、図１５に示すように、カバー膜ＣＦを形成した後に、カバー膜ＣＦにプローブ針ＰＮを接触させて、メモリ回路にデータを書き込む。 On the other hand, in Modification 1, as shown in FIG. 15, after forming the cover film CF, the probe needle PN is brought into contact with the cover film CF, and data is written into the memory circuit.
図１６（ａ）および（ｂ）に示すように、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の開口端の内側を埋め込むように、カバー膜ＣＦを形成する。これにより、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１から露出する電極パッドＥＰの上面をカバー膜ＣＦによって被覆する。 As shown in FIGS. 16A and 16B, the cover film CF is formed so as to bury the inside of the opening end of the opening OP1 formed in the first insulating member IOL. Thus, the upper surface of the electrode pad EP exposed from the opening OP1 formed in the first insulating member IOL is covered with the cover film CF.
電極パッドＥＰの厚さは、例えば０．４μｍ〜６．０μｍ程度であり、代表的な厚さとしては１．０μｍ程度を例示することができる。しかし、電極パッドＥＰの厚さが、例えば０、４μｍ程度と薄い場合は、メモリ回路の初期故障などを調べるスクリーニングテストなどにおいて大電流を流すことができず、検査項目が限定されてしまう。一方、電極パッドＥＰの厚さが、例えば６．０μｍ程度と厚い場合は、電極パッドＥＰは、例えばアルミニウム（Ａｌ）膜を主導電層としていることから、プローブ針ＰＮによる電極パッドＥＰの変形が大きくなり、こぶまたは剥がれなどが生じる。 The thickness of the electrode pad EP is, for example, about 0.4 μm to 6.0 μm, and a typical thickness is about 1.0 μm. However, when the thickness of the electrode pad EP is as thin as about 0 to 4 μm, for example, a large current cannot be passed in a screening test for examining an initial failure of the memory circuit, and the inspection items are limited. On the other hand, when the thickness of the electrode pad EP is as thick as about 6.0 μm, for example, the electrode pad EP is made of, for example, an aluminum (Al) film as a main conductive layer. It becomes larger, causing humps or peeling.
しかし、変形例１によれば、カバー膜ＣＦにプローブ針ＰＮを接触させているので、大電流を流すことができる。また、ニッケル（Ｎｉ）膜はアルミニウム（Ａｌ）膜よりも硬いことから（アルミニウム（Ａｌ）のモース硬度は２〜２．９、ニッケル（Ｎｉ）のモース強度は５、タングステンカーバイト（ＷＣ）のモース強度は９）、プローブ針ＰＮの接触によるカバー膜ＣＦの変形は、電極パッドＥＰの変形よりも小さくすることができる。 However, according to the first modification, the probe needle PN is brought into contact with the cover film CF, so that a large current can flow. Further, since the nickel (Ni) film is harder than the aluminum (Al) film (the Mohs hardness of aluminum (Al) is 2 to 2.9, the Mohs strength of nickel (Ni) is 5, and tungsten carbide (WC) The Mohs strength is 9), and the deformation of the cover film CF due to the contact with the probe needle PN can be made smaller than the deformation of the electrode pad EP.
（変形例２）
変形例２による半導体装置について図１７および図１８を用いて説明する。なお、変形例１と同様、前述の実施の形態で説明した内容と異なる点についてのみ、説明する。図１７は、変形例２による半導体装置の製造方法において、その製造工程の流れの一例を示す工程図である。図１８は、変形例２による半導体装置を示す要部断面図である。
(Modification 2)
A semiconductor device according to Modification 2 will be described with reference to FIGS. As in the first modification, only the points different from the contents described in the above embodiment will be described. FIG. 17 is a process diagram showing an example of the flow of the manufacturing process in the semiconductor device manufacturing method according to the second modification. FIG. 18 is a main part sectional view showing a semiconductor device according to the second modification.
変形例２による半導体装置の製造方法では、前述の実施の形態で説明した半導体ウエハ準備工程（図３に示す工程Ｓ１）から第３絶縁部材形成工程（図３に示す工程Ｓ６）までの各工程と同じ工程を実施した後、第３絶縁部材ＳＲの開口部ＯＰ３から露出する再配置配線ＲＷの表面に電極層（電極）ＵＭを形成し、さらに、以下の工程を実施する。なお、再配置配線ＲＷの表面に形成され、第３絶縁部材ＳＲの開口部ＯＰ３から露出する電極層ＵＭは、例えば金（Ａｕ）またはパラジウム（Ｐｄ）などからなり、例えば電解メッキ法により形成される。 In the method of manufacturing a semiconductor device according to Modification 2, each process from the semiconductor wafer preparation step (step S1 shown in FIG. 3) to the third insulating member formation step (step S6 shown in FIG. 3) described in the above embodiment. After performing the same process as in FIG. 5, an electrode layer (electrode) UM is formed on the surface of the rearrangement wiring RW exposed from the opening OP3 of the third insulating member SR, and the following processes are further performed. The electrode layer UM formed on the surface of the rearrangement wiring RW and exposed from the opening OP3 of the third insulating member SR is made of, for example, gold (Au) or palladium (Pd), and is formed by, for example, electrolytic plating. The
７．個片化（ウエハダイシング）（工程Ｓ２７）
半導体ウエハを区画されたデバイス領域の間のスクライブ領域に沿って切断し、個々の半導体チップに分割する。
7). Individualization (wafer dicing) (Step S27)
The semiconductor wafer is cut along scribe areas between the partitioned device areas and divided into individual semiconductor chips.
８．ダイボンディング（工程Ｓ２８）
次に、図１８に示すように、例えばその主面に複数の電極パッド（電極、ボンディングリード）ＢＰが形成された配線基板（基板）ＭＢを準備する。複数の電極パッドＢＰは、配線基板ＭＢの表面上に形成された複数の配線のそれぞれの一部分で構成され、配線基板ＭＢの表面上に形成された保護膜ＰＦにそれぞれの電極パッドＢＰに対応して形成された複数の開口部ＯＰ５から、これら上面は露出している。
8). Die bonding (Step S28)
Next, as shown in FIG. 18, for example, a wiring board (substrate) MB having a plurality of electrode pads (electrodes, bonding leads) BP formed on the main surface thereof is prepared. The plurality of electrode pads BP includes a part of each of the plurality of wirings formed on the surface of the wiring board MB, and corresponds to each electrode pad BP on the protective film PF formed on the surface of the wiring board MB. These upper surfaces are exposed from the plurality of openings OP5 formed in this manner.
次に、配線基板ＭＢの表面上のチップ搭載領域に接着剤ＣＭを塗布する。接着剤ＣＭには、例えば熱硬化性のエポキシ樹脂が用いられる。続いて、チップ搭載領域に接着剤ＣＭを介して半導体チップを搭載し、その後、熱処理を行い、接着剤ＣＭを硬化させることにより、チップ搭載領域に半導体チップを接着固定する。 Next, an adhesive CM is applied to the chip mounting area on the surface of the wiring board MB. For the adhesive CM, for example, a thermosetting epoxy resin is used. Subsequently, the semiconductor chip is mounted on the chip mounting area via the adhesive CM, and then heat treatment is performed to cure the adhesive CM, thereby bonding and fixing the semiconductor chip to the chip mounting area.
９．ワイヤボンディング（工程Ｓ２９）
次に、半導体基板ＳＵＢの主面上に形成され、第３絶縁部材ＳＲに形成された複数の開口部ＯＰ３にそれぞれ露出する複数の再配置配線ＲＷの他端部と、配線基板ＭＢの表面上に形成され、保護膜ＰＦに形成された複数の開口部ＯＰ５にそれぞれ露出する複数の電極パッドＢＰとを、導電性ワイヤ（導電性部材、ボンディングワイヤ）ＢＷ、例えば金（Ａｕ）線を用いてそれぞれ電気的に接続する。詳細には、導電性ワイヤＢＷの一部は、前述の電極層ＵＭを介して再配置配線ＲＷの他端部と電気的に接続され、導電性ワイヤＢＷの他部は、配線基板ＭＢの電極パッドＢＰと電気的に接続される。
9. Wire bonding (process S29)
Next, the other end of the plurality of rearrangement wirings RW formed on the main surface of the semiconductor substrate SUB and exposed to the plurality of openings OP3 formed in the third insulating member SR, and on the surface of the wiring substrate MB The plurality of electrode pads BP that are formed in the protective film PF and exposed in the plurality of openings OP5 are respectively formed using a conductive wire (conductive member, bonding wire) BW, for example, a gold (Au) wire. Connect each one electrically. Specifically, a part of the conductive wire BW is electrically connected to the other end portion of the rearrangement wiring RW via the electrode layer UM, and the other part of the conductive wire BW is an electrode of the wiring board MB. It is electrically connected to the pad BP.
主として、正ボンディング方式を用いるが、逆ボンディング方式を用いてもよい。正ボンディング方式は、半導体チップに形成された再配置配線ＲＷと導電性ワイヤＢＷの一端部とを接続した後に、配線基板ＭＢの表面上に配置された電極パッドＢＰと導電性ワイヤＢＷの他端部とを接続する方式である。逆ボンディング方式は、配線基板ＭＢの表面上に配置された電極パッドＢＰと導電性ワイヤＢＷの他端部とを接続した後に、半導体チップに形成された再配置配線ＲＷと導電性ワイヤＢＷの一端部とを接続する方式である。 Although the normal bonding method is mainly used, the reverse bonding method may be used. In the positive bonding method, after the rearrangement wiring RW formed on the semiconductor chip and one end of the conductive wire BW are connected, the electrode pad BP disposed on the surface of the wiring board MB and the other end of the conductive wire BW. This is a method of connecting the parts. In the reverse bonding method, after the electrode pad BP disposed on the surface of the wiring board MB and the other end of the conductive wire BW are connected, the rearrangement wiring RW formed on the semiconductor chip and one end of the conductive wire BW are connected. This is a method of connecting the parts.
変形例２では、前述の実施の形態と同様、再配置配線ＲＷは第２絶縁部材ＯＬ上に形成されているため、再配置配線ＲＷに導電性ワイヤＢＷの一部を接続する際に生じる荷重（垂直荷重）が、再配置配線ＲＷよりも下層側に位置する部材に伝わるのを抑制することができる。 In the second modification, the rearrangement wiring RW is formed on the second insulating member OL as in the above-described embodiment. Therefore, the load generated when a part of the conductive wire BW is connected to the rearrangement wiring RW. It is possible to suppress (vertical load) from being transmitted to a member positioned on the lower layer side than the rearrangement wiring RW.
１０．モールド（工程Ｓ３０）
次に、配線基板ＭＢ上に搭載された半導体チップを樹脂（図示は省略）によって封止して、樹脂封止体を形成する。使用する樹脂には、例えばフィラー（例えばシリカ）を含有した熱硬化性のエポキシ樹脂が用いられる。その後、図示はしないが、配線基板ＭＢの裏面（実装面）に外部電極である半田ボールを搭載する。変形例２でいう半導体装置ＳＣとは、これらの工程を経て取得したものを指す。
10. Mold (Process S30)
Next, the semiconductor chip mounted on the wiring board MB is sealed with a resin (not shown) to form a resin sealing body. As the resin to be used, for example, a thermosetting epoxy resin containing a filler (for example, silica) is used. Thereafter, although not shown, solder balls as external electrodes are mounted on the back surface (mounting surface) of the wiring board MB. The semiconductor device SC referred to in Modification 2 refers to a device obtained through these steps.
（変形例３）
変形例３による半導体装置について図１９、図２０および図２１を用いて説明する。なお、変形例１および２と同様、前述の実施の形態で説明した内容と異なる点についてのみ、説明する。図１９は、変形例３による半導体装置の製造方法において、その製造工程の流れの一例を示す工程図である。図２０、図２１の各々の（ａ）および（ｂ）はそれぞれ、変形例３による半導体装置の製造工程中の半導体装置の一部を拡大して示す要部平面図および要部断面図である。
(Modification 3)
A semiconductor device according to Modification 3 will be described with reference to FIGS. Similar to the first and second modifications, only the points different from the contents described in the above embodiment will be described. FIG. 19 is a process diagram showing an example of the flow of the manufacturing process in the semiconductor device manufacturing method according to the third modification. FIGS. 20 and 21 are respectively a plan view and a cross-sectional view of a main part showing an enlarged part of the semiconductor device during the manufacturing process of the semiconductor device according to the third modification. .
変形例３では、メモリ回路を有しない半導体装置について説明する。前述したメモリ回路を有する半導体装置では、メモリ回路に書き込まれたデータの消失を回避するために、図７（ａ）および（ｂ）に示したように、第２絶縁部材ＯＬを、例えば３００℃〜４００℃程度の熱処理により硬化した後に、メモリ回路にデータを書き込んだ。 In Modification 3, a semiconductor device that does not include a memory circuit will be described. In the semiconductor device having the memory circuit described above, in order to avoid erasure of data written in the memory circuit, as shown in FIGS. 7A and 7B, the second insulating member OL is, for example, 300 ° C. Data was written into the memory circuit after being cured by heat treatment at about ˜400 ° C.
これに対して、変形例３では、メモリ回路へデータを書き込む必要がないので、熱処理を施すことで第２絶縁部材ＯＬを形成する工程を実施したとしても、上記データの消失の問題は生じない。従って、この場合は、例えば図１９に示すように、半導体ウエハＳＷの主面上に電極パッドＥＰを形成した後に、電極パッドＥＰにプローブ針ＰＮを接触させて、プローブ検査を行うことができる。 On the other hand, in the third modified example, since it is not necessary to write data to the memory circuit, even if the step of forming the second insulating member OL by performing heat treatment is performed, the problem of data loss does not occur. . Therefore, in this case, as shown in FIG. 19, for example, after the electrode pad EP is formed on the main surface of the semiconductor wafer SW, the probe needle PN is brought into contact with the electrode pad EP, and the probe inspection can be performed.
変形例３による半導体装置の製造方法では、図５に示した、半導体ウエハ準備工程（図３に示す工程Ｓ１）と同じ工程を実施した後、以下の工程を実施する。 In the method for manufacturing a semiconductor device according to Modification 3, after performing the same process as the semiconductor wafer preparation process (process S1 illustrated in FIG. 3) illustrated in FIG. 5, the following processes are performed.
２．プローブ検査（工程Ｓ３２）
図２０に示すように、電極パッドＥＰにプローブ針ＰＮを接触させて、プローブ検査を行う。例えば半導体回路の電気的特性などを測定する。
2. Probe inspection (process S32)
As shown in FIG. 20, the probe inspection is performed by bringing the probe needle PN into contact with the electrode pad EP. For example, the electrical characteristics of the semiconductor circuit are measured.
プローブ針ＰＮは、例えばタングステン（Ｗ）のような硬い金属からなり、また先端が尖端となっているため、アルミニウム（Ａｌ）膜を主導電層とする電極パッドＥＰの表面には、プローブ痕が生じる。 Since the probe needle PN is made of a hard metal such as tungsten (W) and has a pointed tip, a probe mark is formed on the surface of the electrode pad EP having an aluminum (Al) film as a main conductive layer. Arise.
３．第２絶縁部材形成（工程Ｓ３３）
次に、図２１に示すように、半導体ウエハＳＷの主面上に第２絶縁部材ＯＬを形成する。第２絶縁部材ＯＬは、有機絶縁膜であり、例えばポリイミド膜などからなり、この膜は、例えば回転塗布法により形成される。第２絶縁部材ＯＬの厚さは、例えば５μｍ程度である。
3. Second insulating member formation (step S33)
Next, as shown in FIG. 21, the second insulating member OL is formed on the main surface of the semiconductor wafer SW. The second insulating member OL is an organic insulating film made of, for example, a polyimide film, and this film is formed by, for example, a spin coating method. The thickness of the second insulating member OL is, for example, about 5 μm.
後の工程において、電極パッドＥＰと電気的に接続する再配置配線ＲＷを形成するが、第１絶縁部材ＩＯＬ上に直接再配置配線ＲＷを形成すると、実装（組み立て）時または実使用環境におけるストレスにより、再配置配線ＲＷまたはこの再配置配線ＲＷよりも下側（下層）に位置する層（配線層または第１絶縁部材ＩＯＬを含む絶縁層など）にダメージ（例えば断線または亀裂など）が発生する恐れがある。他にも、形成する第１絶縁部材ＩＯＬの厚さが薄い場合には、この第１絶縁部材ＩＯＬの下側（下層）に位置する配線と、第１絶縁部材ＩＯＬ上に形成された再配置配線ＲＷとの間で容量を持たせることが困難となり、ノイズの影響で所望の電気特性が得られなくなる恐れもある。そこで、これらを抑制するために、第１絶縁部材ＩＯＬ上に第２絶縁部材ＯＬを形成している。 In a later step, the rearrangement wiring RW that is electrically connected to the electrode pad EP is formed. However, if the rearrangement wiring RW is formed directly on the first insulating member IOL, stress in mounting (assembly) or in an actual use environment As a result, damage (for example, disconnection or cracking) occurs in the rearrangement wiring RW or a layer (an insulating layer including the first insulating member IOL or the like) located below (lower layer) the rearrangement wiring RW. There is a fear. In addition, when the thickness of the first insulating member IOL to be formed is thin, the wiring located on the lower side (lower layer) of the first insulating member IOL and the rearrangement formed on the first insulating member IOL It is difficult to provide a capacity with the wiring RW, and there is a possibility that desired electrical characteristics cannot be obtained due to the influence of noise. Therefore, in order to suppress these, the second insulating member OL is formed on the first insulating member IOL.
次に、リソグラフィ技術により形成されたレジストパターンをマスク（図示は省略）として、第２絶縁部材ＯＬをエッチングして、電極パッドＥＰの上面を露出させる開口部ＯＰ２を形成する。続いて、半導体ウエハＳＷに対して、例えば３００℃〜４００℃程度の温度で熱処理を行い、第２絶縁部材ＯＬを硬化する。 Next, using the resist pattern formed by the lithography technique as a mask (not shown), the second insulating member OL is etched to form an opening OP2 that exposes the upper surface of the electrode pad EP. Subsequently, heat treatment is performed on the semiconductor wafer SW at a temperature of, for example, about 300 ° C. to 400 ° C. to cure the second insulating member OL.
ここで、前述の実施の形態との相違点として、変形例３では、図２１（ａ）および（ｂ）に示すように、第２絶縁部材ＯＬの開口部ＯＰ２の開口端が、第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端よりも内側に位置している。前述したように、変形例３では、半導体装置がメモリ回路を有していないため、電気的試験のためのプローブ工程を行った後に、第２絶縁部材ＯＬを形成する、言い換えると、熱処理を施すことができる。すなわち、変形例３による半導体装置の製造方法は、第２絶縁部材ＯＬを形成した後にプローブ工程を行わないため、半透明である第２絶縁部材ＯＬの開口部ＯＰ２の開口端を第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端よりも内側に配置することができる。 Here, as a difference from the above-described embodiment, in Modification 3, as shown in FIGS. 21A and 21B, the opening end of the opening OP2 of the second insulating member OL is the first insulating member. It is located inside the opening end of the opening OP1 of the member IOL. As described above, in Modification 3, since the semiconductor device does not have a memory circuit, the second insulating member OL is formed after the probe process for the electrical test is performed, in other words, heat treatment is performed. be able to. That is, in the method of manufacturing a semiconductor device according to Modification 3, since the probe step is not performed after the second insulating member OL is formed, the opening end of the opening OP2 of the second insulating member OL that is translucent is used as the first insulating member. It can arrange | position inside the opening end of opening part OP1 of IOL.
そして、図２１（ａ）および（ｂ）に示すように、第２絶縁部材ＯＬの開口部ＯＰ２の開口端を第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端よりも内側に位置させることで、互いに隣り合う電極パッドＥＰのピッチ（間隔）を、より狭くすることができる。 And as shown to Fig.21 (a) and (b), by positioning the opening end of opening part OP2 of 2nd insulating member OL inside the opening end of opening part OP1 of 1st insulating member IOL, The pitch (interval) between the electrode pads EP adjacent to each other can be made narrower.
その後、図８から図１２に示した、カバー膜形成工程（図３に示す工程Ｓ４）からバンプ電極形成工程（図３に示す工程Ｓ７）までの各工程と同じ工程を実施する。 Thereafter, the same steps as the steps from the cover film forming step (step S4 shown in FIG. 3) to the bump electrode forming step (step S7 shown in FIG. 3) shown in FIGS.
なお、図示はしないが、変形例３のように、第２絶縁部材ＯＬの開口部ＯＰ２の開口端を第１絶縁部材ＩＯＬの開口部ＯＰ１の開口端よりも内側に位置させる場合には、再配置配線ＲＷの幅ＬＲＷは、Ｙ方向（半導体チップの辺に沿った方向）において、第２絶縁部材ＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１、好ましくは、カバー膜ＣＦの幅（長さ）と同じか、それよりも小さくする。 Although not shown, when the opening end of the opening OP2 of the second insulating member OL is positioned on the inner side of the opening end of the opening OP1 of the first insulating member IOL as in Modification 3, it is necessary to re- The width L RW of the placement wiring RW is, in the Y direction (the direction along the side of the semiconductor chip), the width L OP1 of the opening OP1 formed in the second insulating member OL, preferably the width (long) of the cover film CF. )) Or smaller than that.
（変形例４）
変形例４による半導体装置について、図２２乃至図２６を用いて説明する。なお、変形例１乃至３と同様、前述の実施の形態で説明した内容と異なる点についてのみ、説明する。図２２は、変形例４による半導体装置の製造方法において、その製造工程の流れの一例を示す工程図である。図２３〜図２６の各々の（ａ）および（ｂ）はそれぞれ、変形例４による半導体装置の製造工程中の半導体装置の一部を拡大して示す要部平面図および要部断面図である。図２３（ａ）および（ｂ）はそれぞれ、柱状電極形成工程（工程Ｓ４６）を説明する要部平面図および要部断面図である。図２４（ａ）および（ｂ）はそれぞれ、樹脂封止工程（工程Ｓ４７）を説明する要部平面図および要部断面図である。図２５（ａ）および（ｂ）はそれぞれ、研削工程（工程Ｓ４８）を説明する要部平面図および要部断面図である。図２６（ａ）および（ｂ）はそれぞれ、バンプ電極形成工程（工程Ｓ４９）を説明する要部平面図および要部断面図である。
(Modification 4)
A semiconductor device according to Modification 4 will be described with reference to FIGS. Similar to the first to third modifications, only the points different from the contents described in the above embodiment will be described. FIG. 22 is a process diagram showing an example of the flow of the manufacturing process in the method of manufacturing a semiconductor device according to the fourth modification. (A) and (b) of FIG. 23 to FIG. 26 are an essential part plan view and an essential part sectional view, respectively, showing an enlarged part of the semiconductor device during the manufacturing process of the semiconductor device according to Modification 4. . FIGS. 23A and 23B are a main part plan view and a main part sectional view for explaining the columnar electrode formation step (step S46), respectively. FIGS. 24A and 24B are a main part plan view and a main part sectional view for explaining the resin sealing step (step S47), respectively. FIGS. 25A and 25B are a main part plan view and a main part sectional view for explaining the grinding step (step S48), respectively. FIGS. 26A and 26B are a main part plan view and a main part sectional view for explaining the bump electrode forming step (step S49), respectively.
変形例４による半導体装置の製造方法では、前述の実施の形態で説明した半導体ウエハ準備工程（図３に示す工程Ｓ１）から再配置配線形成工程（図３に示す工程Ｓ５）までの各工程と同じ工程を実施した後、さらに、以下の工程を実施する。 In the method of manufacturing a semiconductor device according to the modified example 4, each process from the semiconductor wafer preparation step (step S1 shown in FIG. 3) to the rearrangement wiring formation step (step S5 shown in FIG. 3) described in the above-described embodiment, After performing the same process, the following processes are further performed.
６．柱状電極形成（工程Ｓ４６）
まず、図２３（ａ）および（ｂ）に示すように、再配置配線ＲＷのうちの第２絶縁部材ＯＬ上に位置する部分に、柱状電極（導電性部材）ＣＥを形成する。この柱状電極ＣＥは、例えば以下の製造方法によって形成される。まず、再配置配線ＲＷおよび第２絶縁部材ＯＬを絶縁部材で覆った後、柱状電極ＣＥを形成したい箇所の絶縁部材に開口部を形成する。次に、電解メッキ法またはスパッタリング法などを用いて、絶縁部材に形成した開口部の内部に柱状電極ＣＥを形成する。その後、マスクとして使用した絶縁部材を除去することで、図２３（ａ）および（ｂ）に示すような柱状電極ＣＥが形成される。
6). Columnar electrode formation (step S46)
First, as shown in FIGS. 23A and 23B, a columnar electrode (conductive member) CE is formed on a portion of the rearrangement wiring RW located on the second insulating member OL. The columnar electrode CE is formed by, for example, the following manufacturing method. First, after covering the rearrangement wiring RW and the second insulating member OL with an insulating member, an opening is formed in the insulating member where the columnar electrode CE is to be formed. Next, the columnar electrode CE is formed inside the opening formed in the insulating member by using an electrolytic plating method or a sputtering method. Thereafter, by removing the insulating member used as a mask, the columnar electrode CE as shown in FIGS. 23A and 23B is formed.
７．樹脂封止（工程Ｓ４７）
次に、図２４（ａ）および（ｂ）に示すように、柱状電極ＣＥ、再配置配線ＲＷおよび第２絶縁部材ＯＬの表面を第３絶縁部材ＳＲで覆う。変形例４で使用する第３絶縁部材ＳＲの具体的な材料は樹脂であり、具体的には、例えばフィラー（例えばシリカ）を含有する熱硬化性のエポキシ樹脂である。
7). Resin sealing (Step S47)
Next, as shown in FIGS. 24A and 24B, the surface of the columnar electrode CE, the rearrangement wiring RW, and the second insulating member OL is covered with the third insulating member SR. A specific material of the third insulating member SR used in the modification 4 is a resin, specifically, a thermosetting epoxy resin containing a filler (for example, silica), for example.
８．研削（工程Ｓ４８）
次に、図２５（ａ）および（ｂ）に示すように、柱状電極ＣＥの一部（表面）が露出するまで、第３絶縁部材ＳＲを研削して、第３絶縁部材ＳＲからなる封止体を形成する。
8). Grinding (process S48)
Next, as shown in FIGS. 25A and 25B, the third insulating member SR is ground until a part (surface) of the columnar electrode CE is exposed, and the third insulating member SR is sealed. Form the body.
９．バンプ電極形成（工程Ｓ４９）
次に、図２６（ａ）および（ｂ）に示すように、前述の研削工程により露出した柱状電極ＣＥの一部（表面）に、バンプ電極ＳＢを接続する。このとき、バンプ電極ＳＢと柱状電極ＣＥとの接続性を考慮した場合は、前述の実施の形態で説明したように、電極層（電極）ＵＭを介在させておくことが好ましい。
9. Bump electrode formation (step S49)
Next, as shown in FIGS. 26A and 26B, the bump electrode SB is connected to a part (surface) of the columnar electrode CE exposed by the above-described grinding process. At this time, when considering the connectivity between the bump electrode SB and the columnar electrode CE, it is preferable to interpose an electrode layer (electrode) UM as described in the above-described embodiment.
（変形例５）
変形例５による半導体装置について図２７および図２８を用いて説明する。なお、変形例１乃至４と同様、前述の実施の形態で説明した内容と異なる点についてのみ、説明する。図２７は、変形例５による半導体装置の製造方法において、その製造工程の流れの一例を示す工程図である。図２８（ａ）および（ｂ）はそれぞれ、変形例５による半導体装置の製造工程中の半導体装置の一部を拡大して示す要部平面図および要部断面図である。図２８（ａ）は、半導体ウエハの主面側から見た、再配置配線を覆う絶縁部材（第３絶縁部材）を透かした透過平面図である。また、図２８（ｂ）は、図２８（ａ）に示すＡ−Ａ線に沿った断面図である。
(Modification 5)
A semiconductor device according to Modification 5 will be described with reference to FIGS. Similar to the first to fourth modifications, only the points different from the contents described in the above embodiment will be described. FIG. 27 is a process diagram showing an example of the flow of the manufacturing process in the method for manufacturing a semiconductor device according to Modification 5. 28A and 28B are an essential part plan view and an essential part cross-sectional view showing, in an enlarged manner, a part of the semiconductor device in the manufacturing process of the semiconductor device according to Modification 5. FIG. 28A is a transparent plan view through the insulating member (third insulating member) covering the rearrangement wiring, as viewed from the main surface side of the semiconductor wafer. FIG. 28B is a cross-sectional view taken along line AA shown in FIG.
変形例５による半導体装置では、再配置配線を形成せずに、電極パッドの直上にバンプ電極が形成される。変形例５による半導体装置の製造方法では、前述の実施の形態で説明した半導体ウエハ準備工程（図３に示す工程Ｓ１）からカバー膜形成工程（図３に示す工程Ｓ４）までの各工程と同じ工程を実施した後、さらに、以下の工程を実施する。 In the semiconductor device according to Modification 5, the bump electrode is formed immediately above the electrode pad without forming the rearrangement wiring. In the semiconductor device manufacturing method according to the modified example 5, the same steps as those from the semiconductor wafer preparation step (step S1 shown in FIG. 3) to the cover film formation step (step S4 shown in FIG. 3) described in the above embodiment are performed. After carrying out the steps, the following steps are further carried out.
５．第３絶縁部材形成（工程５５）
図２８（ａ）および（ｂ）に示すように、半導体ウエハＳＷの主面上に第３絶縁部材ＳＲを形成する。
5. Third insulating member formation (process 55)
As shown in FIGS. 28A and 28B, the third insulating member SR is formed on the main surface of the semiconductor wafer SW.
次に、リソグラフィ技術により形成されたレジストパターンをマスク（図示は省略）として、第３絶縁部材ＳＲをエッチングして、カバー膜ＣＦの上面を露出させる開口部ＯＰ６を形成する。 Next, using the resist pattern formed by lithography as a mask (not shown), the third insulating member SR is etched to form an opening OP6 that exposes the upper surface of the cover film CF.
６．柱状電極形成（工程Ｓ５６）
次に、第３絶縁部材ＳＲに形成された開口部ＯＰ６の内部に、カバー膜ＣＦの上面と接続する柱状電極（導電性部材）ＣＥを形成する。
6). Columnar electrode formation (step S56)
Next, a columnar electrode (conductive member) CE connected to the upper surface of the cover film CF is formed inside the opening OP6 formed in the third insulating member SR.
７．バンプ電極形成（工程Ｓ５７）
次に、柱状電極ＣＥと接続する、はんだから構成されるバンプ電極ＢＥを形成する。
7). Bump electrode formation (step S57)
Next, a bump electrode BE made of solder and connected to the columnar electrode CE is formed.
なお、第３絶縁部材ＳＲに開口部ＯＰ６を形成した後、電極パッドＥＰ上に直接、バンプ電極ＢＥを形成することも可能である。しかし、変形例５では、電極パッドＥＰとバンプ電極ＢＥとの間に、カバー膜ＣＦおよび柱状電極ＣＥが形成されているので、バンプ電極ＢＥを電極パッドＥＰ上に直接形成する場合に比べて、接続強度を向上することができる。 It is also possible to form the bump electrode BE directly on the electrode pad EP after forming the opening OP6 in the third insulating member SR. However, in Modification 5, since the cover film CF and the columnar electrode CE are formed between the electrode pad EP and the bump electrode BE, compared to the case where the bump electrode BE is directly formed on the electrode pad EP, Connection strength can be improved.
このように、電極パッドＥＰの直上にバンプ電極ＢＥを形成した場合であっても、直径が小さく、かつ、第３絶縁部材ＳＲの上面から高く突出し、かつ、接続強度の高いバンプ電極ＢＥを形成することができるので、狭ピッチ化に対応した信頼性の高い半導体装置を実現することができる。 As described above, even when the bump electrode BE is formed immediately above the electrode pad EP, the bump electrode BE having a small diameter, a high protrusion from the upper surface of the third insulating member SR, and a high connection strength is formed. Therefore, a highly reliable semiconductor device corresponding to a narrow pitch can be realized.
（変形例６）
変形例６による半導体装置について図２９を用いて説明する。なお、変形例１乃至５と同様、前述の実施の形態で説明した内容と異なる点についてのみ、説明する。図２９は、前述の実施の形態で説明したカバー膜形成工程（図３に示す工程Ｓ４）まで実施した半導体ウエハを個片化することで半導体チップを取得し、その半導体チップを配線基板の内部に埋め込んで形成された半導体装置の要部断面図である。
(Modification 6)
A semiconductor device according to Modification 6 will be described with reference to FIG. Similar to the first to fifth modifications, only differences from the contents described in the above-described embodiment will be described. In FIG. 29, a semiconductor chip is obtained by separating the semiconductor wafer that has been processed up to the cover film forming step (step S4 shown in FIG. 3) described in the above-described embodiment, and the semiconductor chip is placed inside the wiring substrate. 1 is a cross-sectional view of a main part of a semiconductor device formed by being embedded in a semiconductor device.
変形例６による半導体装置は、例えば以下の工程により製造される。 The semiconductor device according to Modification 6 is manufactured by, for example, the following process.
まず、前述の実施の形態で説明したカバー膜形成工程（図３に示す工程Ｓ４）まで実施した半導体ウエハを個片化し、半導体チップＳＣＣ１として準備しておく。 First, the semiconductor wafer that has been processed up to the cover film forming step (step S4 shown in FIG. 3) described in the above-described embodiment is singulated and prepared as a semiconductor chip SCC1.
次に、図２９に示すように、取得した半導体チップＳＣＣ１を、基材ＭＳＵの上面に配置した後、絶縁材ＭＩを用いて半導体チップＳＣＣ１を封止する。なお、このときに使用する絶縁材ＭＩは、例えばエポキシ系の樹脂にガラス繊維を含浸させたものであるが、前述の第３絶縁部材と同様の材料、例えばポリイミド膜を用いてもよい。これにより、半導体チップＳＣＣ１を埋め込んだ配線基板ＭＳが形成される。 Next, as shown in FIG. 29, after the obtained semiconductor chip SCC1 is arranged on the upper surface of the base material MSU, the semiconductor chip SCC1 is sealed with an insulating material MI. The insulating material MI used at this time is, for example, an epoxy-based resin impregnated with glass fibers, but a material similar to the above-described third insulating member, for example, a polyimide film may be used. As a result, the wiring substrate MS in which the semiconductor chip SCC1 is embedded is formed.
次に、絶縁材ＭＩにレーザ光を照射することで、その内側にカバー膜ＣＦの一部（表面）が露出する開口部を形成し、この開口部の内部に導電性部材ＭＣを埋め込む。なお、このときに使用する導電性部材ＭＣは、配線基板ＭＳの各配線層に形成された配線（配線パターン）を構成する材料と同じものであり、例えば銅（Ｃｕ）からなる。 Next, the insulating material MI is irradiated with laser light to form an opening in which a part (surface) of the cover film CF is exposed, and the conductive member MC is embedded in the opening. The conductive member MC used at this time is the same as the material constituting the wiring (wiring pattern) formed in each wiring layer of the wiring board MS, and is made of, for example, copper (Cu).
カバー膜ＣＦは、前述の実施の形態で説明したように、例えばニッケル（Ｎｉ）からなる。そのため、図２９に示すように、カバー膜ＣＦを、アルミニウム（Ａｌ）からなる電極パッドＥＰ上に形成しておくことで、電極パッドＥＰに、直接、レーザ光を照射する場合に比べて、電極パッドＥＰへのダメージを低減することができる。 As described in the above embodiment, the cover film CF is made of, for example, nickel (Ni). Therefore, as shown in FIG. 29, the cover film CF is formed on the electrode pad EP made of aluminum (Al), so that the electrode pad EP can be compared with the case where the electrode pad EP is directly irradiated with laser light. Damage to the pad EP can be reduced.
一方、配線基板ＭＳの配線との接続性まで考慮する場合は、前述の変形例５に示したように、カバー膜ＣＦ上に、柱状電極ＣＥを形成しておくことが好ましい。なお、柱状電極ＣＥを電極パッドＥＰの直上に形成しておくことで、レーザ光の照射により絶縁材ＭＩを除去する際、目標の位置（ここでは、柱状電極の表面）までレーザ光が到達したかどうかの判別もしやすくなる。 On the other hand, when considering the connectivity with the wiring of the wiring board MS, it is preferable to form the columnar electrode CE on the cover film CF as shown in the fifth modification. By forming the columnar electrode CE immediately above the electrode pad EP, the laser beam reaches the target position (here, the surface of the columnar electrode) when the insulating material MI is removed by laser beam irradiation. It becomes easy to determine whether or not.
次に、絶縁材ＭＩに形成した開口部の内部を導電性部材ＭＣで塞いだ後、配線ＭＬＵを形成（接続）し、この配線ＭＬＵを保護膜ＭＩＵにより被覆する。そして、後の工程において、配線基板ＭＳ上に搭載する別の半導体チップＳＣＣ２の電極パッドＭＢＰ（電極、ボンディングリード）と、導電性部材（ここでは、導電性ワイヤ）ＭＢＷを介して電気的に接続される部分（配線ＭＬＵの一部）を、保護膜ＭＩＵから露出させておく。また、配線基板ＭＳの下面（実装面）側においても、基板ＭＳＵの上面と反対側の下面に形成された配線ＭＬＤを保護膜ＭＩＤにより被覆する。そして、後の工程において、外部端子であるはんだボールＭＳＢが接続される部分（配線ＭＬＤの一部）を、保護膜ＭＩＤから露出させておく。 Next, after the inside of the opening formed in the insulating material MI is closed with the conductive member MC, a wiring MLU is formed (connected), and the wiring MLU is covered with the protective film MIU. Then, in a later step, the electrode pad MBP (electrode, bonding lead) of another semiconductor chip SCC2 mounted on the wiring substrate MS is electrically connected via a conductive member (here, conductive wire) MBW. The portion to be formed (a part of the wiring MLU) is exposed from the protective film MIU. Also on the lower surface (mounting surface) side of the wiring substrate MS, the wiring MLD formed on the lower surface opposite to the upper surface of the substrate MSU is covered with the protective film MID. In a later step, a portion (a part of the wiring MLD) to which the solder ball MSB as an external terminal is connected is exposed from the protective film MID.
次に、例えば前述の変形例２と同様にして、配線基板ＭＳの上面側では、配線基板ＭＳのチップ搭載領域に半導体チップＳＣＣ２を搭載した後、半導体チップＳＣＣ２の電極パッドＭＢＰと、保護膜ＭＩＵから露出する配線ＭＬＵの一部とを導電性部材ＭＢＷを用いて接続する。さらに、配線基板ＭＳの下面側では、保護膜ＭＩＤから露出する配線ＭＬＤの一部にはんだボールＭＳＢを接続する。これにより、変形例６による半導体装置が略完成する。 Next, for example, similarly to the above-described modification 2, on the upper surface side of the wiring board MS, after mounting the semiconductor chip SCC2 in the chip mounting area of the wiring board MS, the electrode pads MBP of the semiconductor chip SCC2 and the protective film MIU A part of the wiring MLU exposed from the wiring is connected using a conductive member MBW. Further, on the lower surface side of the wiring board MS, the solder balls MSB are connected to a part of the wiring MLD exposed from the protective film MID. Thereby, the semiconductor device according to the modification 6 is substantially completed.
以上のように、半導体チップＳＣＣ１を埋め込んだ配線基板ＭＳを用いて、ＢＧＡ（Ball Grid Array）を製造することで、半導体装置の高機能化を実現することができる。 As described above, by manufacturing a BGA (Ball Grid Array) using the wiring board MS in which the semiconductor chip SCC1 is embedded, it is possible to realize high functionality of the semiconductor device.
なお、配線基板ＭＳ上に搭載される別の半導体チップＳＣＣ２との電気的な接続方法は、導電性ワイヤに限らず、この別の半導体チップＳＣＣ２の主面（電極パッドＭＢＰが形成された面）を配線基板ＭＳに対向させる、いわゆるフリップチップ接続であってもよい。また、例えば図２９に示す別の半導体チップ上に、さらに別の半導体チップが搭載（積層）されていてもよい。 The electrical connection method with another semiconductor chip SCC2 mounted on the wiring board MS is not limited to the conductive wire, and the main surface (surface on which the electrode pad MBP is formed) of the other semiconductor chip SCC2 The so-called flip chip connection may be used in which the wiring board MS is opposed to the wiring board MS. For example, another semiconductor chip may be mounted (laminated) on another semiconductor chip shown in FIG.
（変形例７）
さらに、上記実施の形態で説明した技術思想の要旨を逸脱しない範囲内において、変形例同士を組み合わせて適用することができる。
(Modification 7)
Furthermore, the modified examples can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.
ＢＥ バンプ電極
ＢＰ 電極パッド（電極、ボンディングリード）
ＢＷ 導電性ワイヤ（導電性部材、ボンディングワイヤ）
ＣＥ 柱状電極（導電性部材）
ＣＦ カバー膜（導電性部材）
ＣＭ 接着剤
ＤＲ デバイス領域（チップ形成領域）
ＥＰ 電極パッド（表面電極）
ＩＤ 層間絶縁膜
ＩＯＬ 第１絶縁部材（第１絶縁膜、第１弾性率を有する絶縁膜、第１パッシベーション膜）
ＬＲ スクライブ領域（ダイシング領域）
ＭＣ 導電性部材
ＭＢ 配線基板（基板）
ＭＢＰ 電極パッド（電極、ボンディングリード）
ＭＢＷ 導電性部材
ＭＩ 絶縁材
ＭＩＤ，ＭＩＵ 保護膜
ＭＬＤ，ＭＬＵ 配線
ＭＳ 配線基板
ＭＳＢ はんだボール
ＭＳＵ 基材
ＯＬ 第２絶縁部材（第２絶縁膜、第２弾性率を有する絶縁膜、第２パッシベーション膜）
ＯＰ１，ＯＰ２，ＯＰ３，ＯＰ４，ＯＰ５，ＯＰ６ 開口部
ＰＦ 保護膜
ＰＮ プローブ針
ＲＰ レジストパターン
ＲＷ 再配置配線（配線、再配線）
ＳＢ バンプ電極（はんだボール）
ＳＣ 半導体装置（半導体チップ）
ＳＣＣ１，ＳＣＣ２ 半導体チップ
ＳＬ シード層
ＳＲ 第３絶縁部材（第３絶縁膜、第３パッシベーション膜、有機材料、樹脂）
ＳＵＢ 半導体基板
ＳＷ 半導体ウエハ
ＵＭ 電極層（電極）
ＤＥＰ 互いに隣り合う電極パッドの間隔
ＤＯＰ１ 互いに隣り合う開口部の間隔
ＬＥＰ 電極パッドの幅
ＬＯＰ１，ＬＯＰ２ 開口部の幅
ＬＲＷ 再配置配線の幅
ＷＥＰ 電極パッドの幅
ＷＯＰ１，ＷＯＰ２ 開口部の幅
ＷＲＷ 再配置配線の幅
BE Bump electrode BP Electrode pad (electrode, bonding lead)
BW conductive wire (conductive member, bonding wire)
CE Columnar electrode (conductive member)
CF cover film (conductive member)
CM Adhesive DR Device area (chip formation area)
EP electrode pad (surface electrode)
ID interlayer insulating film IOL first insulating member (first insulating film, insulating film having first elastic modulus, first passivation film)
LR scribe area (dicing area)
MC Conductive member MB Wiring board (Board)
MBP electrode pads (electrodes, bonding leads)
MBW conductive member MI insulating material MID, MIU protective film MLD, MLU wiring MS wiring board MSB solder ball MSU base material OL second insulating member (second insulating film, insulating film having second elastic modulus, second passivation film)
OP1, OP2, OP3, OP4, OP5, OP6 Opening PF Protective film PN Probe needle RP Resist pattern RW Relocation wiring (wiring, rewiring)
SB Bump electrode (solder ball)
SC semiconductor device (semiconductor chip)
SCC1, SCC2 Semiconductor chip SL Seed layer SR Third insulating member (third insulating film, third passivation film, organic material, resin)
SUB Semiconductor substrate SW Semiconductor wafer UM Electrode layer (electrode)
D EP spacing the openings spacing D OP1 adjacent adjacent electrode pad L EP electrode width of the pad L OP1 each other, L OP2 width W of the width L RW rearrangement wiring openings EP electrode width W of the pad OP1, W OP2 opening width W RW rearrangement wiring width
Claims (12)
（ａ）主面、前記主面上に形成された第１電極パッド、前記主面上に形成され、かつ、平面視において前記第１電極パッドの隣に配置された第２電極パッド、および前記第１電極パッドの上面が露出する第１開口部および前記第２電極パッドの上面が露出する第２開口部が形成された第１絶縁部材、を有する半導体ウエハを準備する工程；
（ｂ）前記半導体ウエハの前記第１絶縁部材上に第２絶縁部材を形成した後、前記第１電極パッドの前記上面が露出する第３開口部および前記第２電極パッドの前記上面が露出する第４開口部を前記第２絶縁部材に形成する工程；
（ｃ）前記第１電極パッドの前記上面および前記第２電極パッドの前記上面を、第１カバー膜および第２カバー膜で、それぞれ覆う工程；
（ｄ）前記第１カバー膜の表面および前記第２カバー膜の表面に、第１配線および第２配線を、それぞれ形成する工程；
（ｅ）前記第１カバー膜の前記表面、前記第２カバー膜の前記表面、前記第１配線および前記第２配線を第３絶縁部材で覆った後、前記第１配線の一部が露出する第５開口部および前記第２配線の一部が露出する第６開口部を前記第３絶縁部材に形成する工程、
ここで、
前記第１電極パッドおよび前記第２電極パッドは、平面視において、第１方向に沿って配置されており、
前記第１カバー膜および前記第２カバー膜のそれぞれは、導電性部材からなり、
前記第１方向における前記第１配線の幅は、前記第２絶縁部材に形成された前記第３開口部の幅よりも小さい、または同じであり、
前記第１方向における前記第２配線の幅は、前記第２絶縁部材に形成された前記第４開口部の幅よりも小さい、または同じである。 A semiconductor device manufacturing method including the following steps:
(A) a main surface, a first electrode pad formed on the main surface, a second electrode pad formed on the main surface and disposed next to the first electrode pad in plan view, and Providing a semiconductor wafer having a first insulating member formed with a first opening exposing the upper surface of the first electrode pad and a second opening exposing the upper surface of the second electrode pad;
(B) After forming the second insulating member on the first insulating member of the semiconductor wafer, the third opening exposing the upper surface of the first electrode pad and the upper surface of the second electrode pad are exposed. Forming a fourth opening in the second insulating member;
(C) covering the upper surface of the first electrode pad and the upper surface of the second electrode pad with a first cover film and a second cover film, respectively;
(D) forming a first wiring and a second wiring on the surface of the first cover film and the surface of the second cover film, respectively;
(E) After covering the surface of the first cover film, the surface of the second cover film, the first wiring, and the second wiring with a third insulating member, a part of the first wiring is exposed. Forming a fifth opening and a sixth opening exposing a part of the second wiring in the third insulating member;
here,
The first electrode pad and the second electrode pad are arranged along a first direction in plan view,
Each of the first cover film and the second cover film is made of a conductive member,
A width of the first wiring in the first direction is smaller than or equal to a width of the third opening formed in the second insulating member;
The width of the second wiring in the first direction is smaller than or the same as the width of the fourth opening formed in the second insulating member.
前記第１電極パッドおよび前記第２電極パッドのそれぞれは、前記主面に形成された半導体回路と電気的に接続されており、
前記第２絶縁部材を形成する工程では熱処理を施し、
前記（ｂ）工程の後、かつ、前記（ｃ）工程の前に、さらに以下の工程を含む：
（ｆ）前記第１電極パッドおよび前記第２電極パッドのそれぞれにプローブ針を接触させて、前記半導体回路に備わるメモリ回路にデータを書き込む工程。 In the manufacturing method of the semiconductor device according to claim 1,
Each of the first electrode pad and the second electrode pad is electrically connected to a semiconductor circuit formed on the main surface,
In the step of forming the second insulating member, heat treatment is performed,
After the step (b) and before the step (c), the following steps are further included:
(F) A step of writing data to a memory circuit included in the semiconductor circuit by bringing a probe needle into contact with each of the first electrode pad and the second electrode pad.
前記第２絶縁部材を形成する工程では熱処理を施し、
前記（ｃ）工程の後、かつ、前記（ｄ）工程の前に、さらに以下の工程を含む：
（ｇ）前記第１カバー膜の前記表面および前記第２カバー膜の前記表面のそれぞれにプローブ針を接触させて、前記半導体回路に備わるメモリ回路にデータを書き込む工程。 In the manufacturing method of the semiconductor device according to claim 1,
In the step of forming the second insulating member, heat treatment is performed,
After the step (c) and before the step (d), the following steps are further included:
(G) A step of writing data to a memory circuit included in the semiconductor circuit by bringing a probe needle into contact with each of the surface of the first cover film and the surface of the second cover film.
前記第１絶縁部材に形成された前記第１開口部の開口端が、前記第２絶縁部材に形成された前記第２開口部の開口端の内側に配置されている。 In the manufacturing method of the semiconductor device according to claim 1,
An opening end of the first opening formed in the first insulating member is disposed inside an opening end of the second opening formed in the second insulating member.
前記第１絶縁部材は第１弾性率を有し、前記第２絶縁部材は前記第１弾性率よりも低い第２弾性率を有する。 In the manufacturing method of the semiconductor device according to claim 1,
The first insulating member has a first elastic modulus, and the second insulating member has a second elastic modulus lower than the first elastic modulus.
前記第１絶縁部材は無機絶縁膜であり、前記第２絶縁部材は有機絶縁膜である。 In the manufacturing method of the semiconductor device according to claim 1,
The first insulating member is an inorganic insulating film, and the second insulating member is an organic insulating film.
前記カバー膜は、ニッケル膜を有する積層膜である。 In the manufacturing method of the semiconductor device according to claim 1,
The cover film is a laminated film having a nickel film.
平面視において、前記第１配線は、前記第１カバー膜の前記表面から前記第２絶縁部材の表面に向かって延びており、
平面視において、前記第２配線は、前記第２カバー膜の前記表面から前記第２絶縁部材の表面に向かって延びており、
前記第１配線の前記一部は、前記第１カバー膜上ではなく、前記第２絶縁部材の前記表面上に位置しており、
前記第２配線の前記一部は、前記第２カバー膜上ではなく、前記第２絶縁部材の前記表面上に位置している。 In the manufacturing method of the semiconductor device according to claim 1,
In plan view, the first wiring extends from the surface of the first cover film toward the surface of the second insulating member,
In plan view, the second wiring extends from the surface of the second cover film toward the surface of the second insulating member,
The part of the first wiring is not on the first cover film but on the surface of the second insulating member,
The part of the second wiring is not on the second cover film but on the surface of the second insulating member.
前記（ｄ）工程は、さらに以下の工程を含む：
（ｄ１）前記第１カバー膜の前記表面および前記第２絶縁部材の前記表面に第１シード層を、前記第２カバー膜の前記表面および前記第２絶縁部材の前記表面に第２シード層を、それぞれ形成する工程；
（ｄ２）前記第１シード層上および前記第２シード層上に、前記第１配線および前記第２配線を、それぞれ形成する工程；
（ｄ３）前記第１シード層のうちの前記第１配線と重ならない部分および前記第２シード層のうちの前記第２配線と重ならない部分を、除去する工程。 The method of manufacturing a semiconductor device according to claim 8.
The step (d) further includes the following steps:
(D1) A first seed layer is formed on the surface of the first cover film and the surface of the second insulating member, and a second seed layer is formed on the surface of the second cover film and the surface of the second insulating member. Each forming step;
(D2) forming the first wiring and the second wiring on the first seed layer and the second seed layer, respectively;
(D3) removing a portion of the first seed layer that does not overlap with the first wiring and a portion of the second seed layer that does not overlap with the second wiring.
前記（ｅ）工程の後、さらに以下の工程を含む：
（ｈ）前記第５開口部から露出する前記第１配線の前記一部および前記第６開口部から露出する前記第２配線の前記一部のそれぞれに、バンプ電極を電気的に接続する工程。 In the manufacturing method of the semiconductor device according to claim 1,
After the step (e), the method further includes the following steps:
(H) A step of electrically connecting a bump electrode to each of the part of the first wiring exposed from the fifth opening and the part of the second wiring exposed from the sixth opening.
前記（ｅ）工程の後、さらに以下の工程を含む：
（ｉ）前記半導体ウエハを、区画されたデバイス領域の間のスクライブ領域に沿って切断し、複数の半導体チップを取得する工程；
（ｊ）配線基板のチップ搭載領域に前記半導体チップを固定する工程；
（ｋ）前記第５開口部から露出する前記第１配線の前記一部および前記第６開口部から露出する前記第２配線の前記一部と、前記配線基板の前記チップ搭載領域の周囲に形成された複数の電極とを、導電性部材を介してそれぞれ電気的に接続する工程。 In the manufacturing method of the semiconductor device according to claim 1,
After the step (e), the method further includes the following steps:
(I) cutting the semiconductor wafer along a scribe region between partitioned device regions to obtain a plurality of semiconductor chips;
(J) fixing the semiconductor chip in the chip mounting region of the wiring board;
(K) Forming the part of the first wiring exposed from the fifth opening and the part of the second wiring exposed from the sixth opening, and the periphery of the chip mounting region of the wiring board. A step of electrically connecting the plurality of formed electrodes to each other through a conductive member.
前記（ｅ）工程において、前記第１配線の前記一部および前記第２配線の前記一部は、前記第１カバー膜上および前記第２カバー膜上に、それぞれ位置している。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (e), the part of the first wiring and the part of the second wiring are respectively located on the first cover film and the second cover film.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014227329A JP6329059B2 (en) | 2014-11-07 | 2014-11-07 | Manufacturing method of semiconductor device |
| US14/886,088 US9711377B2 (en) | 2014-11-07 | 2015-10-18 | Method of manufacturing semiconductor device |
| EP15191412.4A EP3018707B1 (en) | 2014-11-07 | 2015-10-26 | Method of manufacturing a semiconductor device |
| KR1020150154476A KR102343105B1 (en) | 2014-11-07 | 2015-11-04 | Method of manufacturing semiconductor device |
| CN201510751271.5A CN105590872B (en) | 2014-11-07 | 2015-11-06 | Method for manufacturing semiconductor device |
| US15/621,226 US10128129B2 (en) | 2014-11-07 | 2017-06-13 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014227329A JP6329059B2 (en) | 2014-11-07 | 2014-11-07 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016092305A true JP2016092305A (en) | 2016-05-23 |
| JP6329059B2 JP6329059B2 (en) | 2018-05-23 |
Family
ID=54364107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014227329A Active JP6329059B2 (en) | 2014-11-07 | 2014-11-07 | Manufacturing method of semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9711377B2 (en) |
| EP (1) | EP3018707B1 (en) |
| JP (1) | JP6329059B2 (en) |
| KR (1) | KR102343105B1 (en) |
| CN (1) | CN105590872B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018150886A1 (en) * | 2017-02-17 | 2018-08-23 | 株式会社村田製作所 | Solid electrolytic capacitor and method for manufacturing same |
| US11456264B2 (en) | 2020-02-27 | 2022-09-27 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6384879B2 (en) * | 2015-01-23 | 2018-09-05 | オリンパス株式会社 | Imaging device and endoscope |
| JP6663340B2 (en) * | 2016-10-28 | 2020-03-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2019133015A1 (en) | 2017-12-30 | 2019-07-04 | Intel Corporation | Zero-misalignment two-via structures |
| US11328996B2 (en) | 2017-12-30 | 2022-05-10 | Intel Corporation | Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating |
| SG11202004703RA (en) | 2017-12-30 | 2020-07-29 | Intel Corp | Zero-misalignment two-via structures using photoimageable dielectric, buildup film, and electrolytic plating |
| JP7353121B2 (en) * | 2019-10-08 | 2023-09-29 | キヤノン株式会社 | Semiconductor devices and equipment |
| DE102020128994A1 (en) * | 2020-05-27 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of manufacturing the same |
| DE112021007216T5 (en) * | 2021-03-08 | 2024-01-11 | Kioxia Corporation | wafer and probe |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005026678A (en) * | 2003-06-13 | 2005-01-27 | Oki Electric Ind Co Ltd | Semiconductor device |
| JP2005109427A (en) * | 2003-09-12 | 2005-04-21 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2014068015A (en) * | 2012-09-25 | 2014-04-17 | Samsung Electronics Co Ltd | Bump structures, electrical connection structures, and methods of forming the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3578964B2 (en) * | 2000-03-21 | 2004-10-20 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP3927783B2 (en) | 2001-10-16 | 2007-06-13 | 新光電気工業株式会社 | Semiconductor parts |
| JP4428337B2 (en) | 2005-12-02 | 2010-03-10 | ソニー株式会社 | Manufacturing method of semiconductor device |
| JP4818005B2 (en) | 2006-07-14 | 2011-11-16 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2009246218A (en) | 2008-03-31 | 2009-10-22 | Renesas Technology Corp | Semiconductor device and method for manufacturing the same |
| GB2464549B (en) | 2008-10-22 | 2013-03-27 | Cambridge Silicon Radio Ltd | Improved wafer level chip scale packaging |
| JP5582811B2 (en) * | 2010-02-15 | 2014-09-03 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP5926988B2 (en) * | 2012-03-08 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2014
- 2014-11-07 JP JP2014227329A patent/JP6329059B2/en active Active
-
2015
- 2015-10-18 US US14/886,088 patent/US9711377B2/en not_active Expired - Fee Related
- 2015-10-26 EP EP15191412.4A patent/EP3018707B1/en not_active Not-in-force
- 2015-11-04 KR KR1020150154476A patent/KR102343105B1/en active IP Right Grant
- 2015-11-06 CN CN201510751271.5A patent/CN105590872B/en not_active Expired - Fee Related
-
2017
- 2017-06-13 US US15/621,226 patent/US10128129B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005026678A (en) * | 2003-06-13 | 2005-01-27 | Oki Electric Ind Co Ltd | Semiconductor device |
| JP2005109427A (en) * | 2003-09-12 | 2005-04-21 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2014068015A (en) * | 2012-09-25 | 2014-04-17 | Samsung Electronics Co Ltd | Bump structures, electrical connection structures, and methods of forming the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018150886A1 (en) * | 2017-02-17 | 2018-08-23 | 株式会社村田製作所 | Solid electrolytic capacitor and method for manufacturing same |
| US11282653B2 (en) | 2017-02-17 | 2022-03-22 | Murata Manufacturing Co., Ltd. | Solid electrolytic capacitor and method for manufacturing the same |
| US11456264B2 (en) | 2020-02-27 | 2022-09-27 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| US20160133484A1 (en) | 2016-05-12 |
| CN105590872A (en) | 2016-05-18 |
| CN105590872B (en) | 2019-12-17 |
| EP3018707B1 (en) | 2018-04-11 |
| US10128129B2 (en) | 2018-11-13 |
| EP3018707A1 (en) | 2016-05-11 |
| JP6329059B2 (en) | 2018-05-23 |
| US20170278722A1 (en) | 2017-09-28 |
| US9711377B2 (en) | 2017-07-18 |
| KR102343105B1 (en) | 2021-12-24 |
| KR20160055071A (en) | 2016-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6329059B2 (en) | Manufacturing method of semiconductor device | |
| KR100298827B1 (en) | Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate | |
| KR100298828B1 (en) | Method For Manufacturing Wafer Level Chip Scale Packages Using Rerouting Metallized Film And Soldering | |
| KR100787894B1 (en) | Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package | |
| JP2009246218A (en) | Semiconductor device and method for manufacturing the same | |
| JP2008258621A (en) | Semiconductor device package structure and formation method thereof | |
| KR20010031602A (en) | Semiconductor device and method for manufacturing the same | |
| US6841884B2 (en) | Semiconductor device | |
| JP3651346B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20130103400A (en) | Semiconductor device | |
| JP4550102B2 (en) | Semiconductor package, manufacturing method thereof, and semiconductor device including semiconductor package | |
| KR20050116704A (en) | Print circuit board improving a solder joint reliability and semiconductor package module using the same | |
| JP2004079716A (en) | Chip size package type package for semiconductor and its manufacturing method | |
| JP3559554B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP6012688B2 (en) | Semiconductor device | |
| JP4498336B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN111613586B (en) | Electronic device and method for manufacturing electronic device | |
| US10304767B2 (en) | Semiconductor device | |
| JP2010093106A (en) | Semiconductor device and method for manufacturing the same | |
| JP6305375B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| JP2012160739A (en) | Semiconductor device | |
| JP3923944B2 (en) | Semiconductor device | |
| KR101169688B1 (en) | Semiconductor device and stacked semiconductor package | |
| TWI393197B (en) | Chip package | |
| JP2004296464A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170522 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20171228 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180109 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180312 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180327 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180419 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6329059 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |