JP2016066636A - Thin film transistor and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor which inhibits deterioration in electrical characteristics.SOLUTION: A thin film transistor 100 comprises: an oxide semiconductor layer 140 composed of an oxide semiconductor containing at least indium; a silicon-rich insulation layer 150 laminated on the oxide semiconductor layer 140; and an insulation layer 160 laminated on the silicon-rich insulation layer 150 on the side opposite to the oxide semiconductor layer 140. The silicon-rich insulation layer 150 has a silicon concentration higher than that of the insulation layer 160, and the oxide semiconductor layer 140 has a silicon-doped layer 142 in which silicon is doped in a surface layer portion which makes contact with the silicon-rich insulation layer 150.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to a thin film transistor and a method for manufacturing the same.

  A thin film transistor (TFT) is used as a switching element or a driving element on a backplane of an active matrix type display device such as a liquid crystal display device using liquid crystal or an organic EL display device using organic EL (Electro Luminescence). It is used. The channel layer of the thin film transistor has a channel region in which carrier movement is controlled by a voltage applied to the gate electrode. As a material for the channel layer, various semiconductor materials such as amorphous silicon have been studied.

  In recent years, development of an oxide semiconductor TFT using a transparent amorphous oxide semiconductor (TAOS) as a channel layer has been promoted. For example, an oxide semiconductor TFT using TAOS made of a metal oxide (InGaZnO) of indium (In), gallium (Ga), and zinc (Zn) as a channel layer has been put into practical use.

However, in InGaZnO, since carrier mobility can be expected only up to 10 cm ² / Vs, in recent years, TAOS materials having higher carrier mobility have been studied.

For example, an oxide semiconductor in which tungsten oxide (WO ₃ ), silicon oxide (SiO ₂ ), or the like is added to indium oxide (In ₂ O ₃ ) (hereinafter referred to as an In—X—O-based oxide semiconductor) is proposed. Has been. A TFT using an In—X—O-based oxide semiconductor has higher mobility than a TFT using InGaZnO. Further, since an In—X—O-based oxide semiconductor does not contain acid-soluble gallium oxide (Ga ₂ O ₃ ) and zinc oxide (ZnO), controllability of processing of a semiconductor layer using a wet etching process. (See Non-Patent Documents 1 and 2).

Shinya Aikawa, Peter Darmawan, Keiichi Yanagisawa, Toshihide Nabatame, Yoshiyuki Abe, and Kazuhito Tsukagoshi, "Thin-film transistors fabricated by low-temperature process based on Ga- and Zn-free amorphous oxide semicondutor" APPLIED PHYSICS LETTERS 102, 102101 (2013 ) Shinya Aikawa, Toshihide Nabatame, and Kazuhito Tsukagoshi, "Effects of dopants in InOx-based amorphous oxide semiconductors for thin-film transistor applications" APPLIED PHYSICS LETTERS 103, 172105 (2013)

  However, since the In—X—O-based oxide semiconductor has a low crystallization temperature, the In—X—O-based oxide semiconductor is subjected to, for example, a high temperature process of 200 ° C. or higher after the In—X—O based oxide semiconductor is formed. The —O-based oxide semiconductor is crystallized. When the In—X—O-based oxide semiconductor is crystallized, carrier conduction is hindered by the generated crystal grain boundary, which causes a problem that mobility is lowered and electrical characteristics of the TFT are deteriorated.

  Therefore, the present disclosure provides a thin film transistor in which deterioration of electrical characteristics is suppressed and a method for manufacturing the same.

  In order to solve the above problems, a thin film transistor according to the present disclosure includes an oxide semiconductor layer formed of an oxide semiconductor containing at least indium, a first silicon insulating layer stacked on the oxide semiconductor layer, and the first A second silicon insulating layer stacked on a side of the silicon insulating layer opposite to the oxide semiconductor layer, wherein the first silicon insulating layer has a higher silicon concentration than the second silicon insulating layer, and the oxide The semiconductor layer has a silicon doped layer in which silicon is doped in a surface layer portion in contact with the first silicon insulating layer.

  A method for manufacturing a thin film transistor according to the present disclosure is a method for manufacturing a thin film transistor including an oxide semiconductor layer including an oxide semiconductor containing at least indium, and the first silicon insulating layer is provided on the oxide semiconductor layer. A first forming step of forming, and a second forming step of forming a second silicon insulating layer on the first silicon insulating layer, wherein the first silicon insulating layer has a silicon concentration higher than that of the second silicon insulating layer. Highly, in at least one of the first formation step and the second formation step, silicon included in the first silicon insulating layer is doped into a surface layer portion of the oxide semiconductor layer, so that the oxide semiconductor layer A silicon doped layer is formed on the surface layer portion.

  According to the present disclosure, a thin film transistor in which deterioration of electrical characteristics is suppressed can be realized.

1 is a partially cutaway perspective view of an organic EL display device according to Embodiment 1. FIG. 2 is a perspective view illustrating an example of a pixel bank of the organic EL display device according to Embodiment 1. FIG. FIG. 3 is an electric circuit diagram illustrating a configuration of a pixel circuit in the organic EL display device according to the first embodiment. 1 is a schematic cross-sectional view of a thin film transistor according to a first embodiment. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the thin film transistor according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the thin film transistor according to the first embodiment. FIG. 4 is a diagram showing film forming conditions for the silicon-rich insulating layer, the first insulating layer, and the second insulating layer according to the first embodiment. 3 is a diagram showing an element concentration distribution in a stacking direction of Sample A and Sample B produced in Embodiment 1. FIG. 7 is a diagram illustrating a measurement result by X-ray diffraction (XRD) of an oxide semiconductor layer of Sample A manufactured in Embodiment 1. FIG. 7 is a diagram illustrating a measurement result by XRD of an oxide semiconductor layer of Sample B manufactured in Embodiment 1. FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a thin film transistor according to Embodiment 2. FIG. It is a figure which shows the film-forming conditions of the amorphous silicon layer and insulating layer which concern on Embodiment 2, and the conditions of an oxidative plasma process. It is a schematic sectional drawing which shows the manufacturing process of the thin-film transistor which concerns on the modification of embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed explanation than necessary may be omitted. For example, detailed descriptions of already well-known matters and overlapping descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

  In addition, the inventors provide the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and these are intended to limit the subject matter described in the claims. is not.

  Each figure is a mimetic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected about the same structural member.

(Embodiment)
[1. Organic EL display device]
First, the configuration of the organic EL display device 10 according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a partially cutaway perspective view of an organic EL display device 10 according to the present embodiment. FIG. 2 is a perspective view showing an example of a pixel bank of the organic EL display device 10 according to the present embodiment.

[1-1. Constitution]
As shown in FIG. 1, an organic EL display device 10 includes a TFT substrate (TFT array substrate) 20 on which a plurality of thin film transistors are arranged, an anode 41 that is a lower electrode, and an EL layer 42 that is a light emitting layer made of an organic material. And it is comprised by the laminated structure with the organic EL element (light emission part) 40 which consists of the cathode 43 which is a transparent upper electrode.

  A plurality of pixels 30 are arranged in a matrix on the TFT substrate 20, and each pixel 30 is provided with a pixel circuit 31.

  The organic EL element 40 is formed corresponding to each of the plurality of pixels 30, and the light emission of each organic EL element 40 is controlled by the pixel circuit 31 provided in each pixel 30. The organic EL element 40 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of thin film transistors.

  The organic EL element 40 has a configuration in which an EL layer 42 is disposed between an anode 41 and a cathode 43. A hole transport layer is further laminated between the anode 41 and the EL layer 42, and an electron transport layer is further laminated between the EL layer 42 and the cathode 43. Note that another organic functional layer may be provided between the anode 41 and the cathode 43.

  Each pixel 30 is driven and controlled by a respective pixel circuit 31. The TFT substrate 20 includes a plurality of gate wirings (scanning lines) 50 arranged along the row direction of the pixels 30 and a plurality of gate wirings 50 arranged along the column direction of the pixels 30 so as to intersect the gate wiring 50. Source wiring (signal wiring) 60 and a plurality of power supply wirings (not shown) arranged in parallel with the source wiring 60 are formed. Each pixel 30 is partitioned by, for example, an orthogonal gate line 50 and a source line 60.

  The gate wiring 50 is connected to the gate electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each row. The source wiring 60 is connected to the source electrode of the thin film transistor operating as a switching element included in each pixel circuit 31 for each column. The power supply wiring is connected to the drain electrode of the thin film transistor operating as a drive element included in each pixel circuit 31 for each column.

  As shown in FIG. 2, each pixel 30 of the organic EL display device 10 is composed of sub-pixels 30R, 30G, and 30B of three colors (red, green, and blue), and these sub-pixels 30R, 30G, and 30B. Are formed in a matrix on the display surface. The sub-pixels 30R, 30G, and 30B are separated from each other by the bank 21.

  The banks 21 are formed in a lattice shape so that the ridges extending in parallel to the gate wiring 50 and the ridges extending in parallel to the source wiring 60 intersect each other. Each of the portions surrounded by the protrusions (that is, the opening of the bank 21) and the sub-pixels 30R, 30G, and 30B have a one-to-one correspondence. In the present embodiment, the bank 21 is a pixel bank, but may be a line bank.

  The anode 41 is formed for each of the sub-pixels 30R, 30G, and 30B on the interlayer insulating film (flattening layer) on the TFT substrate 20 and in the opening of the bank 21. Similarly, the EL layer 42 is formed for each of the sub-pixels 30R, 30G, and 30B on the anode 41 and in the opening of the bank 21. The transparent cathode 43 is continuously formed on the plurality of banks 21 so as to cover all the EL layers 42 (all the sub-pixels 30R, 30G, and 30B).

  Furthermore, the pixel circuit 31 is provided for each of the sub-pixels 30R, 30G, and 30B, and each of the sub-pixels 30R, 30G, and 30B and the corresponding pixel circuit 31 are electrically connected by a contact hole and a relay electrode. Has been. The sub-pixels 30R, 30G, and 30B have the same configuration except that the emission color of the EL layer 42 is different.

[1-2. Pixel circuit]
Here, the circuit configuration of the pixel circuit 31 in the pixel 30 will be described with reference to FIG. FIG. 3 is an electric circuit diagram showing the configuration of the pixel circuit 31 in the organic EL display device 10 according to the present embodiment.

  As shown in FIG. 3, the pixel circuit 31 includes a thin film transistor 32 that operates as a driving element, a thin film transistor 33 that operates as a switching element, and a capacitor 34 that stores data to be displayed on the corresponding pixel 30. . In the present embodiment, the thin film transistor 32 is a drive transistor for driving the organic EL element 40, and the thin film transistor 33 is a switching transistor for selecting the pixel 30.

  The thin film transistor 32 includes a drain electrode 33d of the thin film transistor 33 and a gate electrode 32g connected to one end of the capacitor 34, a drain electrode 32d connected to the power supply wiring 70, the other end of the capacitor 34, and an anode 41 of the organic EL element 40. And a semiconductor film (not shown). The thin film transistor 32 supplies a current corresponding to the data voltage held by the capacitor 34 from the power supply wiring 70 to the anode 41 of the organic EL element 40 through the source electrode 32 s. Thereby, in the organic EL element 40, a drive current flows from the anode 41 to the cathode 43, and the EL layer 42 emits light.

  The thin film transistor 33 includes a gate electrode 33g connected to the gate wiring 50, a source electrode 33s connected to the source wiring 60, a drain electrode 33d connected to one end of the capacitor 34 and the gate electrode 32g of the thin film transistor 32, and a semiconductor film. (Not shown). In the thin film transistor 33, when a predetermined voltage is applied to the connected gate wiring 50 and source wiring 60, the voltage applied to the source wiring 60 is stored in the capacitor 34 as a data voltage.

  Note that the organic EL display device 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 30 located at the intersection of the gate line 50 and the source line 60. Thereby, the corresponding organic EL element 40 selectively emits light by the thin film transistors 32 and 33 of each pixel 30 (each sub-pixel 30R, 30G, and 30B), and a desired image is displayed.

[2. TFT]
Hereinafter, the thin film transistor formed on the TFT substrate 20 according to the present embodiment will be described with reference to FIG. Note that the thin film transistor according to this embodiment is a bottom-gate and channel protective thin film transistor.

  FIG. 4 is a schematic cross-sectional view of the thin film transistor 100 according to the present embodiment.

  As shown in FIG. 4, the thin film transistor 100 according to this embodiment includes a substrate 110, a gate electrode 120, a gate insulating layer 130, an oxide semiconductor layer 140, a silicon rich insulating layer 150, an insulating layer 160, and the like. , A source electrode 170s and a drain electrode 170d.

  The thin film transistor 100 is, for example, the thin film transistor 32 shown in FIG. That is, the thin film transistor 32 can be used as a drive transistor. Specifically, when the thin film transistor 100 is the thin film transistor 32 (drive transistor), the gate electrode 120 corresponds to the gate electrode 32g, the source electrode 170s corresponds to the source electrode 32s, and the drain electrode 170d corresponds to the drain electrode 32d.

  The thin film transistor 100 may be, for example, the thin film transistor 33 shown in FIG. That is, the thin film transistor 100 may be used as a switching transistor.

[2-1. substrate]
The substrate 110 is a substrate made of a material having electrical insulation. For example, the substrate 110 may be a glass material such as alkali-free glass, quartz glass, or high heat resistance glass, a resin material such as polyethylene, polypropylene, or polyimide, a semiconductor material such as silicon (Si) or gallium arsenide (GaAs), or an insulating material. A substrate made of a metal material such as stainless steel coated with a layer.

  The substrate 110 may be a flexible substrate such as a resin substrate. In this case, the thin film transistor 100 can be used for a flexible display or the like.

[2-2. Gate electrode]
The gate electrode 120 is provided at a position facing the oxide semiconductor layer 140 with the gate insulating layer 130 interposed between the gate electrode 120 and the oxide semiconductor layer 140. In the present embodiment, the gate electrode 120 is formed on the substrate 110 in a predetermined shape. The film thickness of the gate electrode 120 is, for example, 20 nm to 300 nm. Note that the gate electrode 120 may be formed above the substrate 110 via, for example, a buffer layer (undercoat layer).

  In addition, when it describes as "A-B" about the range of a numerical value, it shows that it is A or more and B or less. The same applies to the following description.

  The gate electrode 120 is an electrode made of a conductive material. For example, as a material of the gate electrode 120, molybdenum, aluminum, copper, tungsten, titanium, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium and other metals, metal alloys, indium oxide Conductive metal oxides such as tin (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO), and conductive polymers such as polythiophene and polyacetylene can be used. The gate electrode 120 may have a multilayer structure in which these materials are stacked.

[2-3. Gate insulation layer]
The gate insulating layer 130 is an insulating layer provided on the opposite side of the oxide semiconductor layer 140 from the silicon-rich insulating layer 150. In this embodiment, the gate insulating layer 130 is formed between the gate electrode 120 and the oxide semiconductor layer 140. Specifically, the gate insulating layer 130 is formed on the gate electrode 120 and the substrate 110 so as to cover the gate electrode 120. The film thickness of the gate insulating layer 130 is, for example, 50 nm to 500 nm.

  The gate insulating layer 130 is made of an electrically insulating material. For example, the gate insulating layer 130 is a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a hafnium oxide film, or a stacked film thereof.

[2-4. Oxide semiconductor layer]
The oxide semiconductor layer 140 is used as a channel layer of the thin film transistor 100. The oxide semiconductor layer 140 is formed in a predetermined shape above the substrate 110 so as to face the gate electrode 120. Specifically, the oxide semiconductor layer 140 is formed in an island shape on the gate insulating layer 130 at a position facing the gate electrode 120. The film thickness of the oxide semiconductor layer 140 is, for example, 30 nm to 150 nm.

  The oxide semiconductor layer 140 is formed using an oxide semiconductor containing at least indium (In). In this embodiment, the oxide semiconductor layer 140 is formed using an In—X—O-based oxide semiconductor. X means one or more kinds of metal atoms, specifically, tungsten (W) or titanium (Ti). The oxide semiconductor is a transparent amorphous oxide semiconductor (TAOS).

For example, an In—X—O oxide semiconductor has a mobility of 30 cm ² / Vs or higher, which is higher than InGaZnO (about 10 cm ² / Vs at most). In other words, in this embodiment, InGaZnO is not included in the In—X—O-based oxide semiconductor. More specifically, in the In—X—O-based oxide semiconductor, the atomic ratio of indium (In), gallium (Ga), and zinc (Zn) is In: Ga: Zn = 1: 1: 1. This oxide semiconductor is not included.

  As illustrated in FIG. 4, the oxide semiconductor layer 140 includes an InXO layer 141 and a silicon doped layer 142.

  The InXO layer 141 is a main layer of the oxide semiconductor layer 140 and is composed of an In—X—O-based oxide semiconductor. Specifically, the InXO layer 141 is a bulk layer of the oxide semiconductor layer 140 and includes a channel region in which carrier movement is controlled by a voltage applied to the gate electrode 120. In this embodiment, the InXO layer 141 is an InWO layer formed of an oxide semiconductor containing indium and tungsten.

  The silicon doped layer 142 is a surface layer portion of the oxide semiconductor layer 140 and is a layer in which silicon is doped in a portion in contact with the silicon rich insulating layer 150. Specifically, the silicon doped layer 142 is formed by doping silicon into the oxide semiconductor that forms the oxide semiconductor layer 140. In the present embodiment, the silicon doped layer 142 is an InWSiO layer containing indium, tungsten, and silicon.

In the present embodiment, a silicon concentration peak exists at the interface between the silicon doped layer 142 and the silicon rich insulating layer 150 in the silicon concentration distribution in the stacking direction. At this time, the peak silicon concentration is 1.0 × 10 ²² atoms / cm ^{2 to} 3.0 × 10 ²² atoms / cm ² .

  Note that details of film properties of the oxide semiconductor layer 140 will be described later.

[2-5. Silicon rich insulating layer]
The silicon rich insulating layer 150 is an example of a first silicon insulating layer stacked on the oxide semiconductor layer 140. The silicon rich insulating layer 150 is an insulating layer having a higher silicon concentration than the insulating layer 160 provided between the insulating layer 160 and the oxide semiconductor layer 140. The silicon rich insulating layer 150 is formed over the gate insulating layer 130 so as to cover the oxide semiconductor layer 140.

  The silicon rich insulating layer 150 is an insulating layer containing silicon, and is a silicon oxide film (SiO) in the present embodiment. The silicon rich insulating layer 150 may be, for example, a silicon nitride film (SiN) or a silicon oxynitride film (SiON). The film thickness of the silicon rich insulating layer 150 is, for example, 1 nm to 15 nm.

  The silicon concentration of the silicon rich insulating layer 150 will be described later.

[2-6. Insulation layer]
The insulating layer 160 is an insulating layer containing silicon, and is an example of a second silicon insulating layer stacked on the opposite side of the silicon rich insulating layer 150 from the oxide semiconductor layer 140. The insulating layer 160 is formed on the silicon rich insulating layer 150. The film thickness of the insulating layer 160 is, for example, 50 nm to 500 nm.

  In this embodiment, the insulating layer 160 functions as a protective film (channel protective layer) that protects the channel region of the oxide semiconductor layer 140. Specifically, the insulating layer 160 is an etching stopper that prevents the oxide semiconductor layer 140 from being etched when the drain electrode 170d and the source electrode 170s formed over the oxide semiconductor layer 140 are patterned by etching. Acts as a layer. Accordingly, process damage on the back channel side of the oxide semiconductor layer 140 can be reduced in the bottom-gate TFT. In the present embodiment, the insulating layer 160 is an interlayer insulating film formed over the entire surface of the substrate 110.

  The insulating layer 160 includes a plurality of layers. Specifically, as illustrated in FIG. 4, the insulating layer 160 has a two-layer structure, and includes a first insulating layer 161 and a second insulating layer 162 that are sequentially stacked.

[2-6-1. First insulating layer]
The first insulating layer 161 is an insulating film provided over the oxide semiconductor layer 140. In the present embodiment, the first insulating layer 161 is an insulating layer containing silicon, for example, a silicon oxide film. The first insulating layer 161 may be a silicon nitride film or a silicon oxynitride film. The film thickness of the first insulating layer 161 is, for example, 5 nm to 40 nm.

[2-6-2. Second insulating layer]
The second insulating layer 162 is an insulating film provided on the first insulating layer 161. For example, the second insulating layer 162 is an insulating layer containing silicon, and is a silicon oxide film in this embodiment. Note that the second insulating layer 162 may be a silicon nitride film or a silicon oxynitride film. The film thickness of the second insulating layer 162 is, for example, such that the film thickness as the insulating layer 160 is 500 nm or less. That is, the thickness of the second insulating layer 162 is a thickness that is 500 nm or less in total with the thickness of the first insulating layer 161.

  In addition, the 1st insulating layer 161 and the 2nd insulating layer 162 may be comprised from the same material, and may be comprised from a different material.

  The first insulating layer 161, the second insulating layer 162, and the silicon rich insulating layer 150 are provided with contact holes for connecting the drain electrode 170d and the source electrode 170s to the oxide semiconductor layer 140, respectively. The materials constituting the drain electrode 170d and the source electrode 170s each reach the oxide semiconductor layer 140 along the wall surface of the contact hole. Alternatively, the contact holes may be filled with materials that constitute the drain electrode 170d and the source electrode 170s, respectively.

[2-7. Drain electrode and source electrode]
The drain electrode 170d and the source electrode 170s are formed in a predetermined shape on the insulating layer 160. For example, the drain electrode 170d and the source electrode 170s are disposed on the second insulating layer 162 so as to be spaced apart from each other in the horizontal direction of the substrate. Specifically, the drain electrode 170d and the source electrode 170s are each formed on the second insulating layer 162 so as to be connected to the oxide semiconductor layer 140 (specifically, the silicon doped layer 142) through a contact hole. It is formed. The film thickness of the drain electrode 170d and the source electrode 170s is, for example, 100 nm to 500 nm.

  The drain electrode 170d and the source electrode 170s are electrodes made of a conductive material. The drain electrode 170d and the source electrode 170s are formed of, for example, Ta (tantalum), Mo (molybdenum), Ti (titanium), W (tungsten), Al (aluminum), or at least one alloy thereof, or copper. Single layer film (Cu film), laminated structure of copper film and tungsten film (Cu / W), laminated structure of copper film and titanium nitride film (Cu / TiN), or alloy film of copper and manganese, copper film and molybdenum It is comprised by the laminated structure (CuMn / Cu / Mo) of a film | membrane. Alternatively, as the material of the drain electrode 170d and the source electrode 170s, for example, the same material as the material of the gate electrode 120 can be used.

[3. Manufacturing method of TFT]
Next, a method for manufacturing the thin film transistor 100 according to this embodiment will be described with reference to FIGS. 5A and 5B. 5A and 5B are schematic cross-sectional views illustrating the manufacturing process of the thin film transistor 100 according to the present embodiment.

[3-1. Formation of gate electrode]
First, as shown in FIG. 5A, a substrate 110 is prepared, and a gate electrode 120 having a predetermined shape is formed above the substrate 110. For example, a metal film is formed on the substrate 110 by sputtering, and the metal film is processed by photolithography and etching, whereby the gate electrode 120 having a predetermined shape is formed. Note that an undercoat layer such as a silicon oxide film may be formed on the surface of the substrate 110 before the gate electrode 120 is formed.

Specifically, first, a glass substrate is prepared as the substrate 110, and a 20 nm Mo film and a 200 nm Cu film are sequentially formed on the substrate 110 by sputtering. Then, the gate electrode 120 is formed by patterning the Mo film and the Cu film by photolithography and wet etching. For wet etching of the Mo film and Cu film, for example, a chemical solution in which hydrogen peroxide water (H ₂ O ₂ ) and an organic acid are mixed can be used.

[3-2. Formation of gate insulating layer]
Next, as illustrated in FIG. 5A (b), a gate insulating layer 130 is formed over the substrate 110. For example, the gate insulating layer 130 is formed by plasma CVD (Plasma-Enhanced Chemical Vapor Deposition: PE-CVD) or sputtering so as to cover the gate electrode 120.

  Specifically, a gate insulating layer 130 is formed by sequentially forming a 220 nm silicon nitride film and a 50 nm silicon oxide film on the substrate 110 by plasma CVD so as to cover the gate electrode 120. The film formation temperature at this time is, for example, 350 ° C. to 400 ° C.

The silicon nitride film can be formed by using, for example, silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) as the introduction gas. The silicon oxide film can be formed by using, for example, silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as introduction gases. Note that the gate insulating layer 130 may be a single layer film of a silicon oxide film or a silicon nitride film.

[3-3. Formation of oxide semiconductor layer]
Next, as illustrated in FIG. 5A, an oxide semiconductor layer 140 having a predetermined shape is formed above the substrate 110 and at a position facing the gate electrode 120. For example, an oxide semiconductor film is formed over the gate insulating layer 130 by sputtering. Then, the oxide semiconductor film is processed by photolithography and etching, whereby the oxide semiconductor layer 140 having a predetermined shape is formed. For sputtering, for example, a DC magnetron sputtering apparatus or an RF magnetron sputtering apparatus can be used.

Specifically, an oxide semiconductor (InWO) containing indium and tungsten is placed as a sputtering target on a cathode in a vacuum chamber. Then, argon (Ar) gas as an inert gas flows into the vacuum chamber, and a gas containing oxygen (O ₂ ) as a reactive gas flows, and a voltage with a predetermined power density is applied to the target material. Accordingly, an InWO film can be formed as the oxide semiconductor layer 140 over the gate insulating layer 130.

At this time, as film formation conditions, for example, using a DC magnetron sputtering apparatus, the total pressure of the gas flowing into the vacuum chamber is 0.2 Pa to 0.5 Pa, and the oxygen partial pressure is 0.01 Pa to 0.05 Pa. You can do it. The substrate temperature is, for example, set at room temperature to 50 ° C., the power density may be, for ^example, to ^{1.0W / cm 2 ~4.0W / cm 2} .

Further, the amount of tungsten oxide (WO ₃ ) contained in the target material (InXO) is, for example, 1 wt% to 5 wt%. At this time, the target material may contain 1 wt% to 5 wt% of titanium oxide (TiO ₃ ). The amount of indium oxide (In ₃ O ₂ ) included in the target material is, for example, 89 wt% to 99 wt%.

Next, the InWO formed over the gate insulating layer 130 is wet-etched, whereby the oxide semiconductor layer 140 is formed. InWO wet etching can be performed using, for example, a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed.

[3-4. Formation of silicon-rich insulating layer]
Next, as illustrated in FIG. 5A, the silicon rich insulating layer 150 is formed over the oxide semiconductor layer 140. For example, a silicon-rich silicon oxide film is formed over the entire surface by plasma CVD so as to cover the oxide semiconductor layer 140. For example, a parallel plate type (capacitive coupling type) plasma CVD apparatus can be used. Specifically, the silicon-rich insulating layer 150 is formed at a first temperature T1 that is lower than the crystallization temperature of the oxide semiconductor included in the oxide semiconductor layer 140.

  The film forming conditions for the silicon rich insulating layer 150 are shown in FIG. FIG. 6 is a diagram showing film forming conditions for the silicon rich insulating layer 150, the first insulating layer 161, and the second insulating layer 162 according to this embodiment.

  In FIG. 6, the temperature Tc is a crystallization temperature of the oxide semiconductor included in the oxide semiconductor layer 140. In this embodiment, since InWO is used as the oxide semiconductor, the temperature Tc is the crystallization temperature of InWO. Specifically, the temperature Tc is about 200 ° C.

The film formation conditions of the silicon rich insulating layer 150 are as shown in the column “Si-rich SiO” in FIG. Specifically, the deposition temperature (first temperature T1) of the silicon rich insulating layer 150 is lower than the crystallization temperature Tc of the oxide semiconductor. The power density of the plasma CVD ^{is 0.55W / cm 2 ~1.0W / cm 2} , pressure 100Pa～400Pa, the inter-electrode distance is 400Mils～700mils. The film thickness of the silicon rich insulating layer 150 is 1.0 nm to 15.0 nm, preferably 5.0 nm to 10.0 nm.

  As the reactive gas, silane gas and nitrous oxide gas are used. At this time, when a dilution gas (for example, Ar gas) is used, the usage rate of the nitrous oxide gas can be reduced and cost reduction can be realized. However, the oxide semiconductor layer 140 is damaged (defects) on the surface and the bulk. Therefore, in order to improve the electrical characteristics of the thin film transistor 100, it is preferable not to use a dilution gas.

The silane flow rate ratio (SiH ₄ / (SiH ₄ + N ₂ O)) is 3.0% to 6.0%, preferably 2.0% to 5.0%. The normalized total flow rate is 3.0 sccm / cm ^{2 to} 8.0 sccm / cm ² . By increasing the silane flow ratio, the silicon concentration can be made higher than that of other silicon oxide films (specifically, the insulating layer 160). The normalized flow rate is obtained by dividing the gas flow rate by the electrode area.

[3-5. Formation of first insulating layer and silicon doped layer]
Next, as shown in FIG. 5B (e), a first insulating layer 161 is formed on the silicon-rich insulating layer 150. For example, a silicon oxide film is formed on the silicon rich insulating layer 150 by plasma CVD. Specifically, the first insulating layer 161 is formed at a second temperature T2 that is equal to or higher than the crystallization temperature of the oxide semiconductor included in the oxide semiconductor layer 140.

  At this time, during the formation of the first insulating layer 161, silicon included in the silicon rich insulating layer 150 is doped into the surface layer portion of the oxide semiconductor layer 140. Thereby, the silicon doped layer 142 is formed in the surface layer portion of the oxide semiconductor layer 140. Here, although the case where silicon is doped in the formation process of the first insulating layer 161 is shown, silicon may be doped in the formation process of the silicon rich insulating layer 150.

The film formation conditions of the first insulating layer 161 are as shown in the column “ES1-SiO” in FIG. Specifically, the deposition temperature (second temperature T2) of the first insulating layer 161 is a temperature equal to or higher than the crystallization temperature Tc. The power density of the plasma CVD ^{is 0.55W / cm 2 ~1.2W / cm 2} , pressure 70Pa～400Pa, the inter-electrode distance is 400Mils～700mils. Incidentally, preferably, the power density of the plasma CVD ^{is 0.9W / cm 2 ~1.2W / cm 2} , pressure is 100Pa～200Pa, the inter-electrode distance is 500Mils～600mils.

The silane flow rate ratio (SiH ₄ / (SiH ₄ + N ₂ O)) is 0.8% to 1.2%. The normalized total flow rate is 7.0 sccm / cm ^{2 to} 10.0 sccm / cm ² . Similar to the deposition of the silicon rich insulating layer 150, argon gas is not used.

  Note that the thickness of the first insulating layer 161 may be a thickness that allows silicon to be doped into the surface layer portion of the oxide semiconductor layer 140. For example, the film thickness of the first insulating layer 161 may be 20 nm or less, and is 10 nm as an example.

  The film thickness of the silicon doped layer 142, that is, the depth at which silicon is doped is, for example, 20 nm or less.

[3-6. Formation of second insulating layer]
Next, as shown in FIG. 5B (f), a second insulating layer 162 is formed on the first insulating layer 161. For example, a silicon oxide film is formed on the first insulating layer 161 by plasma CVD. Specifically, the second insulating layer 162 is formed on the first insulating layer 161 at a third temperature T3 that is equal to or higher than the second temperature T2.

  The film forming conditions of the second insulating layer 162 are as shown in the column “ES2-SiO” in FIG. Specifically, the film formation temperature (third temperature T3) of the second insulating layer 162 is higher than the crystallization temperature Tc, for example, a temperature equal to or higher than the film formation temperature of the first insulating layer 161. For example, the film formation temperature of the second insulating layer 162 is 300 ° C. or lower.

The power density of the plasma CVD ^{is 0.55W / cm 2 ~1.2W / cm 2} , pressure 70Pa～400Pa, the inter-electrode distance is 400Mils～700mils. Incidentally, preferably, the power density of the plasma CVD ^{is 0.9W / cm 2 ~1.2W / cm 2} , pressure is 100Pa～200Pa, the inter-electrode distance is 500Mils～600mils.

The silane flow rate ratio (SiH ₄ / (SiH ₄ + N ₂ O)) is 0.8% to 1.2%. The normalized total flow rate is 7.0 sccm / cm ^{2 to} 10.0 sccm / cm ² . Similar to the deposition of the silicon rich insulating layer 150, argon gas is not used.

  The film thickness of the second insulating layer 162 is larger than the film thickness of the first insulating layer 161. For example, the film thickness of the second insulating layer 162 is controlled so that the total film thickness with the first insulating layer 161 (that is, the film thickness of the insulating layer 160) is, for example, 50 nm to 300 nm.

  The film formation of the silicon rich insulating layer 150, the first insulating layer 161, and the second insulating layer 162 was set to the respective temperatures because the first temperature T1, the second temperature T2, and the third temperature T3 were different from each other. Using a vacuum chamber (specifically, a first vacuum chamber set at the first temperature T1, a second vacuum chamber set at the second temperature T2, and a third vacuum chamber set at the third temperature T3). Each layer must be formed. On the other hand, continuous film formation can also be performed by switching the substrate stage temperature in one same vacuum chamber. Thereby, the manufacturing apparatus of the thin-film transistor 100 can be simplified and cost reduction can be realized.

[3-7. Formation of drain electrode and source electrode]
Next, as illustrated in FIG. 5B (g), the drain electrode 170d and the source electrode 170s are formed on the second insulating layer 162 (insulating layer 160). Specifically, first, a part of the insulating layer 160 and the silicon rich insulating layer 150 is removed by etching to form a contact hole. That is, contact holes for exposing part of the oxide semiconductor layer 140 (specifically, the silicon doped layer 142) are formed in the insulating layer 160 and the silicon rich insulating layer 150.

For example, when the silicon rich insulating layer 150 and the insulating layer 160 are silicon oxide films, reactive ion etching (RIE) can be used as dry etching. At this time, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas. Parameters such as the gas flow rate, pressure, applied power, and frequency are appropriately set according to the substrate size, etching film thickness, and the like.

Then, a metal film is formed on the insulating layer 160 by sputtering so as to fill the formed contact hole. For example, a 20 nm Mo film, a 300 nm Cu film, and a 20 nm copper and manganese alloy film (CuMn film) are sequentially stacked on the insulating layer 160. Thereafter, the stacked metal films are processed by photolithography and etching to form a drain electrode 170d and a source electrode 170s having a predetermined shape. For the wet etching of the Mo film, the Cu film, and the CuMn film, for example, a chemical solution in which hydrogen peroxide solution (H ₂ O ₂ ) and an organic acid are mixed can be used.

  As described above, the thin film transistor 100 illustrated in FIG. 4 can be manufactured. Note that an organic EL element can be formed after a planarization film or the like is formed over the thin film transistor 100.

[4. Element concentration distribution]
Subsequently, an element concentration distribution in the stacking direction of the thin film transistor 100 according to this embodiment will be described with reference to FIGS. FIG. 7 is a diagram showing an element concentration distribution in the stacking direction of the sample manufactured in this embodiment.

[4-1. Sample configuration and manufacturing conditions]
FIG. 7 shows the concentration distribution of each of the two samples (sample A and sample B). Sample A and sample B differ in the method of forming a silicon oxide film covering an oxide semiconductor composed of InWO.

  Specifically, Sample A is a device in which a 180 nm silicon oxide film is formed on an oxide semiconductor layer 140 made of InWO. That is, the sample A does not include the silicon rich insulating layer 150 and the silicon doped layer 142 described above.

  In Sample B, a silicon-rich insulating layer 150 having a thickness of 10 nm is formed on the oxide semiconductor layer 140 made of InWO based on the manufacturing method shown in FIGS. 5A and 5B, and then the first insulating layer 161 and In this device, a total of 170 nm of the second insulating layer 162 is sequentially formed. That is, the sample B includes the silicon rich insulating layer 150 and the silicon doped layer 142.

  Here, detailed manufacturing conditions of the sample A and the sample B will be described. First, the manufacturing conditions of sample A will be described.

  As the substrate 110, a silicon substrate or a glass substrate was used. The diameter of the substrate 110 is 6 inches, for example, and the thickness is 0.7 mm, for example. Specifically, the sample for measuring the element concentration shown in FIG. 7 was prepared using a silicon substrate, and the sample for X-ray diffraction shown in FIGS. 8A and 8B was prepared using a glass substrate.

The oxide semiconductor layer 140 is formed using an oxide semiconductor (InWO) containing indium and tungsten. The film forming conditions for InWO are as follows. As the sputtering apparatus, a DC magnetron sputtering apparatus having a cathode having a diameter of 6 inches was used. The partial pressure of oxygen was set to 0.03 Pa with respect to the total pressure of 0.3 Pa of the gas introduced into the vacuum chamber. The substrate temperature was set to room temperature, for example, and the input power was set to 550 W, for example. The amount of WO ₃ in the target material (InWO) is, for example, 5 wt%. The film thickness of the formed InWO is 60 nm.

In Sample A, a silicon oxide film was formed over the oxide semiconductor layer 140 by plasma CVD. SiH ₄ gas and N ₂ O gas were used as the film forming gas. The silane flow ratio (SiH ₄ / (SiH ₄ + N ₂ O)) at this time is 1%. The input power is 180 W, the pressure is 3 torr (about 400 Pa), and the distance between the electrodes is 550 mils.

  Note that three samples A were produced by varying the deposition temperature of the silicon oxide film. The deposition temperatures of the silicon oxide films of the three samples A are 190 ° C., 220 ° C., and 250 ° C., respectively.

  Next, the manufacturing conditions of sample B will be described.

  The conditions of the substrate 110 and the oxide semiconductor layer 140 are the same as those of the sample A.

In Sample B, a silicon-rich silicon oxide film was formed as a silicon-rich insulating layer 150 on the oxide semiconductor layer 140 by plasma CVD. As a film forming gas, 30 sccm of SiH ₄ gas was introduced and 500 sccm of N ₂ O gas was introduced. The silane flow ratio (SiH ₄ / (SiH ₄ + N ₂ O)) at this time is 5.7%. The input power is 180 W, the pressure is 3 torr (about 400 Pa), and the distance between the electrodes is 550 mils. The film thickness of the silicon-rich silicon oxide film is about 10 nm. The film formation temperature (first temperature T1) is 190 ° C., which is lower than the crystallization temperature Tc of InWO.

Further, a silicon oxide film was formed as an insulating layer 160 on the silicon rich insulating layer 150 by plasma CVD. SiH ₄ gas and N ₂ O gas were used as the film forming gas. The silane flow ratio (SiH ₄ / (SiH ₄ + N ₂ O)) at this time is 1%. The input power is 180 W, the pressure is 3 torr (about 400 Pa), and the distance between the electrodes is 550 mils. The thickness of the silicon oxide film is about 170 nm.

  Note that three samples B were manufactured by varying the deposition temperature of the silicon oxide film (insulating layer 160). The deposition temperatures of the silicon oxide films of the three samples B are 190 ° C., 220 ° C., and 250 ° C., respectively.

  5A and 5B, the insulating layer 160 is divided into two layers of the first insulating layer 161 and the second insulating layer 162, but in Sample B, it is formed as a single insulating film at the same film formation temperature. did.

[4-2. Silicon concentration distribution]
FIG. 7 shows the concentration distribution of elements in the stacking direction of Sample A and Sample B by SIMS (Secondary Ion Mass Spectrometry) analysis. Specifically, FIG. 7A shows the concentration distribution of silicon, and FIG. 7B shows the concentration distribution of indium. Note that Sample A and Sample B shown in FIG. 7 have a silicon oxide film deposition temperature of 250 ° C.

  In FIG. 7, the silicon oxide film has a depth in the range of 0 nm to 180 nm. In Sample B, the depth range of 0 nm to 170 nm corresponds to the insulating layer 160, and the range of 170 nm to 180 nm corresponds to the silicon rich insulating layer 150. Further, the oxide semiconductor layer 140 has a depth in the range of 180 nm to 240 nm, and the silicon substrate has a depth in the range of 240 nm or more.

  As shown in FIG. 7B, it was confirmed that the concentration of indium was stable in the range from about 180 nm to about 240 nm, and that the range was the oxide semiconductor layer 140. That is, as described above, since the InWO film of about 60 nm was formed in both the sample A and the sample B, it was confirmed that the InWO film having a desired film thickness was formed.

  Note that in each of the sample A and the sample B, indium is diffused into a layer in contact with the oxide semiconductor layer 140. For example, in Sample B, the silicon-rich insulating layer 150 and the insulating layer 160 contain a small amount of indium.

  As shown in FIG. 7A, the sample B has a higher silicon concentration than the sample A in the surface layer portion (about 180 nm to about 200 nm) of the oxide semiconductor layer 140 on the silicon oxide film side. That is, in sample B, it can be seen that the surface layer portion is doped with silicon from the silicon-rich insulating layer 150. That is, in Sample B, the silicon doped layer 142 is formed on the surface layer portion of the oxide semiconductor layer 140.

For example, the silicon doped layer 142 is a region where the silicon concentration is higher than 1.0 × 10 ¹⁹ atoms / cm ² . The film thickness of the silicon doped layer 142 is, for example, about 20 nm.

  Further, in Sample B, a peak of silicon concentration appears in the vicinity of the interface between the oxide semiconductor layer 140 (silicon doped layer 142) and the silicon rich insulating layer 150 (position of about 180 nm). On the other hand, in sample A, the peak of the silicon concentration does not appear in the vicinity of the interface between the oxide semiconductor layer 140 and the silicon oxide film (position of about 180 nm).

Specifically, the silicon concentration at the peak in sample B is about 2.0 × 10 ²² atoms / cm ² . The silicon concentration at the peak is larger than the average value (about 7.0 × 10 ²¹ atoms / cm ² ) of the silicon concentration of the silicon oxide film (insulating layer 160). Note that the silicon concentration at the peak is smaller than the average value (about 5.0 × 10 ²¹ atoms / cm ² ) of the silicon concentration of the silicon substrate.

[4-3. X-ray diffraction]
Next, measurement results by X-ray diffraction (XRD) of the oxide semiconductor layers 140 of Sample A and Sample B will be described with reference to FIGS. 8A and 8B. 8A and 8B are diagrams illustrating measurement results of the oxide semiconductor layers of Sample A and Sample B by XRD, respectively.

  As shown in FIG. 8A, in sample A, no peak occurred at 190 ° C., whereas at 220 ° C. and 250 ° C., a peak occurred at a position where 2θ was about 30.6. That is, it can be seen that the oxide semiconductor layer is not crystallized when it is 190 ° C., whereas it is crystallized when it is 220 ° C. or higher. It can also be seen that the peak intensity is larger at 250 ° C. than 220 ° C., and the crystallization is more advanced.

  From the above, it can be seen that in Sample A, the oxide semiconductor is crystallized when the silicon oxide film is formed at least at 220 ° C. It can also be seen that the higher the deposition temperature of the silicon oxide film is, the more crystallization proceeds.

  This is because crystal nuclei are generated at the interface between the oxide semiconductor and the insulating layer when an insulating layer such as a silicon oxide film is formed over the In—X—O-based oxide semiconductor. The crystal nuclei facilitate the crystallization of the oxide semiconductor during or after the insulating layer is formed.

  On the other hand, as shown in FIG. 8B, in sample B, no peak occurs at any of 190 ° C., 220 ° C., and 250 ° C. That is, in Sample B, it can be seen that the oxide semiconductor is not crystallized.

  Since the bond energy between silicon and oxygen is large, the structure of the silicon doped layer 142 is stable, and the generation of crystal nuclei at the interface is suppressed. As shown in FIG. 8B, it can be seen that the generation of crystal nuclei is suppressed even when the subsequent process includes a high-temperature thermal process. Therefore, the insulating layer (second insulating layer 162) can be formed at a high temperature, and the insulating layer 160 having favorable film quality can be formed as the channel protective layer.

[5. Effect etc.]
As described above, the thin film transistor 100 according to this embodiment includes the oxide semiconductor layer 140 formed using an oxide semiconductor containing at least indium, the silicon-rich insulating layer 150 stacked over the oxide semiconductor layer 140, and silicon. The rich insulating layer 150 includes an insulating layer 160 stacked on the opposite side of the oxide semiconductor layer 140. The silicon rich insulating layer 150 has a higher silicon concentration than the insulating layer 160, and the oxide semiconductor layer 140 includes silicon. The surface layer portion in contact with the rich insulating layer 150 has a silicon doped layer 142 doped with silicon.

  Accordingly, since the silicon doped layer 142 doped with silicon is formed on the surface layer portion of the oxide semiconductor layer 140, the structure of the silicon doped layer 142 is stabilized and generation of crystal nuclei is suppressed. Therefore, since the insulating layer 160 can be formed by a high temperature process, the film quality of the insulating layer 160 can be improved.

  The region other than the surface layer portion of the oxide semiconductor layer 140 is formed using an In—X—O-based oxide semiconductor. That is, the channel region of the oxide semiconductor layer 140 can be formed using InWO or the like with higher mobility than InGaZnO.

  Note that since silicon has a large binding energy with oxygen, if the amount of silicon doped increases, oxygen defects that generate carriers are less likely to occur. Therefore, the mobility of the surface layer portion doped with silicon is reduced. Therefore, in the thin film transistor 100 according to this embodiment, an In—X—O-based oxide semiconductor with high mobility is used for a bulk portion (a portion where a channel region is formed) of the oxide semiconductor layer 140, and In order to improve the process stability, the surface layer portion is doped with silicon.

  As described above, the thin film transistor 100 according to this embodiment includes a favorable insulating film and a channel region with high mobility. Therefore, according to this embodiment, it is possible to realize the thin film transistor 100 in which deterioration of electrical characteristics is suppressed.

Further, for example, in the present embodiment, there is a silicon concentration peak at the interface between the silicon doped layer 142 and the silicon rich insulating layer 150 in the silicon concentration distribution in the stacking direction. For example, in the present embodiment, the silicon concentration at the peak is 1.0 × 10 ²² atoms / cm ² or more and 3.0 × 10 ²² atoms / cm ² or less.

  As a result, a silicon concentration peak exists at the interface between the oxide semiconductor layer 140 and the silicon-rich insulating layer 150, so that the structure near the interface of the oxide semiconductor layer 140 is stabilized and the generation of crystal nuclei is suppressed near the interface. Is done. Therefore, since the insulating layer 160 can be formed by a high temperature process, the film quality of the insulating layer 160 can be improved.

  For example, in the present embodiment, the film thickness of the silicon rich insulating layer 150 is 1 nm or more and 15 nm or less.

  As a result, the silicon-rich insulating layer 150 is thin and requires less time for film formation, so that generation of crystal nuclei in the oxide semiconductor layer 140 during the formation of the silicon-rich insulating layer 150 is suppressed. can do.

  For example, in this embodiment, the thin film transistor 100 includes the oxide semiconductor layer 140 between the gate insulating layer 130 provided on the opposite side of the silicon-rich insulating layer 150 and the oxide semiconductor layer 140. And the gate electrode 120 provided at a position facing the oxide semiconductor layer 140 with the gate insulating layer 130 interposed therebetween.

  Accordingly, since the thin film transistor 100 is a bottom-gate TFT, the insulating layer 160 is provided as a channel protective layer. That is, since the thin film transistor 100 includes a good channel protective layer, deterioration of electrical characteristics can be suppressed.

  For example, in this embodiment, the oxide semiconductor further contains tungsten.

  Accordingly, since InWO has higher mobility than InGaZnO, the thin film transistor 100 can be applied to an active matrix display device having a high definition, a large screen, and a high driving speed.

  Further, for example, the method for manufacturing the thin film transistor 100 according to this embodiment is a method for manufacturing the thin film transistor 100 including the oxide semiconductor layer 140 including an oxide semiconductor containing at least indium, and includes the oxide semiconductor layer 140 over the oxide semiconductor layer 140. The silicon-rich insulating layer 150 includes a first forming step of forming the silicon-rich insulating layer 150 and a second forming step of forming the insulating layer 160 on the silicon-rich insulating layer 150. The silicon-rich insulating layer 150 has a silicon concentration higher than that of the insulating layer 160. Highly, in at least one of the first formation step and the second formation step, silicon included in the silicon-rich insulating layer 150 is doped into the surface layer portion of the oxide semiconductor layer 140, so that the surface layer portion of the oxide semiconductor layer 140 is doped. A silicon doped layer 142 is formed.

  Accordingly, by doping silicon in the surface layer portion of the oxide semiconductor layer 140, the structure of the surface layer portion of the oxide semiconductor layer 140 is stabilized, and generation of crystal nuclei is suppressed. Therefore, since the insulating layer 160 can be formed by a high temperature process, the film quality of the insulating layer 160 can be improved.

  The region other than the surface layer portion of the oxide semiconductor layer 140 is formed using an In—X—O-based oxide semiconductor. That is, the channel region of the oxide semiconductor layer 140 can be formed using InWO or the like with higher mobility than InGaZnO.

  As described above, according to this embodiment, the thin film transistor 100 having a good insulating film and a high mobility channel region can be manufactured. Therefore, the thin film transistor 100 in which deterioration of electrical characteristics is suppressed can be manufactured.

  For example, in this embodiment, in the first formation step, the silicon-rich insulating layer 150 is formed at the first temperature T1 lower than the crystallization temperature Tc of the oxide semiconductor, and in the second formation step, the oxide semiconductor The insulating layer 160 is formed at a second temperature T2 that is equal to or higher than the crystallization temperature Tc.

  Accordingly, since the deposition temperature (first temperature T1) of the silicon-rich insulating layer 150 is lower than the crystallization temperature Tc of the oxide semiconductor, crystal nuclei of the oxide semiconductor are generated when the silicon-rich insulating layer 150 is deposited. Can be suppressed. Further, since the insulating layer 160 can be formed at a temperature higher than the crystallization temperature Tc of the oxide semiconductor, the high-quality insulating layer 160 can be formed.

  Further, for example, in the present embodiment, in the second forming step, (i) the first insulating layer 161 is formed on the silicon rich insulating layer 150 at the second temperature T2, and (ii) the first insulating layer 161 is formed. In addition, the insulating layer 160 is formed by forming the second insulating layer 162 at a third temperature T3 that is equal to or higher than the second temperature T2.

  Thus, by forming a two-layer structure of the first insulating layer 161 and the second insulating layer 162, for example, the film formation temperature can be made different between the first insulating layer 161 and the second insulating layer 162. For example, the first insulating layer 161 is formed at a temperature suitable for doping silicon on the surface portion of the oxide semiconductor layer 140, and the second insulating layer 162 is formed as a channel protective layer with a high-quality insulating film. Therefore, the film can be formed at a higher temperature.

  Note that in this embodiment, the silicon doped layer 142 is formed by doping silicon of the silicon-rich insulating layer 150 formed by plasma CVD into the surface layer portion of the oxide semiconductor layer 140. On the other hand, for example, it is conceivable that the InWSiO layer is formed as the silicon doped layer 142 after the InXO layer 141 is formed by sputtering.

  In sputtering, the composition of the film to be formed is substantially the same as the composition of the target material. Therefore, it is difficult to form an InWSiO layer so that a silicon concentration peak exists at the interface between the silicon oxide film and the oxide semiconductor layer 140, that is, has a concentration gradient in the film.

  For this reason, when the laminated structure of the InWSiO layer and the InWO layer is formed by sputtering, the distance from the region having a high silicon concentration to the interface between the InWO and the gate insulating layer 130 is shortened, and the diffusion of silicon reaches the front channel side. There is a possibility of progress. When silicon diffuses into the front channel, since the binding energy between silicon and oxygen is large, the generation of oxygen defects is suppressed. For this reason, the carrier concentration in the channel layer is lowered, and the possibility that the mobility is lowered is increased.

  In addition, when forming a laminated structure of an InWSiO layer and an InWO layer, it is necessary to make capital investment such as adding a sputtering chamber or increasing the types of target materials.

  On the other hand, when the silicon-rich insulating layer 150 is formed by plasma CVD, the above-mentioned problem of sputtering does not occur. Moreover, even if the substrate 110 is increased in size, it can be handled by an existing large plasma CVD apparatus, and no new equipment investment is required, and the thin film transistor 100 can be manufactured at low cost.

(Embodiment 2)
Next, a thin film transistor and a manufacturing method thereof according to Embodiment 2 will be described. In this embodiment mode, the structure of the thin film transistor is the same as that in Embodiment Mode 1, and the manufacturing method is different. For this reason, below, it demonstrates focusing on a different point from Embodiment 1. FIG.

  In Embodiment 1, an example in which the silicon-rich insulating layer 150 is formed over the oxide semiconductor layer 140 has been described; however, in this embodiment, an amorphous silicon layer is formed over the oxide semiconductor layer 140, and then The silicon rich insulating layer 150 is formed by oxidation.

[1. Manufacturing method of TFT]
FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the thin film transistor according to the present embodiment.

  Note that the steps until the oxide semiconductor layer 140 is formed are as illustrated in FIGS.

[1-1. Formation of amorphous silicon layer]
After the oxide semiconductor layer 140 is formed, an amorphous silicon layer 250 is formed over the oxide semiconductor layer 140 as illustrated in FIG. For example, an amorphous silicon film is formed over the entire surface by plasma CVD so as to cover the oxide semiconductor layer 140. For example, a parallel plate type plasma CVD apparatus can be used. Specifically, the amorphous silicon layer 250 is formed at a first temperature T <b> 1 that is lower than the crystallization temperature of the oxide semiconductor included in the oxide semiconductor layer 140.

  The deposition conditions for the amorphous silicon layer 250 are shown in FIG. FIG. 10 is a diagram showing the film formation conditions for the amorphous silicon layer 250 and the insulating layer 260 and the conditions for the oxidizing plasma treatment according to this embodiment.

The deposition conditions for the amorphous silicon layer 250 are as shown in the column “a-Si” in FIG. Specifically, the deposition temperature (first temperature T1) of the amorphous silicon layer 250 is lower than the crystallization temperature Tc of the oxide semiconductor. The power density of the plasma CVD ^{is 0.05W / cm 2 ~0.3W / cm 2} , pressure 70Pa～300Pa, the inter-electrode distance is 300Mils～900mils. The distance between the electrodes is preferably 350 mils to 500 mils. The film thickness of the amorphous silicon layer 250 is 1.0 nm to 10.0 nm, preferably 3.0 nm to 5.0 nm.

Moreover, silane gas and hydrogen gas are used as gas introduced into the chamber. The normalized flow rate of silane gas is, for example, 0.01 sccm / cm ^{2 to} 0.25 sccm / cm ² . Normalized flow rate of hydrogen gas is, for ^{example, 0sccm / cm 2 ~0.55sccm / cm 2} .

  At this time, it is preferable not to use hydrogen gas in order to reduce the amount of hydrogen generated during film formation and improve film thickness controllability by reducing the film formation rate. In addition, when a dilution gas (for example, Ar gas) is used, it is possible to reduce the use ratio of the nitrous oxide gas and reduce the cost. However, the oxide semiconductor layer 140 is damaged (defects) on the surface and the bulk. Therefore, in order to improve the electrical characteristics of the thin film transistor 100, it is preferable not to use a dilution gas.

[1-2. Oxidative plasma treatment]
Next, as illustrated in FIG. 9B, the amorphous silicon layer 250 is oxidized by performing an oxidizing plasma treatment on the amorphous silicon layer 250. That is, the amorphous silicon layer 250 is oxidized by exposing the amorphous silicon layer 250 to the N ₂ O plasma 251. Thereby, the silicon rich insulating layer 150 is formed. Specifically, N ₂ O plasma treatment is performed as the oxidizing plasma treatment. For example, a parallel plate type plasma CVD apparatus can be used for the oxidizing plasma treatment. Specifically, the silicon-rich insulating layer 150 is formed by performing an oxidative plasma treatment on the amorphous silicon layer 250 at a second temperature T2 that is equal to or higher than the crystallization temperature Tc.

  At this time, silicon contained in the amorphous silicon layer 250 is doped into the surface layer portion of the oxide semiconductor layer 140 during the oxidizing plasma treatment. Thereby, the silicon doped layer 142 is formed in the surface layer portion of the oxide semiconductor layer 140.

The conditions for the N ₂ O plasma treatment are as shown in the column “N ₂ O plasma” in FIG. Specifically, the processing temperature (second temperature T2) of the N ₂ O plasma processing is a temperature equal to or higher than the crystallization temperature Tc of the oxide semiconductor. The power density ^{is 0.05W / cm 2 ~0.3W / cm 2} , pressure 100Pa～400Pa, the inter-electrode distance is 400Mils～700mils. The pressure is preferably 100 Pa to 200 Pa, and the interelectrode distance is preferably 350 mils to 500 mils.

Further, nitrous oxide (N ₂ O) gas is used as the gas introduced into the chamber. The normalized flow rate of N ₂ O gas is, for example, 5.0 sccm / cm ^{2 to} 10.0 sccm / cm ² .

The processing time of the N ₂ O plasma processing is, for example, 1 second to 300 seconds, and preferably 30 seconds to 180 seconds. If the processing time is too short, the amorphous silicon layer 250 cannot be oxidized. When the treatment time is too long, plasma damage occurs in the oxide semiconductor layer 140 and promotes the generation of crystal nuclei.

[1-3. Formation of insulating layer]
Next, as shown in FIG. 9C, the insulating layer 260 is formed on the silicon rich insulating layer 150. For example, a silicon oxide film is formed on the silicon rich insulating layer 150 by plasma CVD. Specifically, the insulating layer 260 is formed on the silicon rich insulating layer 150 at a third temperature T3 that is equal to or higher than the crystallization temperature Tc.

The conditions for forming the insulating layer 260 are as shown in the column “SiO ₂ ” in FIG. Specifically, the deposition temperature (third temperature T3) of the insulating layer 260 is higher than the crystallization temperature Tc of the oxide semiconductor, for example, a temperature equal to or higher than the processing temperature of the N ₂ O plasma treatment. The power density of the plasma CVD ^{is 0.55W / cm 2 ~1.2W / cm 2} , pressure 70Pa～400Pa, the inter-electrode distance is 400Mils～700mils. Incidentally, preferably, the power ^density was ^{0.9W / cm 2 ~1.2W / cm 2} , pressure 100Pa～200Pa, the inter-electrode distance is 500Mils～600mils. The thickness of the insulating layer 260 is 50 nm to 300 nm.

The silane flow rate ratio (SiH ₄ / (SiH ₄ + N ₂ O)) is 0.8% to 1.2%. The normalized total flow rate is 7.0 sccm / cm ^{2 to} 10.0 sccm / cm ² . At this time, no dilution gas such as argon gas is used.

  Note that although one insulating layer 260 is formed in this embodiment mode, two insulating layers may be formed as the insulating layer 260 as in Embodiment Mode 1.

  Thereafter, as shown in FIG. 5B (g), a thin film transistor can be manufactured by forming the drain electrode 170d and the source electrode 170s.

[2. Sample configuration and manufacturing conditions]
Here, Sample C was manufactured using the method for manufacturing a thin film transistor according to this embodiment. The sample C includes the silicon rich insulating layer 150 and the silicon doped layer 142 similarly to the sample B according to the first embodiment. At this time, the silicon-rich insulating layer 150 is obtained by oxidizing the amorphous silicon layer 250 by oxidizing plasma treatment.

  First, detailed manufacturing conditions of the sample C will be described.

  The deposition conditions of the substrate 110 and the oxide semiconductor layer 140 are the same as those of the sample A.

In Sample C, an amorphous silicon layer 250 was formed over the oxide semiconductor layer 140 by plasma CVD. As a film forming gas, 30 sccm of SiH ₄ gas was introduced. The input power is 50 W, the pressure is 2 torr (about 267 Pa), and the distance between the electrodes is 350 mils. The film thickness of the amorphous silicon layer 250 is about 10 nm. The film forming temperature is 190 ° C., which is lower than the crystallization temperature Tc of InWO.

Further, the amorphous silicon layer 250 was subjected to N ₂ O plasma treatment to oxidize the amorphous silicon layer 250 to form the silicon rich insulating layer 150. As the introduction gas, 1500 sccm of N ₂ O gas was introduced. The input power is 30 W, the pressure is 3 torr (about 400 Pa), and the distance between the electrodes is 550 mils. The processing time is 180 seconds. The processing temperature (second temperature T2) is 200 ° C., which is the same temperature as the crystallization temperature Tc of InWO.

Further, a silicon oxide film was formed as an insulating layer 260 on the silicon rich insulating layer 150 by plasma CVD. SiH ₄ gas and N ₂ O gas were used as the film forming gas. The silane flow ratio (SiH ₄ / (SiH ₄ + N ₂ O)) at this time is 1%. The input power is 180 W, the pressure is 3 torr (about 400 Pa), and the distance between the electrodes is 550 mils. The thickness of the silicon oxide film is about 170 nm.

  Note that three samples C were produced by varying the film formation temperature of the silicon oxide film (insulating layer 260). The deposition temperatures of the silicon oxide films of the three samples C are 190 ° C., 220 ° C., and 250 ° C., respectively.

  Sample C produced under the above conditions produced a film-quality device as shown in FIGS. 7 and 8B. That is, according to the method for manufacturing a thin film transistor according to this embodiment, as in Embodiment 1, the insulating layer 260 having favorable film quality can be formed as the channel protective layer.

[3. Effect etc.]
As described above, in the method for manufacturing the thin film transistor according to this embodiment, the first formation step includes forming the amorphous silicon layer 250 at the first temperature T1 lower than the crystallization temperature Tc of the oxide semiconductor, Forming a silicon rich insulating layer 150 by performing an oxidizing plasma treatment on the silicon layer 250 at a second temperature T2 that is equal to or higher than the crystallization temperature Tc of the oxide semiconductor.

  Thus, as in Embodiment 1, by doping silicon into the surface layer portion of the oxide semiconductor layer 140, the structure of the surface layer portion of the oxide semiconductor layer 140 is stabilized, and generation of crystal nuclei is suppressed. Therefore, since the insulating layer 260 can be formed by a high temperature process, the film quality of the insulating layer 260 can be improved.

  The region other than the surface layer portion of the oxide semiconductor layer 140 is formed using an In—X—O-based oxide semiconductor. That is, the channel region of the oxide semiconductor layer 140 can be formed using InWO or the like with higher mobility than InGaZnO.

  Thus, according to this embodiment mode, a thin film transistor having a good insulating film and a high mobility channel region can be manufactured. Therefore, a thin film transistor in which deterioration of electrical characteristics is suppressed can be manufactured.

(Modification)
Subsequently, a modification of the method for manufacturing the thin film transistor according to the above-described embodiment will be described with reference to FIGS. FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the thin film transistor according to this modification.

  As shown in FIG. 11A, when the oxide semiconductor layer 140 is formed, minute unevenness 343 (or particles) may be formed on the surface. Since the minute unevenness 343 promotes the generation of crystal nuclei, as shown in FIG. 11B, the oxide semiconductor layer 140 is etched by a predetermined thickness before the silicon-rich insulating layer 150 is formed. By etching, the surface layer of the oxide semiconductor layer 140 is removed, and minute unevenness 343 on the surface is removed.

For example, wet etching of the oxide semiconductor layer 140 can be performed using a chemical solution in which phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water are mixed, for example. At this time, the concentration of the chemical solution is adjusted so that the etching rate is 1 nm / min. The surface layer of the oxide semiconductor layer 140 is removed by immersing the chemical solution in the oxide semiconductor layer 140 for 1 to 3 minutes. The film thickness to be removed is, for example, 1 nm to 3 nm.

  As described above, the method for manufacturing a thin film transistor according to the present modification further includes an etching step of etching the oxide semiconductor layer 140 by a predetermined thickness before forming the silicon-rich insulating layer 150.

  Accordingly, the roughness (roughness) of the surface of the oxide semiconductor layer 140 can be reduced, and generation of crystal nuclei can be suppressed.

(Other embodiments)
As described above, the embodiments have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed. Moreover, it is also possible to combine each component demonstrated in the said embodiment and it can also be set as a new embodiment.

  Thus, other embodiments will be exemplified below.

  For example, in the above embodiment, a bottom gate type and channel protection type thin film transistor has been described. However, the present invention is not limited to this. The thin film transistor may be a bottom gate type and a channel etch type, or may be a top gate type thin film transistor. Note that in the case of a top-gate thin film transistor, the above-described insulating layer 160 and the silicon-rich insulating layer 150 can be used as a gate insulating film.

  For example, in the above embodiment, the organic EL display device 10 is described as a display device using the thin film transistor 100. However, the thin film transistor 100 in the above embodiment uses an active matrix substrate such as a liquid crystal display device. The present invention can also be applied to other display devices.

  In addition, the display device (display panel) such as the organic EL display device 10 described above can be used as a flat panel display, and is applied to all electronic devices having a display panel such as a television set, a personal computer, and a mobile phone. can do. In particular, it is suitable for a large-screen and high-definition display device.

  As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

  Accordingly, among the components described in the attached drawings and detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to exemplify the above technique. May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  Moreover, since the above-mentioned embodiment is for demonstrating the technique in this indication, a various change, substitution, addition, abbreviation, etc. can be performed in a claim or its equivalent range.

  The thin film transistor and the manufacturing method thereof according to the present disclosure can be used for, for example, a display device such as an organic EL display device or other electronic devices, or a manufacturing method thereof.

10 Organic EL display device 20 TFT substrate 21 Bank 30 Pixels 30B, 30G, 30R Subpixel 31 Pixel circuits 32, 33, 100 Thin film transistors 32d, 33d, 170d Drain electrodes 32g, 33g, 120 Gate electrodes 32s, 33s, 170s Source electrode 34 Capacitor 40 Organic EL element 41 Anode 42 EL layer 43 Cathode 50 Gate wiring 60 Source wiring 70 Power supply wiring 110 Substrate 130 Gate insulating layer 140 Oxide semiconductor layer 141 InXO layer 142 Silicon doped layer 150 Silicon rich insulating layers 160 and 260 Insulating layer 161 First insulating layer 162 Second insulating layer 250 Amorphous silicon layer 251 N ₂ O plasma 343 Concavity and convexity

Claims (12)

An oxide semiconductor layer composed of an oxide semiconductor containing at least indium;
A first silicon insulating layer stacked on the oxide semiconductor layer;
A second silicon insulating layer stacked on the opposite side of the first silicon insulating layer from the oxide semiconductor layer;
The first silicon insulating layer has a higher silicon concentration than the second silicon insulating layer,
The oxide semiconductor layer has a silicon doped layer in which silicon is doped in a surface layer portion in contact with the first silicon insulating layer. 2. The thin film transistor according to claim 1, wherein a silicon concentration peak exists at an interface between the silicon doped layer and the first silicon insulating layer in a silicon concentration distribution in a stacking direction. The thin film transistor according to claim 2, wherein a silicon concentration at the peak is 1.0 × 10 ²² atoms / cm ² or more and 3.0 × 10 ²² atoms / cm ² or less. The thin film transistor according to any one of claims 1 to 3, wherein a film thickness of the first silicon insulating layer is not less than 1 nm and not more than 15 nm. The thin film transistor further comprises:
A gate insulating layer provided on the opposite side of the oxide semiconductor layer from the first silicon insulating layer;
The thin film transistor according to claim 1, further comprising: a gate electrode provided at a position facing the oxide semiconductor layer with the gate insulating layer interposed between the oxide semiconductor layer and the oxide semiconductor layer. The thin film transistor according to claim 1, wherein the oxide semiconductor further contains tungsten. A method for producing a thin film transistor comprising an oxide semiconductor layer composed of an oxide semiconductor containing at least indium,
A first forming step of forming a first silicon insulating layer on the oxide semiconductor layer;
Forming a second silicon insulating layer on the first silicon insulating layer;
The first silicon insulating layer has a higher silicon concentration than the second silicon insulating layer,
In at least one of the first forming step and the second forming step, silicon included in the first silicon insulating layer is doped into a surface layer portion of the oxide semiconductor layer, so that a surface layer portion of the oxide semiconductor layer is formed. A method of manufacturing a thin film transistor, wherein a silicon doped layer is formed on the substrate. In the first formation step, the first silicon insulating layer is formed at a first temperature lower than the crystallization temperature of the oxide semiconductor,
The method of manufacturing a thin film transistor according to claim 7, wherein in the second formation step, the second silicon insulating layer is formed at a second temperature that is equal to or higher than a crystallization temperature of the oxide semiconductor. The first forming step includes
Forming an amorphous silicon layer at a first temperature lower than the crystallization temperature of the oxide semiconductor;
The thin film transistor according to claim 7, further comprising: performing an oxidizing plasma treatment on the amorphous silicon layer at a second temperature equal to or higher than a crystallization temperature of the oxide semiconductor to form the first silicon insulating layer. Production method. In the second forming step, (i) a first insulating layer is formed on the first silicon insulating layer at the second temperature, and (ii) a second temperature equal to or higher than the second temperature is formed on the first insulating layer. The method for manufacturing a thin film transistor according to claim 8 or 9, wherein the second silicon insulating layer is formed by forming a second insulating layer at three temperatures. The method for manufacturing the thin film transistor further includes an etching step of etching the oxide semiconductor layer by a predetermined thickness before forming the first silicon insulating layer. Manufacturing method of the thin film transistor. The method for manufacturing a thin film transistor according to claim 7, wherein the oxide semiconductor further includes tungsten.

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