JP2016062212A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily inspect a state of a signal between a memory and a controller with an operation test after assembly.SOLUTION: A semiconductor storage device includes a wiring board, a memory, a bonding wire which electrically connects the wiring board and the memory, a memory controller, and an insulating resin layer. The wiring board includes a junction that is provided on a first surface and to which the bonding wire is joined, a bonding pad having a via land portion, a via penetrating through the wiring board so as to overlap the via land portion, and a connection pad which is provided on a second surface so as to overlap the via, is electrically connected to the bonding pad through the via, and is exposed to a second surface so as to include a part of the via.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor memory device.

  A NAND flash memory with a built-in controller, such as eMMC (embedded MultiMediaCard: eMMC), which is one of semiconductor memory devices, has advantages such as low power consumption and a small area as well as high speed operation.

  In manufacturing a semiconductor memory device, an operation test for inspecting whether the operation is normally performed after assembly is performed. In the operation test of the NAND flash memory, for example, the probe pin is brought into contact with the external connection terminal exposed on the package surface, and the memory cell can be correctly selected by using a memory tester or the like, and the data can be correctly written to the selected memory cell. Furthermore, it checks whether or not the written data can be read out with a prescribed access time.

  However, in the operation test of the controller built-in type NAND flash memory, it is difficult to discriminate between a defective memory portion and a defective memory controller portion. In the NAND flash memory with a built-in controller, since the memory and the memory controller are sealed as one package, the connection portion between the memory and the memory controller is not exposed on the package surface. For this reason, it is not easy to examine the state of signals between the memory and the memory controller by an operation test because, for example, it is necessary to process a mold resin after assembly.

JP 2013-069019 A

  A problem to be solved by the invention of the embodiment is that in a controller-embedded semiconductor memory device including a memory and a controller, it is possible to easily inspect the state of a signal between the memory and the controller by an operation test after assembly. It is to be.

  The semiconductor memory device of the embodiment includes a wiring board having a first surface and a second surface facing each other, a memory mounted on the first surface, and a bonding wire that electrically connects the wiring substrate and the memory. And a memory controller mounted on the first surface and electrically connected to the memory through the wiring board, and an insulating resin layer for sealing the memory, the memory controller, and the bonding wire. The wiring board is provided on the first surface and has a bonding pad having a bonding wire bonded thereto, a bonding pad having a via land part, a via penetrating the wiring board so as to overlap the via land part, and overlapping the via. A connection pad that is provided on the second surface and is electrically connected to the bonding pad through the via and exposed to the second surface so as to include a part of the via.

It is a figure which shows the structural example of a semiconductor memory device. It is an enlarged view of a semiconductor memory device It is a top view which shows the example of a planar layout of a semiconductor memory device. It is a one part enlarged view of a pad part. It is a one part enlarged view of a pad part. It is a figure which shows the example of a layout of the connection pad in a pad part. It is a figure which shows the planar shape of a connection pad. It is a figure which shows the planar shape of a connection pad.

  Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and for example, the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may be different from the actual ones. In the embodiments, substantially the same constituent elements are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a diagram illustrating a structure example of a semiconductor memory device. A semiconductor memory device 10 shown in FIG. 1 includes a wiring board 1, a memory 2, a memory controller 3, a bonding wire 4, an insulating resin layer 5, and a conductive layer 6.

  The wiring substrate 1 has a first surface and a second surface. The first surface of the wiring substrate 1 corresponds to the upper surface of the wiring substrate 1 in FIG. 1, and the second surface corresponds to the lower surface of the wiring substrate 1 in FIG.

  The memory 2 is mounted on the first surface of the wiring board 1. The memory 2 includes, for example, a stack of a plurality of semiconductor chips, and the plurality of semiconductor chips are bonded to each other so that a part thereof is overlapped with an adhesive layer interposed therebetween. The plurality of semiconductor chips are electrically connected by connecting electrode pads provided on each semiconductor chip by wire bonding. As the semiconductor chip, for example, a memory chip having a storage element such as a NAND flash memory can be used. At this time, the semiconductor chip may include a decoder or the like in addition to the memory cell.

  The memory controller 3 is mounted on the first surface of the wiring board 1 and is electrically connected to the memory 2 via the wiring board 1. The memory controller 3 controls operations such as data writing to and data reading from the memory 2. The memory controller 3 is composed of a semiconductor chip. For example, the memory controller 3 is electrically connected to the wiring board 1 by connecting electrode pad pads provided on the semiconductor chip by wire bonding and connection pads such as bonding pads provided on the wiring board 1. Connected.

  The connection method between the memory 2 and the memory controller 3 and the wiring board 1 is not limited to wire bonding, and wireless bonding such as flip chip bonding or tape automated bonding may be used. A three-dimensional mounting structure such as a TSV (Through Silicon Via: TSV) system in which the chip of the memory 2 and the chip of the memory controller 3 are stacked on the wiring substrate 1 may be used.

  The bonding wire 4 electrically connects the wiring board 1 and the memory 2. Thereby, the bonding wire 4 is electrically connected to the connection portion between the memory 2 and the memory controller 3. As the bonding wire 4, for example, gold, silver, copper, aluminum or the like can be used. A plurality of bonding wires may be provided as the bonding wires 4.

The insulating resin layer 5 contains an inorganic filler (for example, SiO ₂ ). For example, a mold such as a transfer molding method, a compression molding method, or an injection molding method using a sealing resin obtained by mixing the inorganic filler with an organic resin or the like. Formed by law.

  The conductive layer 6 is provided on the second surface of the wiring board 1. The conductive layer 6 has a function as an external connection terminal. For example, a signal, a power supply voltage, and the like are supplied to the memory controller 3 via an external connection terminal. At this time, the power supply voltage may be supplied to the memory 2 via the external connection terminal. The conductive layer 6 is formed of, for example, gold, copper, solder, or the like. For example, tin-silver or tin-silver-copper lead-free solder may be used. Further, the conductive layer 6 may be provided by stacking a plurality of metal materials. In FIG. 2, the conductive layer 6 made of conductive balls is formed, but the conductive layer 6 made of bumps may be formed.

  2 is an enlarged view of a part of the semiconductor memory device 10 shown in FIG. As shown in FIG. 2, the wiring board 1 includes an insulating layer 11, a wiring layer 12, a wiring layer 13, a solder resist 14, a solder resist 15, a via 16a, and a via 16b.

  The insulating layer 11 is provided between the first surface and the second surface of the wiring substrate 1. As the insulating layer 11, for example, a semiconductor substrate, a glass substrate, a ceramic substrate, a resin substrate such as glass epoxy, or the like can be used.

  The wiring layer 12 is provided on the first surface of the wiring board 1. The wiring layer 12 has a plurality of conductive layers including bonding pads 121 and wirings 122.

  The bonding pad 121 includes a bonding portion 121a to which the bonding wire 4 is bonded and a via land portion 121b juxtaposed to the bonding portion 121a. Further, a plurality of bonding pads may be provided as the bonding pad 121. Further, FIG. 2 shows an example in which the bonding wire 4 is bonded by wedge bonding, but the present invention is not limited to this, and the bonding wire 4 may be bonded by ball bonding.

  The wiring layer 13 is provided on the second surface of the wiring board 1. The wiring layer 13 has a plurality of conductive layers including a connection pad 131a in which the conductive layer 6 is not provided on the surface and a connection pad 131b in which the conductive layer 6 is provided on the surface. The surface of the connection pad 131a is exposed on the second surface, and the surface of the connection pad 131b is covered with the conductive layer 6.

  The connection pad 131a has a function as a test pad for inspecting a signal state between the memory 2 and the memory controller 3 in an operation test. For example, by bringing a probe pin into contact with the connection pad 131a, an operation test can be performed using a memory tester or the like. The connection pad 131a may be electrically connected to a connection node between the memory 2 and the memory controller 3. The connection pad 131a only needs to include at least a part of the via 16a. For example, only the exposed surface of the via 16a on the second surface may be regarded as the connection pad 131a.

  The connection pad 131 b has a function as a land for forming the conductive layer 6. The diameter of the connection pad 131b may be larger than the diameter of the connection pad 131a. Further, the connection pad 131b may be electrically connected to another connection wiring.

  The wiring layer 12 and the wiring layer 13 include, for example, copper, silver, gold, nickel, or the like. For example, the wiring layer 12 and the wiring layer 13 may be formed by forming a plating film containing the above material by an electrolytic plating method or an electroless plating method. Alternatively, the wiring layer 12 and the wiring layer 13 may be formed using a conductive paste.

  The solder resist 14 is provided on the wiring layer 12 and has an opening. The opening of the solder resist 14 is provided on at least a part of the bonding pad 121, for example. In FIG. 2, the solder resist 14 is formed on the wiring 122, but an opening is formed on another part of the wiring 122.

  The solder resist 15 is provided on the wiring layer 13 and has an opening. The opening of the solder resist 15 is provided, for example, on at least a part of the connection pad 131a and the connection pad 131b.

  As the solder resist 14 and the solder resist 15, for example, an insulating resin material can be used. For example, an ultraviolet curable resin, a thermosetting resin, or the like can be used. Moreover, an opening can be formed in a part of the solder resist 14 and the solder resist 15 by, for example, etching or the like.

  The via 16 a overlaps the via land portion 121 b of the bonding pad 121 and penetrates the wiring board 1. By superimposing the via 16a on the via land portion 121b, an increase in area can be suppressed. At this time, it is preferable that the via 16 a is not overlapped with the bonding portion 121 a of the bonding pad 121. The via 16a may not penetrate the via land portion 121b.

  At least a part of the via 16a is included in a part of the connection pad 131a. The via 16a electrically connects the bonding pad 121 and the connection pad 131a. The via 16a may not penetrate the connection pad 131a. The diameter of the via 16a is preferably 80 μm or less, for example.

  The via 16b penetrates the wiring board 1 to electrically connect the wiring 122 and the connection pad 131b. The via 16b may not penetrate the wiring 122 and the connection pad provided on the second surface. The diameter of the via 16b may be equal to or larger than the diameter of the via 16a.

  The via 16a and the via 16b include, for example, a conductor layer provided along an inner wall of an opening that penetrates the insulating layer 11, and a hole filling material filled inside the conductor layer. The opening is formed using a laser, for example. The conductor layer includes copper, silver, gold, nickel, or the like. For example, the conductor layer may be formed by forming a plating film containing the above material by an electrolytic plating method or an electroless plating method. Alternatively, the conductive layer may be formed using a conductive paste. At least one of the bonding pad 121, the wiring 122, the connection pad 131a, and the connection pad 131b may be formed by the same process as the conductor layer. The hole filling material is formed using, for example, an insulating material or a conductive material. However, the present invention is not limited to this, and the via 16a and the via 16b may be formed by, for example, filling the opening with a conductive material by copper plating or the like.

  As described above, in the present embodiment, the connection pad (test pad) for inspecting the signal between the memory and the memory controller in the operation test is formed on the second surface of the wiring board. Thereby, in the semiconductor memory device, the state of signals between the memory and the memory controller can be easily inspected by an operation test after assembly.

  When providing connection pads, it is necessary to increase the pitch of the connection pads. At this time, in order to secure the connection pad formation region, for example, it is conceivable to dispose the connection pad at a position away from the bonding pad. However, if the position of the connection pad moves away from the position of the bonding pad, the wiring length becomes long, so that parasitic capacitance, parasitic resistance, parasitic inductance, and the like increase, causing a reduction in the characteristic impedance of the transmission line.

  In contrast, in this embodiment, vias are formed on the first surface of the wiring board so as to overlap the via land portions of the bonding pads, and connection pads including a part of the vias are formed on the second surface of the wiring board. To do. As a result, parasitic capacitance, parasitic resistance, parasitic inductance, and the like are reduced, and a reduction in operating speed can be suppressed.

  Further, an example of a top layout of the semiconductor memory device 10 shown in FIG. 1 will be described with reference to FIG. FIG. 3 is a top view illustrating a top surface layout example of the semiconductor memory device. In FIG. 3, the insulating resin layer 5 is omitted for convenience.

  In the semiconductor memory device 10 shown in FIG. 3, the memory 2 and the memory controller 3 are mounted on the wiring board 1, and a plurality of connection pads such as the bonding pads 121 electrically connected to the memory 2 through the bonding wires 4 are provided. A pad portion 120 is provided. In FIG. 3, two pad portions 120 are provided, but the present invention is not limited to this.

  An enlarged view of a part of the pad portion 120 is shown in FIG. In FIG. 4, a bonding pad 121 having a rectangular planar shape is illustrated. Thus, the planar shape of the bonding pad 121 is a shape having a major axis and a minor axis, and the joint portion 121a and the via land portion 121b are juxtaposed in the major axis direction.

  Furthermore, the plurality of bonding pads 121 are juxtaposed in the short axis direction so that the directions in the long axis direction are staggered. However, the bonding pads 121 may be juxtaposed so that the major axis directions are the same.

  At this time, the length (L1) in the major axis direction of the bonding pad 121 is preferably 360 μm or less, for example, 356 μm or less. The length (L2) in the minor axis direction of the bonding pad 121 is preferably greater than 60 μm, 190 μm or less, more preferably 180 μm or less, and even more preferably 150 μm or less, considering the alignment accuracy of the via 16a.

  The length (L3) from the junction 121a to the via 16a is preferably 65 μm or less, for example. Here, the length from the center of the junction 121a to the center of the via 16a is L3. The distance (L4) between the bonding pads 121 adjacent in the minor axis direction is preferably 40 μm or less, and more preferably 30 μm or less.

  The distance (L5) between the vias 16a of the bonding pads 121 adjacent to each other in the minor axis direction is larger than 90 μm, 220 μm or less, and further 190 μm or less in consideration of the etching property of the bonding pad 121 and the like. preferable. Here, the length from the center of the reference via 16a to the center of the via 16a of the adjacent bonding pad 121 is defined as the interval between the vias 16a. The shortest distance (L6, also referred to as clearance) between the vias 16a of the bonding pads 121 adjacent in the minor axis direction is preferably 200 μm or less in consideration of substrate manufacturability and reliability. Here, the shortest distance from the peripheral edge of the reference via 16 to the peripheral edge of the adjacent via 16a is L6. Note that the dimensions of the connection pads not used in the operation test are not limited to this, and may be smaller than the bonding pads 121, for example.

  The planar shape of the bonding pad 121 is not limited to a rectangular shape. FIG. 5 is an enlarged view of a part of the pad portion 120 including the bonding pad 121 having a polygonal planar shape.

  The bonding pad 121 shown in FIG. 5 is a bonding pad having a T-shaped planar shape in which the width of the bonding portion 121a of the bonding pad 121 shown in FIG. 4 is narrower than the width of the via land portion 121b. At this time, the width (L2b) of the joint portion 121a in the minor axis direction is, for example, 60 μm or more, preferably less than 190 μm, more preferably less than 180 μm, and even more preferably less than 150 μm.

  Further, the plurality of bonding pads 121 shown in FIG. 5 are juxtaposed along the short axis direction so that the directions in the long axis direction are staggered. At this time, the plurality of bonding pads 121 are juxtaposed while being spaced apart so that the interval between the vias 16a in the minor axis direction is equal to or less than the width of the via land portion 121b in two or more adjacent bonding pads 121. That is, the interval between the via land portions 121b of two or more adjacent bonding pads 121 is narrower than the interval between the via land portions 121b shown in FIG.

  When the via 16a is arranged so as to overlap with the via land portion 121b of the bonding pad 121, it is necessary to increase the width of the bonding pad 121, the degree of freedom in wiring design is lowered, and the accompanying electrical characteristics are deteriorated. There is a problem of an increase in cost due to an increase in the wiring length. On the other hand, as shown in FIG. 5, the degree of freedom in wiring design can be increased by making the width of the bonding portion in the bonding pad 121 narrower than that of the via land portion 121b.

  Next, a layout example of connection pads in the pad portion will be described with reference to FIG. As shown in the upper part of FIG. 6, the pad unit 120 has power supply terminals (VCC, VCCQ, VSS), input / output terminals (IO0 to IO7), a data strobe signal terminal (DQS), and a read enable signal terminal (RE). Assume that a total of 20 connection pads are spaced apart and juxtaposed. Note that the arrangement order of the pads is not limited to this, and is designed according to the positions of the terminals of the memory chip or the memory controller. Further, other connection pads may be provided.

  The power supply terminal is a terminal for supplying the power supply voltage VCC, the input / output circuit power supply voltage VCCQ, and the power supply voltage VSS. The input / output terminal is a terminal for inputting / outputting at least one of a command, an address, program data, and read data. The data strobe signal terminal is a terminal from which a data strobe signal DQS for controlling the timing of data transmission / reception between the memory and the memory controller is output. A differential signal (DQS0, DQSZ0) may be used as the data strobe signal. The read enable signal terminal is a status pin for instructing a read operation or the like. A differential signal (RE0, REZ0) may be used as the read enable signal.

  Of the 20 connection pads, 12 connection pads are required as RE0, REZ0, IO0 to IO7, DQS0, and DQSZ0. At this time, since the two terminals RE0 and REZ0 are often arranged at a place where the pad density is relatively low, the necessity for narrowing the pitch is low. Here, a layout example in which a total of ten connection pads (terminals) IO0 to IO7, DQS0, and DQSZ0 are used as narrow pitch test pads will be described. Other test pads are also referred to as normal connection pads.

  For example, when the planar bonding pads 121 shown in FIG. 4 are used as the ten connection pads in order to function as test pads for operation test, as shown in the middle stage of FIG. 6, IO0 to IO7, DQS0, and DQSZ0 In the 18 terminals including the terminal and the power supply terminal, when the total length L of the connection pad pitch (interval between the center portions of the connection pads) is L2 = 180 μm, (210 μm (narrow pitch test pad−narrow pitch use) Pitch between test pads) × 7) + (150 μm (pitch between narrow pitch test pad and normal connection pad) × 6) + (90 μm (pitch between normal connection pad and normal connection pad) × 4) = 2730 μm, Furthermore, when L2 = 150 μm, (180 μm (pitch between narrow pitch test pad and narrow pitch test pad) × 7) + (135 μm (pitch between narrow pitch test pad and normal connection pad) × 6) + (90 μm (pitch between normal connection pad and normal connection pad) × 4) = 2430 μm.

  On the other hand, when the planar bonding pad 121 shown in FIG. 5 is used as the ten connection pads in order to function as an operation test test pad, when the total length L is L2 = 180 μm (150 μm ( Narrow-pitch test pad-pitch between narrow-pitch test pads) × 7) + (150 μm (pitch between narrow-pitch test pad-normal connection pads) × 6) + (90 μm (between normal connection pads-normal connection pads) Pitch) × 4) = 2430 μm, and when L2 = 150 μm, (135 μm (pitch between narrow pitch test pad and narrow pitch test pad) × 7) + (135 μm (narrow pitch test pad—normal connection) (Pitch between pads) × 6) + (90 μm (Pitch between normal connection pad−Normal connection pad) × 4) = 2215 μm. In this manner, the pitch can be further reduced by configuring the test pad using the planar bonding pad shown in FIG.

  Next, the planar shape of the connection pad 131a will be described with reference to FIGS. 7 and 8 are diagrams showing the planar shape of the connection pads.

  The planar shape of the connection pad 131a shown in FIG. 7 is circular. At this time, only the exposed surface of the via 16a may be regarded as the connection pad 131a. Moreover, the planar shape of the connection pad 131a shown in FIG. 8 is a rectangle. At this time, for example, the connection pad 131a may be extended in the minor axis direction. Thus, by forming the connection pad 131a larger than the diameter of the via 16a, for example, the probe pin of the memory tester can easily come into contact, and the operation test can be easily performed.

  This embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... Memory, 3 ... Memory controller, 4 ... Bonding wire, 5 ... Insulating resin layer, 6 ... Conductive layer, 10 ... Semiconductor memory device, 11 ... Insulating layer, 12 ... Wiring layer, 13 ... Wiring layer 14 ... solder resist, 15 ... solder resist, 16 ... via, 16a ... via, 16b ... via, 120 ... pad part, 121 ... bonding pad, 121a ... joining part, 121b ... via land part, 122 ... wiring, 131a ... connection Pad 131b: Connection pad.

Claims (5)

A wiring board having a first surface and a second surface facing each other;
A memory mounted on the first surface;
A bonding wire for electrically connecting the wiring board and the memory;
A memory controller mounted on the first surface and electrically connected to the memory via the wiring board;
An insulating resin layer that seals the memory, the memory controller, and the bonding wire;
The wiring board is
A bonding pad provided on the first surface and having a bonding portion to which the bonding wire is bonded, and a via land portion;
A via penetrating the wiring board so as to overlap the via land portion;
A connection pad provided on the second surface so as to overlap the via, electrically connected to the bonding pad via the via, and exposed to the second surface so as to include a part of the via A semiconductor memory device. The semiconductor memory device according to claim 1,
The connection pad functions as a terminal for inputting / outputting at least one of a command, an address, program data, and read data or a test pad for a data strobe signal terminal. The semiconductor memory device according to claim 1 or 2,
As the bonding pad, it has a plurality of bonding pads provided in parallel with the via land portion along the major axis direction, the bonding pad having a width narrower than the width of the via land portion,
The semiconductor memory device, wherein the plurality of bonding pads are juxtaposed while being spaced apart so that the directions of the major axes are staggered. The semiconductor memory device according to claim 3.
The via has a diameter of 80 μm or less;
The semiconductor memory device, wherein an interval between the vias of two or more adjacent bonding pads is equal to or less than a width of the via land portion. In any one of Claims 1 thru | or 4,
The semiconductor memory device, wherein the planar shape of the connection pad is rectangular.

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