JP2016004860A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve bond strength in a laminated semiconductor device.SOLUTION: A semiconductor device comprises: an interface ship IF and a core chip CC0 which have plane sizes different from each other; a plurality of back bumps BB which are provided on a surface of the interface chip IF and arranged in a longer side direction along a central part of the chip and a plurality of back bumps BB which are provided on the surface of the interface chip IF and arranged in a shorter side direction along an edge of the chip; and surface bumps FB which are provided on a surface of the core chip CC0 and bonded to the back bumps BB of the interface chip IF, respectively. According to the present embodiment, since bond strength between semiconductor chips adjacent to each other in a vertical direction is improved, reliability of the semiconductor device can be improved.

Description

  The present invention relates to a semiconductor device, and more particularly to a stacked semiconductor device in which a plurality of semiconductor chips are stacked.

  In recent years, stacked semiconductor devices in which a plurality of semiconductor chips are stacked, such as a memory chip and a control chip for controlling the memory chip, are widely used. In a stacked semiconductor device, electrodes are provided on the surface of each semiconductor chip, and electrical and mechanical connections are made by joining electrodes of semiconductor chips adjacent vertically.

  For example, in the stacked semiconductor devices described in Patent Documents 1 and 2, a semiconductor in which a plurality of core chips in which DRAM (Dynamic Random Access Memory) memory cores are integrated and an interface chip for controlling the memory cores are stacked. An apparatus is described. The core chip includes a through electrode provided so as to penetrate the semiconductor substrate, and a laminated body composed of a plurality of core chips is configured by joining through electrodes existing at positions overlapping in plan view. The interface chip is also provided with a through electrode, and the through electrode of the core chip located in the lowermost layer and the through electrode of the interface chip are joined.

JP 2013-183120 A JP 2013-1973387 A

  However, since the core chip and the interface chip have different planar shapes and sizes, the bonding strength between the core chip and the interface chip may be insufficient compared to the case where the core chips are bonded to each other. Such a problem is a problem that occurs not only when a core chip and an interface chip are stacked, but also when a plurality of semiconductor chips are stacked.

  A semiconductor device according to an aspect of the present invention includes a semiconductor chip having first and second surfaces facing each other, a first semiconductor chip formed on the first surface, and in a long side direction along a central portion of the semiconductor chip. A plurality of first electrodes arranged on the second surface, a plurality of second electrodes formed on the second surface and arranged at a second pitch different from the first pitch, and the first And a plurality of third electrodes arranged in a short side direction along the edge of the semiconductor chip.

  A semiconductor device according to another aspect of the present invention includes a first semiconductor chip having a first planar size, a second semiconductor chip having a second planar size different from the first planar size, and the first semiconductor chip. A plurality of first electrodes provided on a surface of one semiconductor chip and arranged in a long side direction along a central portion of the semiconductor chip; and provided on the surface of the first semiconductor chip; A plurality of second electrodes arranged in the short-side direction along the edges of the first semiconductor chip, and a plurality of third electrodes provided on the surface of the second semiconductor chip and joined to the plurality of first electrodes, respectively. And a plurality of fourth electrodes provided on the surface of the second semiconductor chip and joined to the plurality of second electrodes, respectively.

  According to the present invention, the bonding strength between vertically adjacent semiconductor chips is improved, so that the reliability of the semiconductor device can be increased.

It is typical sectional drawing for demonstrating the structure of the semiconductor device 10 by preferable embodiment of this invention. It is sectional drawing which shows the structure of penetration electrode TSV provided in core chip CC0-CC6, and front surface bump FB and back surface bump BB corresponding to this. It is sectional drawing which shows the structure of the surface bump FB provided in core chip CC7. It is sectional drawing which shows the structure of penetration electrode TSV provided in interface chip IF, and back surface bump BB corresponding to this. It is sectional drawing which shows the structure of the surface bump FB provided in interface chip IF. 2 is a schematic plan view showing a layout of a core chip CC0 according to the first embodiment. FIG. 2 is a schematic plan view showing a layout of an interface chip IF according to the first embodiment. FIG. FIG. 6 is a schematic plan view showing a layout of a core chip CC0 according to a second embodiment. 6 is a schematic plan view showing a layout of an interface chip IF according to a second embodiment. FIG.

  Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment has the same function as each other, and is different from the eight core chips CC0 to CC7 manufactured using the same manufacturing mask, and the core chips CC0 to CC7. It has a structure in which one interface chip IF manufactured using a manufacturing mask and one interposer IP are stacked. The core chips CC0 to CC7 and the interface chip IF are semiconductor chips using a silicon substrate, and are stacked on the interposer IP in a face-down manner. The face-down method refers to a method in which a semiconductor chip is mounted such that a main surface on which an electronic circuit such as a transistor is formed faces downward, that is, the main surface faces the interposer IP side.

  However, the semiconductor device according to the present invention is not limited to this, and each semiconductor chip may be stacked in a face-up manner. The face-up method refers to a method in which a semiconductor chip is mounted so that a main surface on which an electronic circuit such as a transistor is formed faces upward, that is, the main surface faces away from the interposer IP. Further, semiconductor chips stacked by the face-down method and semiconductor chips stacked by the face-up method may be mixed.

  Of these semiconductor chips, the core chips CC0 to CC6 and the interface chip IF, excluding the core chip CC7 located in the uppermost layer, are each provided with a number of through electrodes TSV (Through Substrate Via) penetrating the semiconductor substrate. In the core chips CC <b> 0 to CC <b> 6, the front bump FB and the rear bump BB are provided at a position overlapping the through electrode TSV in a plan view as viewed from the stacking direction. The surface bump FB is an electrode provided on the main surface side, and is disposed on the surface of the multilayer wiring structure covering the main surface of the semiconductor substrate. On the other hand, the back surface bump BB is an electrode disposed on the back surface of the semiconductor substrate.

  On the other hand, in the interface chip IF, the back bump BB is provided at a position overlapping the through electrode TSV in a plan view as viewed from the stacking direction, but the front bump FB is not provided at a position overlapping the through electrode TSV in a plan view. There is a case. This is because the interface chip IF is a chip located in the lowest layer and needs to be connected to the interposer IP. That is, since the substrate electrodes 11 provided on the interposer IP are arranged at a pitch allowed by the wiring rule of the interposer IP, the arrangement pitch of the substrate electrodes is larger than the arrangement pitch of the through electrodes TSV. For this reason, it is necessary to perform pitch conversion in the interface chip IF located in the lowermost layer. For this reason, many surface bumps FB are provided at different planar positions from the through silicon via TSV.

  Of these nine semiconductor chips, the back surface bump BB of the semiconductor chip located in the lower layer and the front surface bump FB of the semiconductor chip located in the upper layer are joined to connect the semiconductor chips adjacent vertically. Is done.

  As described above, the through-hole electrode TSV is not provided in the uppermost core chip CC7. This is because the uppermost core chip CC7 is laminated in a face-down manner, and it is not necessary to form a bump electrode on the back side of the core chip CC7. Thus, when the through-hole electrode TSV is not provided in the uppermost core chip CC7, the uppermost core chip CC7 can be made thicker than the other core chips CC0 to CC6, so that the mechanical strength of the core chip CC7 is increased. It becomes possible. However, in the present invention, the through silicon via TSV may be provided in the uppermost core chip CC7. In this case, all the core chips CC0 to CC7 can be manufactured in the same process.

  The core chips CC0 to CC7 are semiconductor chips in which a so-called front end portion that interfaces with the outside is deleted from circuit blocks included in a normal SDRAM (Synchronous DRAM) that operates alone. In other words, it is a memory chip in which only memory cores belonging to the back-end unit are integrated. The circuit block included in the front end unit includes a parallel / serial conversion circuit that performs parallel / serial conversion of input / output data between the memory cell array and the data input / output terminals, and a DLL (Delay Locked) that controls the input / output timing of data. Loop) circuit.

  On the other hand, the interface chip IF is a semiconductor chip in which only a front end portion is integrated among circuit blocks included in a normal SDRAM operating alone. The interface chip IF functions as a common front end unit for the eight core chips CC0 to CC7. Therefore, all external accesses are performed via the interface chip IF, and data input / output is also performed via the interface chip IF.

  On the other hand, the interposer IP is a circuit board made of resin, and a plurality of external terminals (solder balls) SB are formed on the back surface IPb thereof. The interposer IP functions as a rewiring board for ensuring the mechanical strength of the semiconductor device 10 and increasing the electrode pitch. That is, the substrate electrode 11 formed on the upper surface IPa of the interposer IP is drawn out to the back surface IPb by the through-hole electrode 12, and the pitch of the external terminals SB is expanded by the rewiring layer 13 provided on the back surface IPb. A portion of the upper surface IPa of the interposer IP where the substrate electrode 11 is not formed is covered with a resist 16. Further, a portion of the back surface IPb of the interposer IP where the external terminal SB is not formed is covered with a resist 17. Although only five external terminals SB are shown in FIG. 1, a large number of external terminals are actually provided. The layout of the external terminal SB is the same as that in the SDRAM defined by the standard. Therefore, it can be handled as one SDRAM from an external controller.

  The gap between the stacked core chips CC0 to CC7 and the interface chip IF is filled with an underfill 14, thereby ensuring mechanical strength. NCP (Non-Conductive Paste) 15 is filled in the gap between the interposer IP and the interface chip IF. The entire package is covered with a mold resin 18. Thereby, each chip is physically protected.

  FIG. 2 is a cross-sectional view showing the structure of the through silicon vias TSV provided in the core chips CC0 to CC6 and the corresponding front surface bumps FB and back surface bumps BB.

  FIG. 2 shows two through silicon vias TSV, and front bumps FB and back bumps BB corresponding to them. The pitch of the front surface bump FB and the pitch of the back surface bump BB in the core chips CC0 to CC6 are both P0.

  As shown in FIG. 2, the core chips CC <b> 0 to CC <b> 6 have a semiconductor substrate 20, a multilayer wiring structure 30 provided on the main surface of the semiconductor substrate 20, and a passivation film 21 that covers the back surface of the semiconductor substrate 20. The through silicon vias TSV provided in the core chips CC <b> 0 to CC <b> 6 are provided through the semiconductor substrate 20, and further penetrate through the interlayer insulating film 31 and the passivation film 21 included in the multilayer wiring structure 30. Although not particularly limited, the through silicon via TSV is made of Cu (copper). The main surface 20a of the semiconductor substrate 20 is a device formation surface on which devices such as transistors are formed. The periphery of the through electrode TSV is covered with an insulating layer 22, thereby ensuring insulation between the through electrode TSV and the semiconductor substrate 20.

  An end portion of the through silicon via TSV on the back surface side of the semiconductor substrate 20 is covered with a back surface bump BB. Although not particularly limited, the back surface bump BB is made of SnAg solder covering the surface of the through silicon via TSV made of Cu (copper). On the other hand, the end portion of the through silicon via TSV on the surface side of the semiconductor substrate 20 is connected to the pad wiring MP <b> 1 included in the multilayer wiring structure 30.

  The multilayer wiring structure 30 has a structure in which interlayer insulating films 31 to 35, a cover film 36, and a polyimide film 37 are laminated, and wiring layers M1 to M4 are provided on the surfaces of the interlayer insulating films 31, 33 to 35. It has been. The wiring layers M1 to M4 are provided with normal wirings ML1 to ML4 and pad wirings MP1 to MP4, respectively. The normal wirings ML1 to ML4 are signal wirings and power supply wirings. On the other hand, the pad wirings MP1 to MP4 are wirings assigned to the through silicon vias TSV, and are provided at positions overlapping the corresponding through silicon vias TSV in plan view. The pad wirings MP1 to MP4 adjacent to each other in the vertical direction are connected to each other through the through-hole conductor TH, whereby the front surface bump FB and the back surface bump BB are short-circuited through the through electrode TSV. .

  2 are power supply pad wirings MP1 to MP4, and are designed to have a larger area than signal pad wirings MP1 to MP4 (not shown) in order to lower the power supply resistance. The power supply pad wirings MP1 to MP4 are connected to the internal circuit in the chip via the normal wirings ML1 to ML4, whereby power is supplied to the internal circuit. In addition, with respect to a part of the signal pad wirings MP1 to MP4, a part of the through-hole conductor TH is deleted, so that the front surface bump FB and the back surface bump BB that are present in an overlapping position in plan view may not be short-circuited. .

  FIG. 3 is a cross-sectional view showing the structure of the surface bump FB provided on the core chip CC7.

  As shown in FIG. 3, since the core chip CC7 is not provided with the through electrode TSV, the pad wirings MP1, MP2 and the like corresponding to the surface bump FB are omitted. Since other configurations are as shown in FIG. 2, the same reference numerals are given to the same elements, and duplicate descriptions are omitted. Also in the core chip CC7, the pitch of the surface bumps FB is P0.

  FIG. 4 is a cross-sectional view showing the structure of the through silicon via TSV provided in the interface chip IF and the back surface bump BB corresponding thereto.

  FIG. 4 shows two through silicon vias TSV, and front bumps FB and back bumps BB corresponding thereto. Also in the interface chip IF, the pitch of the back bumps BB is P0.

  As shown in FIG. 4, in the interface chip IF, the surface bump FB is not provided at a position overlapping with most of the through electrodes TSV in plan view except for some of the through electrodes TSV. This is because pitch conversion is performed by the interface chip IF as described above. Since other configurations are as shown in FIG. 2, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  FIG. 5 is a cross-sectional view showing the structure of the surface bump FB provided on the interface chip IF.

  As shown in FIG. 5, a surface bump FB having a pitch enlarged to P1 (> P0) is provided on the surface side of the interface chip IF. The structure is the same as that of the surface bump FB shown in FIG. 3, and corresponding pad wirings MP1, MP2 and the like are omitted. Since other configurations are as shown in FIG. 23, the same reference numerals are given to the same elements, and redundant descriptions are omitted.

  The through silicon via TSV, the front surface bump FB, the back surface bump BB, and the like shown in FIGS. 4 and 5 are elements used for power supply. In this case, the through silicon via TSV and the back surface bump BB shown in FIG. 4 and the front surface bump FB shown in FIG. 5 are short-circuited inside the interface chip IF. As a result, the power supply potential supplied from the interposer IP is supplied to the interface chip IF and the core chips CC0 to CC7. Further, the signal supplied from the interposer IP is input to an internal circuit (not shown) via the front surface bump FB shown in FIG. 5, and then undergoes a predetermined process, and then the through electrode TSV and the back surface bump shown in FIG. Output from BB.

  FIG. 6 is a schematic plan view showing the layout of the core chip CC0 according to the first embodiment.

  As shown in FIG. 6, the core chip CC0 has 16 memory banks BANK0 to BANK15. Among them, the memory banks BANK0 to BANK3, BANK8 to BANK11 are arranged in an area close to one side L11 in the Y direction of the core chip CC0, and the memory banks BANK4 to BANK7 and BANK12 to BANK15 are the other in the Y direction of the core chip CC0. It is arranged in an area close to the side L12 on the side. Sides L11 and L12 are long sides of the core chip CC0. Each memory bank is divided into two in the Y direction, and a row decoder XDEC for performing row access is arranged between them.

  A column decoder YDEC, a main amplifier MA, and a fuse circuit FUSE are arranged between memory banks adjacent in the X direction. The column decoder YDEC is a circuit for performing column access. The main amplifier MA is a circuit for amplifying read data or write data. The fuse circuit FUSE is a circuit for storing a defective address.

  A peripheral circuit PEC extending in the X direction is disposed at the center of the chip in the Y direction. Examples of circuits included in the peripheral circuit PEC include a logic circuit, a power supply circuit, and an input / output circuit. A large number of surface bumps FB are provided in the region S1 between the peripheral circuit PEC and the memory bank BANK, and through electrodes TSV are provided at positions overlapping the surface bumps FB in plan view. The through silicon vias TSV arranged in the region S1 are mainly a power through electrode and a signal through electrode.

  Further, the core chip CC0 includes a large number of surface bumps FB disposed in the region S2 along the sides L13 and L14 and the through silicon via TSVD corresponding thereto. Sides L13 and L14 are short sides of the core chip CC0. The through silicon via TSVD disposed in the region S2 is a dummy through electrode, and has the same structure as the through silicon via TSV shown in FIG. 2, but is not used for either power supply or signal and is exclusively joined. It is provided to increase the strength. Therefore, these may be in a floating state. Then, by bonding the lower surface bump BB corresponding to the dummy through electrode TSVD and the upper surface bump FB, the short side of the chip is firmly bonded, so that the warp of the chip can be prevented.

  In the present embodiment, the dummy through silicon vias TSVD arranged in the region S2 are grouped into two groups. The first group is a group G1 arranged near both ends in the Y direction, and the second group is a group G2 arranged near the center in the Y direction.

  A plurality of test pads TP are also arranged in the region S2. The test pad TP is an electrode for contacting a tester probe in an operation test performed before lamination, and is designed to have a larger planar size and a larger pitch than the surface bump FB.

  Further, an alignment mark FCM is provided in the region S2. The alignment mark FCM is configured by a wiring pattern provided on the uppermost wiring layer M4 on the main surface side of the chip, and is configured by a back surface bump BB on the back surface side of the chip.

  Other core chips CC1 to CC6 have the same structure as the core chip CC0 shown in FIG. On the other hand, the uppermost core chip CC7 basically has the same configuration as the core chip CC0. However, as already described, the core chip CC7 is not provided with the through silicon via TSV and the back surface bump BB.

  The core chips CC <b> 0 to CC <b> 7 having such a configuration are laminated so that the back surface bump BB of the chip located in the lower layer and the surface bump FB of the chip located in the upper layer are bonded. For this reason, the core chips CC0 to CC7 that are vertically adjacent to each other are joined at the portions corresponding to the region S1 and the region S2, thereby keeping the gap between the chips constant.

  FIG. 7 is a schematic plan view showing the layout of the interface chip IF according to the first embodiment.

  As shown in FIG. 7, a peripheral circuit PEIF extending in the X direction is arranged at the center of the interface chip IF in the Y direction. Examples of circuits included in the peripheral circuit PEIF include a logic circuit, a power supply circuit, and a fuse circuit. In the region S3 on both sides in the Y direction of the peripheral circuit PEIF, a plurality of through silicon vias TSV are arranged so as to sandwich the peripheral circuit PEIF. The layout of the through silicon via TSV arranged in the region S3 matches the layout of the through silicon via TSV arranged in the region S1 of the core chips CC0 to CC6. The through silicon vias TSV arranged in the region S3 are mainly a power through electrode and a signal through electrode.

  Furthermore, the interface chip IF includes a large number of through silicon vias TSVD arranged in a region S4 along the sides L23 and L24. Sides L23 and L24 are short sides of the interface chip IF. The through electrode TSVD arranged in the region S4 is a dummy through electrode, and has the same structure as the through electrode TSV shown in FIG. 4, but is not used for either power supply or signal, and is exclusively joined. It is provided to increase the strength. Therefore, these may be in a floating state. Then, the back surface bump BB corresponding to the through silicon via TSVD disposed in the region S4 is bonded to the surface bump FB corresponding to the group G2 among the surface bumps FB disposed in the region S2 of the core chip CC0. Is increased.

  However, the interface chip IF is at least smaller in width in the Y direction than the core chips CC0 to CC7. For this reason, among the surface bumps FB arranged in the region S2 of the core chip CC0, the surface bumps FB corresponding to the group G1 are exposed without being covered by the interface chip IF. Therefore, the surface bump FB corresponding to the group G1 is not used in the core chip CC0.

  Further, input / output circuits DQ, DLL circuits, test circuits DFT, BIST, and the like are disposed between the long sides L21, L22 of the interface chip IF and the region S3, and surface bumps FB and test pads TP are disposed. Is placed. The surface bump FB provided on the interface chip IF has the structure shown in FIG. 5 and is bonded to the substrate electrode 11 provided on the interposer IP.

  As described above, in the first embodiment, the interface chip IF and the core chip CC0 are not only joined to each other at the portions corresponding to the regions S1 and S3, but are also joined to each other at the portions corresponding to the regions S2 and S4. Is done. In the present embodiment, since the interface chip IF has an elongated shape in the X direction, there is a concern about the occurrence of warping in the X direction. However, the interface chip IF is joined to the core chip CC0 at a portion corresponding to the region S4 along the short side. Therefore, it is possible to greatly suppress the warpage of the interface chip IF.

  FIG. 8 is a schematic plan view showing the layout of the core chip CC0 according to the second embodiment.

  As shown in FIG. 8, the core chip CC0 according to the present embodiment is different from the first embodiment shown in FIG. 6 in that the power supply circuit PUMP is arranged in the region S2. Since other configurations are as shown in FIG. 6, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  The power supply circuit PUMP is arranged in an empty area located between the surface bump FB of the group G1 and the surface bump FB of the group G2 in plan view. The power supply circuit PUMP receives the power supply potential via the surface bump FB of the group G2, and generates a desired internal potential by boosting or stepping down the power supply potential. Therefore, in the present embodiment, among the dummy through silicon vias TSVD, at least the dummy through silicon via TSVD belonging to the group G2 is used for power supply.

  FIG. 9 is a schematic plan view showing the layout of the interface chip IF according to the second embodiment.

  As shown in FIG. 9, the interface chip IF according to the present embodiment has the first embodiment shown in FIG. 7 in that a surface bump FBV for power supply is provided adjacent to the dummy through electrode TSVD. Is different. Since other configurations are as shown in FIG. 7, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  In the present embodiment, the power supply potential is supplied from the interposer IP to the interface chip IF via the power supply surface bump FBV, and this is supplied to the core chips CC0 to CC7 via the dummy through electrode TSVD. The power supply potential supplied via the dummy through electrode TSVD is supplied to the power supply circuit PUMP, thereby generating an internal potential. Thus, in this embodiment, since the dummy through electrode TSVD is used for the power supply, in addition to the effects of the first embodiment, the power supply can be further strengthened.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Substrate electrode 12 Through-hole electrode 13 Rewiring layer 14 Underfill 16, 17 Resist 18 Mold resin 20 Semiconductor substrate 20a Main surface 21 of semiconductor substrate Passivation film 22 Insulating layer 30 Multilayer wiring structure 31 Interlayer insulating film 31- 35 Interlayer insulating film 36 Cover film 37 Polyimide film BANK0 to BANK15 Memory bank BB Back surface bump CC0 to CC7 Core chip FB, FBV Front surface bump FCM Alignment mark G1, G2 Group IF Interface chip IP Interposer IPa Top surface IPb Back surface L11-L14, L21-L24 Side M1 to M4 Wiring layer ML1 to ML4 Normal wiring MP1 to MP4 Pad wiring PEC, PEIF Peripheral circuit PUMP Power supply circuit S1 to S4 Area SB External terminal TH Through-hole conductor P test pad TSV, TSVD through electrode

Claims (14)

A semiconductor chip having first and second surfaces facing each other;
A plurality of first electrodes formed on the first surface and arranged at a first pitch in a long side direction along a central portion of the semiconductor chip;
A plurality of second electrodes formed on the second surface and arranged at a second pitch different from the first pitch;
A semiconductor device comprising: a plurality of third electrodes formed on the first surface and arranged in a short side direction along an edge of the semiconductor chip.   The semiconductor device according to claim 1, wherein the second pitch is larger than the first pitch. The semiconductor chip includes a semiconductor substrate and a multilayer wiring structure formed on the main surface of the semiconductor substrate,
The semiconductor device according to claim 2, wherein the first surface is constituted by a back surface of the semiconductor substrate, and the second surface is constituted by a surface of the multilayer wiring structure.   The semiconductor device according to claim 3, wherein the plurality of first and third electrodes include a through electrode penetrating the semiconductor substrate.   The semiconductor device according to claim 4, wherein the plurality of third electrodes are in a floating state.   The semiconductor device according to claim 4, wherein a power supply potential is supplied to the plurality of third electrodes.   A plurality of fourth electrodes formed on the second surface and arranged at the second pitch along the plurality of third electrodes in plan view; The semiconductor device according to claim 6, wherein the power supply potential is supplied through the plurality of fourth electrodes.   The semiconductor device according to claim 7, wherein the plurality of fourth electrodes do not overlap with the plurality of third electrodes in plan view. A first semiconductor chip having a first planar size;
A second semiconductor chip having a second planar size different from the first planar size;
A plurality of first electrodes provided on a surface of the first semiconductor chip and arranged in a long side direction along a central portion of the semiconductor chip;
A plurality of second electrodes provided on the surface of the first semiconductor chip and arranged in a short-side direction along an edge of the semiconductor chip;
A plurality of third electrodes provided on a surface of the second semiconductor chip and respectively joined to the plurality of first electrodes;
A semiconductor device comprising: a plurality of fourth electrodes provided on the surface of the second semiconductor chip and respectively joined to the plurality of second electrodes.   The semiconductor device according to claim 9, wherein the first plane size is smaller than the second plane size. The first semiconductor chip includes a semiconductor substrate and a multilayer wiring structure formed on the main surface of the semiconductor substrate,
The semiconductor device according to claim 9, wherein the front surface of the first semiconductor chip is constituted by a back surface of the semiconductor substrate. A plurality of fifth electrodes provided on the surface of the multilayer wiring structure;
The semiconductor device according to claim 11, wherein an arrangement pitch of the plurality of first electrodes and an arrangement pitch of the plurality of second electrodes are smaller than an arrangement pitch of the plurality of fifth electrodes.   The semiconductor device according to claim 12, wherein the plurality of fifth electrodes do not overlap with the plurality of first and second electrodes in a plan view.   The semiconductor device according to claim 9, further comprising a third semiconductor chip stacked on the second semiconductor chip and having the second planar size.

Images