JP2010010288A - Stacked semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate wiring structure that achieves improvement in signal quality in a stacked semiconductor device in which a plurality of semiconductor packages are stacked. <P>SOLUTION: A stacked semiconductor device 50 includes an upper semiconductor package 52 and a lower semiconductor package 54. A signal line 350 connected to a semiconductor integrated circuit 180 of the lower semiconductor package 54 is connected to the upper semiconductor package 52 via an upper-face electrode 154 on the wiring-substrate upper face 122 of the lower semiconductor package 54 and extracted from the upper-face electrode 154 to a land 200 on the wiring-substrate lower face 124. The upper-face electrode 154 and the land 200 are arranged close to each other in the peripheral edge region of the wiring substrate 120. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a stacked semiconductor device, and more particularly to a semiconductor device having a structure in which a plurality of semiconductor packages are stacked and bonded, that is, a so-called package on package (PoP) structure.

  A system in package (SiP) technology in which a plurality of semiconductor chips are accommodated in one package is known as a technology that can meet demands for higher functionality and downsizing of semiconductor devices. Recently, a package-on-package (PoP) technology in which a plurality of packages incorporating semiconductor chips are stacked has been developed. As compared with SiP, PoP can flexibly and easily configure semiconductor devices with various specifications by combining various package parts.

  In general, a semiconductor device may be provided with a terminal or an electrode for inspection, and the terminal or the like is used to perform inspection before shipment or mounting, failure analysis, or the like. In order to sufficiently exhibit the high functions of the SiP type or PoP type semiconductor device, it is preferable to perform the above inspection, analysis, and the like.

  Although not SiP type and PoP type semiconductor devices, Patent Documents 1 and 2 disclose semiconductor devices having a structure for inspection.

  Patent Document 1 discloses a ball grid array (BGA) package having an additional electrode that can also be used as a test terminal. Specifically, the ball electrodes forming the BGA are arranged in a lattice shape in an inner ball arrangement area with a certain area (ball arrangement prohibited area) from the outer periphery of the package, and the additional electrodes are arranged in the ball arrangement prohibited area. Yes. The additional electrode is exposed on the back surface of the element mounting surface of the package substrate.

  Patent Document 2 discloses a module structure for inspecting a memory element incorporated in a BGA package in a state where the package is mounted on a module substrate (mounting substrate). Specifically, a solder ball (ball electrode) that constitutes an external electrode lead of a BGA package is provided on a test signal line for a package drawn out of the solder ball alignment group in the BGA module, a connection portion, and a module substrate. To the probe pad on the module substrate via the substrate test signal line. The connecting portion is composed of pads connected to the signal lines and a connecting member (desirably manufactured in a ball shape like a solder ball) for connecting the two pads.

JP 2006-294976 A JP 2005-10147 A

  In inspection / analysis of a semiconductor device, it is useful to monitor not only a signal (output signal) output to the outside of the package but also a signal (internal signal) used inside the package. For this purpose, it is necessary to draw an internal signal to the outside of the package. However, the wiring for drawing out the signal may act as an open stub and degrade the signal quality.

  In addition, SiP type and PoP type semiconductor devices have a large number of terminals, wirings, and the like, but their arrangement may cause a reduction in signal quality.

  In addition, for inspection and analysis, a configuration for selectively supplying power to only a part of the internal circuit and a configuration for inputting signals generated separately outside the semiconductor device to the internal circuit are adopted. In some cases, these configurations may cause a decrease in signal quality.

  As described above, the signal quality may be deteriorated due to various factors.

  As described above, the PoP structure can flexibly and easily cope with various specifications, so that an increase in demand is expected in the future. For this reason, it is thought that the request | requirement of the signal quality improvement with respect to a PoP structure will become increasingly strong.

  An object of the present invention is to provide a semiconductor device capable of improving the signal quality of a stacked semiconductor device (so-called PoP type semiconductor device) in which a plurality of semiconductor packages are stacked.

  In one embodiment according to the present invention, the stacked semiconductor device includes an upper semiconductor package and a lower semiconductor package. The signal line connected to the semiconductor integrated circuit of the lower semiconductor package is connected to the upper semiconductor package via the upper surface electrode on the upper surface of the wiring substrate of the lower semiconductor package, and is drawn from the upper surface electrode to the land on the lower surface of the wiring substrate. It is. The upper surface electrode and the land are arranged close to each other in the peripheral region of the wiring board.

  In another embodiment of the present invention, the semiconductor integrated circuit has a plurality of interface units, and each interface unit is provided at a chip corner of the semiconductor chip. The upper surface electrode connected to each interface unit is arranged along two sides adjacent to the interface unit among the sides forming the outline of the wiring board.

  According to the embodiment, a signal (internal signal) transmitted between the lower semiconductor package and the upper semiconductor package is drawn to the land on the lower surface of the substrate. By using the land, it is possible to inspect an internal signal. At this time, since the upper surface electrode and the land are disposed close to each other on the peripheral edge side of the substrate, the signal lead-out line is shortened as compared with the configuration in which the land is disposed on the central side of the substrate, that is, the inner side (inner peripheral side) of the terminal array. Is possible. For this reason, it is possible to improve signal quality by suppressing signal reflection by the signal lead-out line.

  Further, according to the embodiment, the upper semiconductor package and the signal lead line are connected to the signal line at the upper surface electrode. For this reason, compared with the configuration in which the signal lead-out line is connected to the signal line at a position away from the upper surface electrode, the number of electrical connection points that can cause signal reflection can be reduced. Thereby, the signal quality can be improved.

  According to another embodiment described above, it is possible to eliminate the arrangement that bypasses the semiconductor integrated circuit for the wiring connecting the interface unit and the upper surface electrode. For this reason, signal quality can be improved by shortening wiring.

  FIG. 1 illustrates a cross-sectional view outlining the structure of a stacked semiconductor device 50 according to an embodiment of the present invention. For the sake of illustration, FIG. 1 also shows a substrate (or mother board) 56 on which the stacked semiconductor device 50 is mounted with a one-dot chain line.

  In the example of FIG. 1, the stacked semiconductor device 50 has a structure in which two semiconductor devices (or semiconductor packages) 52 and 54 are stacked, and has a so-called package-on-package (PoP) structure. Hereinafter, for easy understanding, the semiconductor package 54 on the side close to the mounting substrate 56 is referred to as a lower package 54, and the semiconductor package 52 that is stacked on the lower package 54 and is far from the mounting substrate 56 is referred to as the lower package 54. It will be referred to as the upper package 52.

  The expression “upper side” used in this specification is relatively defined when the side mounted on the mounting substrate 56 in the stacked semiconductor device 50 is referred to as “lower side”. That is, the expressions “upper side” and “lower side” in this specification do not intend an absolute positional relationship that is determined based on the direction of gravity or the like. This also applies to expressions such as “upper surface” and “lower surface” which will be described later.

  In the example of FIG. 1, the upper package 52 includes a wiring substrate 60, an upper semiconductor integrated circuit 90, bonding wires 98, a sealing resin 100, and terminals (or electrodes) 110.

  The wiring board 60 is a multilayer wiring board having a predetermined wiring structure. The upper semiconductor integrated circuit 90 is mounted on the central portion of one main surface 62 (hereinafter also referred to as a substrate upper surface 62) of the wiring substrate 60. Here, the upper semiconductor integrated circuit 90 is composed of two semiconductor chips 92 a and 92 b, and both the chips 92 a and 92 b are stacked on the substrate upper surface 62.

  For example, the two semiconductor chips 92 a and 92 b may be arranged on the substrate upper surface 62 without being stacked. In addition, for example, a semiconductor chip in which the structures of two semiconductor chips 92a and 92b are integrated into one chip can be used.

  The bonding wires 98 connect predetermined terminals of the semiconductor chips 92a and 92b and predetermined wirings of the wiring board 60, respectively. In the cross-sectional position shown in FIG. 1, the bonding wire 98 connected to the semiconductor chip 92b is not shown, but extends in a cross section perpendicular to the drawing, for example. The semiconductor chip 92a disposed directly on the wiring board 60 may be connected to a predetermined wiring of the wiring board 60 by a flip chip (FC) connection technique.

  The sealing resin 100 is disposed on the upper surface 62 of the substrate so as to cover the semiconductor chips 92 a and 92 b of the semiconductor integrated circuit 90 and the bonding wires 98.

  The terminal 110 constitutes an external connection terminal in the upper package 52, and the other main surface 64 of the wiring substrate 60, that is, a main surface 64 that forms a front-back relationship with the main surface 62 (hereinafter also referred to as a substrate lower surface 64). ). Each of the terminals 110 is connected to a predetermined wiring of the wiring board 60 and is connected to the semiconductor integrated circuit 90 via the wiring or the like. Here, each of the terminals 110 is constituted by a ball electrode (also referred to as a bump electrode) using a solder ball.

  In the example of FIG. 1, the lower package 54 includes a wiring substrate 120 and a lower semiconductor integrated circuit 180.

  The wiring board 120 is a multilayer wiring board having a predetermined wiring structure. The lower semiconductor integrated circuit 180 is mounted on the central portion of one main surface 122 (hereinafter also referred to as a substrate upper surface 122) of the wiring substrate 120. The substrate upper surface 122 is a surface facing the upper package 52 in the wiring substrate 120.

  In this example, the lower semiconductor integrated circuit 180 is constituted by one semiconductor chip 182, and the chip 182 is flip-chip connected to the wiring of the wiring board 120 via the gold bump 188. It can also be used. In the example of FIG. 1, an underfill 189 made of an insulating resin or the like is filled between the semiconductor chip 182 and the wiring substrate 120. The entire semiconductor chip 182 may be covered with a mold resin (not shown).

  The wiring board 120 has terminals 190 and lands 200.

  The terminal 190 constitutes an external connection terminal in the lower package 54, and constitutes an external connection terminal in the stacked semiconductor device 50. It is provided on the other main surface 124 of the wiring board 120, that is, the main surface 124 (hereinafter also referred to as a substrate lower surface 124) that forms a front-back relationship with the main surface 122. Each of the terminals 190 is connected to a predetermined wiring of the wiring board 120, and is connected to the semiconductor integrated circuit 180 or the like via the wiring. Here, each terminal 190 is constituted by a ball electrode made of a solder ball.

  The land 200 is a land provided in an opening of the substrate lower surface 124 among the lands in the wiring substrate 120. Each land 200 is connected to a predetermined wiring of the wiring board 120. The land 200 is located at a position retracted to the inner side of the wiring board 120 as compared with the terminal (ball electrode) 190. Therefore, even when the ball electrode 190 is in contact with the mounting board 56 (mounted state), Does not contact the mounting substrate 56.

  Here, FIG. 2 illustrates an enlarged cross-sectional view of the stacked semiconductor device 50, and an example of the structure of the wiring boards 60 and 120 will be described. In FIG. 2, the sealing resin 100 is not shown.

  In the wiring substrate 60 illustrated in FIG. 2, the wiring layer LL <b> 1 and the insulating layer 82 are stacked in this order on one main surface 72 (or the upper surface 72) of the insulating layer 70, and the other main surface of the insulating layer 70. On the surface 74 (or the lower surface 74), the wiring layer LL2 and the insulating layer 86 are laminated in this order. The wiring layers LL1 and LL2 are made of, for example, copper, the insulating layer 70 is made of, for example, glass epoxy resin, and the insulating layers 82, 86 are made of, for example, polyimide resin, epoxy resin, or the like. The insulating layer 70 is thicker than the other layers LL1, 82, LL2, 86 and may be called a core material. The insulating layers 82 and 86 are solder resists.

  The wiring layers LL1 and LL2 are each formed with a predetermined conductive pattern, and a signal line, a power supply line, and the like are configured by the conductive pattern. In the portion illustrated in FIG. 2, the wiring layer LL1 has a wiring 80, the wiring layer LL2 has a wiring 84, and both the wirings 80 and 84 penetrate between the two main surfaces 72 and 74 of the insulating layer 70. They are electrically connected through through holes (or via holes) 76.

  The wiring layer LL2 has a land to which the ball electrode 110 is connected, and the insulating layer 86 is opened on the land. Although not shown in FIG. 2, the wiring layer LL1 has a land for wire bonding mounting, and the insulating layer 82 is opened on the land.

  In the wiring board 120 illustrated in FIG. 2, the wiring layer L3, the insulating layer 142, the wiring layer L2, the insulating layer 148, and the wiring layer L1 are formed on one main surface 132 (or the upper surface 132) of the insulating layer 130. And the insulating layer 156 are stacked in this order. On the other main surface 134 (or lower surface 134) of the insulating layer 130, the wiring layer L4, the insulating layer 162, the wiring layer L5, the insulating layer 168, the wiring layer L6, and the insulating layer 176 are formed. Laminated in order.

  The wiring layers L1 to L6 are made of, for example, copper, the insulating layer 130 is made of, for example, glass epoxy resin, and the insulating layers 142, 148, 156, 162, 168, and 176 are made of, for example, polyimide resin, epoxy resin, or the like. It is configured. The insulating layer 130 is thicker than the other layers L1 to L6, 142, 148, 156, 162, 168, and 176, and may be referred to as a core material. The insulating layer 130 and the wiring layers L3 and L4 are collectively referred to as a core layer, and the insulating layers 142 and 148 and the wiring layers L2 and L1 are referred to as a buildup layer on the upper surface side of the substrate, and the insulating layers 162 and 168 are connected to the wiring. The layers L5 and L6 may be referred to as a buildup layer on the lower surface side of the substrate. The insulating layers 156 and 176 are solder resists.

  For example, the wiring layer L1 is used for forming signal lines and lands, the wiring layer L2 is used for forming signal lines, the wiring layer L3 is used for forming a ground (GND) plane, and the wiring layer L4 is a power source. The wiring layer L5 is used for forming signal lines and power planes, and the wiring layer L6 is used for forming terminals 190, lands 200, and power planes.

  Each of the wiring layers L1 to L6 has a predetermined conductive pattern. In the portion illustrated in FIG. 2, the wiring layers L1 to L6 include wirings 152, 146, 140, 160, 166, and 172, respectively.

  The wiring 152 of the wiring layer L1 is connected to the wiring 146 of the wiring layer L2 (more specifically, to the land portion of the wiring 146) through the through hole 150 provided in the insulating layer 148. The wiring 146 is connected to the wiring 140 of the wiring layer L3 through the through hole 144 of the insulating layer 142. Further, the wirings 140 and 160 of the wiring layers L3 and L4 are connected through a through hole 136 of the insulating layer 130 therebetween. The wiring 172 of the wiring layer L6 is connected to the wiring 166 of the wiring layer L5 through the through hole 170 of the insulating layer 168, and the wiring 166 of the wiring layer L5 is connected to the wiring layer through the through hole 164 of the insulating layer 162. It is connected to the wiring 160 of L4. Thereby, in the part illustrated in FIG. 2, the wiring 152 of the wiring layer L1 and the wiring 172 of the wiring layer L6 are electrically connected.

  Although the wiring layer L1 is not shown in FIG. 2, the wiring layer L1 has a land for flip chip mounting of the semiconductor chip 182 (see FIG. 1), and the insulating layer 156 is opened on the land. The land is connected to the wiring 152 of the wiring layer L1, for example.

  In the example of FIG. 2, the wiring layer L1 has lands 154 connected to the end portions of the wirings 152, whereby the lands 154 connect the wirings 152, the flip chip mounting lands, and the gold bumps 188. And is electrically connected to the semiconductor integrated circuit 180 (see FIG. 1). Note that the electrical connection between the land 154 and the flip-chip mounting land can also be made, for example, via the wiring of the wiring layer L2.

  An insulating layer 156 is opened on the land 154, and the ball electrode 110 of the upper package 52 is connected (bonded) to the land 154 through the opening. That is, the land 154 forms a pad electrode (or land electrode). Since the land 154 is provided on the substrate upper surface 122 (see FIG. 1) side, the land 154 is also referred to as an upper surface electrode 154 hereinafter.

  The wiring layer L6 includes a land 174, and the insulating layer 176 is opened on the land 174. The land 174 includes a structure in which the ball electrode 190 is bonded and a structure in which the ball electrode 190 is not provided and the land 200 is formed. As shown in FIG. 2, the land 200 having no ball electrode is connected to the end portion of the wiring 172, whereby the wirings 172, 166, 160, 140, 146, and 152 of the wiring layers L6 to L1 are connected. Are electrically connected to the upper surface electrode 154.

  Note that the number of wiring layers of the wiring boards 60 and 120 is not limited to the above example.

  Here, FIG. 3 illustrates a schematic plan view of the lower package 54 viewed from the substrate upper surface 122 side. Here, the case where both the wiring substrate 120 and the semiconductor chip 182 are substantially square in plan view is illustrated, but the shape is not limited thereto.

  In the illustration of FIG. 3, the semiconductor chip 182 is disposed at the center of the substrate upper surface 122, and a side that defines the outline of the semiconductor chip 182 (hereinafter referred to as a chip side) 184 is a side that outlines the wiring board 120 ( (Hereinafter referred to as the substrate side) 126 is arranged in a state of being substantially parallel to the substrate 126.

  A plurality of upper surface electrodes 154 are arranged outside the semiconductor integrated circuit 180 on the substrate upper surface 122, more specifically, in the peripheral region of the wiring substrate 120, and the entire circumference of the semiconductor integrated circuit 180 is formed in two rows. Is enclosed. Further, each of the two rows extends along the substrate side 126. In other words, these upper surface electrodes 154 are arranged in a land grid array (LGA) mode in which the central portion is hollow for the semiconductor integrated circuit 180. Note that the arrangement of the upper surface electrodes 154 is not limited to the above two rows.

  Here, since the upper surface electrode 154 is connected to the terminal 110 of the upper package 52 (see FIG. 1) as described above, the upper surface electrode 154 in FIG. It can also be grasped as an arrangement mode of the terminal 110 when viewed from the side (see FIG. 1).

  In order to distinguish the four substrate sides 126, reference numerals 126a, 126b, 126c, and 126d are used. These substrate sides 126a, 126b, 126c, and 126d are counterclockwise in this order in the top view of FIG. It is assumed that they are continuous (adjacent). Similarly, when distinguishing the four chip sides 184, reference numerals 184a, 184b, 184c, and 184d are used. At this time, the chip sides 184a, 184b, 184c, and 184d are assumed to be close to the substrate sides 126a, 126b, 126c, and 126d, respectively.

  At this time, a vertex (hereinafter referred to as a substrate vertex) 128ab of the wiring board 120 is configured as an intersection of the continuous substrate sides 126a and 126b. Similarly, a substrate vertex 128bc is configured by the intersection of the substrate sides 126b and 126c. The substrate vertex 128cd is configured by the sides 126c and 126d, and the substrate vertex 128da is configured by the substrate sides 126d and 126a. In addition, when not distinguishing each board | substrate vertex 128ab, 128bc, 128cd, 128da, the code | symbol 128 will be used.

  Similarly, a vertex (hereinafter referred to as a chip vertex) 186ab of the semiconductor chip 182 is configured by the intersection of the chip sides 184a and 184b, a chip vertex 186bc is configured by the chip sides 184b and 184c, and a chip vertex is formed by the chip sides 184c and 184d. 186cd is configured, and the chip apex 186da is configured by the chip sides 184d and 184a. In addition, when not distinguishing each chip | tip vertex 186ab, 186bc, 186cd, 186da, the code | symbol 186 will be used.

  FIG. 4 shows a schematic plan view of the configuration of the wiring substrate 120 on the substrate lower surface 124 side as seen through from the substrate upper surface 122 side. In FIG. 4, for easy understanding, the ball electrode 190 is indicated by a white circle, the land 200 is indicated by a black circle, and the semiconductor chip 182 is indicated by a one-dot chain line.

  In the example of FIG. 4, a plurality of ball electrodes 190 are arranged in a ball grid array (BGA) configuration parallel to each of two orthogonal substrate sides 126, and the central portion of the ball grid array Is hollow. The hollow area where the ball electrode 190 is not disposed corresponds to the central portion of the semiconductor chip 182, and the arrangement range of the ball electrode 190 (or the group of ball electrodes 190) straddles the position of each chip side 184 (see FIG. 3). The semiconductor chip 182 extends inside and outside. That is, the arrangement range of the plurality of ball electrodes 190 is wider than the outer dimension of the semiconductor chip 182. The arrangement of the ball electrodes 190 extends to the vicinity of each substrate side 126.

  Lands 200 are arranged outside the outermost periphery of the array of ball electrodes 190, more specifically, in the peripheral region of the wiring board 120. In the example of FIG. 4, one row of lands 200 surrounds the entire circumference of the group of ball electrodes 190 along the substrate side 126. The lands 200 are aligned on the extension of the BGA array by the ball electrodes 190. For this reason, the BGA array by the ball electrodes 190 is a grid array (lattice dot array) in which the LGA array by the lands 200 is surrounded. Yes.

  The total number (725) of ball electrodes 190 and lands 200 provided on the lower surface 124 of the wiring board 120 is larger than the number of upper surface electrodes (lands) 154, that is, the number of ball electrodes 110 of the upper semiconductor package 52 (160). . The arrangement pitch of the plurality of ball electrodes 190 (the distance between the centers of the two ball electrodes 190 adjacent in the vertical direction and the horizontal direction along the substrate side 126) is the same as that of the plurality of ball electrodes 110 of the upper semiconductor package 52. It is smaller than the arrangement pitch. For example, the pitch of the ball electrodes 190 is about 0.5 mm, and the pitch of the ball electrodes 110 is about 0.65 mm.

  As can be seen from FIGS. 1 to 4, the land 200 is close to the upper surface electrode 154 in the thickness direction of the wiring board 120. In the example shown in the drawing, the above-described proximity arrangement is realized by the arrangement area of the lands 200 and the arrangement area of the upper surface electrodes 154 (here, the arrangement areas for two rows) facing each other in the substrate thickness direction.

  Here, in the present embodiment, a memory chip, more specifically, a mobile DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) is exemplified as the semiconductor chips 92a and 92b of the upper package 52. As an international standard for DDR-SDRAM, for example, the JEDEC standard (JEDEC STANDARD) is known, and according to this standard, standards for terminal arrangement, terminal function, operation mode, and the like are standardized.

  Further, as the semiconductor chip 182 of the lower package 54, that is, the semiconductor integrated circuit 180, a logic chip (in other words, a microcomputer) having a function of controlling the two DDR-SDRAMs is exemplified. The microcomputer can be configured as, for example, an SOC (System On Chip).

  In the following description, the semiconductor chips 92a and 92b are also referred to as SDRAMs 92a and 92b, and the semiconductor chip 182 (in other words, the semiconductor device 180) is also referred to as the SOC 182.

  FIG. 5 is a block diagram outlining the stacked semiconductor device 50 in this example. As illustrated in FIG. 5, the SOC 182 includes a core circuit unit 300, an interface (I / F) unit 305 and memory I / F units 310 a and 310 b connected to the core circuit unit 300. The SDRAM 92 a includes an I / F unit 380 and a memory cell unit (having a control unit) 390 connected to the I / F unit 380.

  The core circuit unit 300 of the SOC 182 includes, for example, a central processing unit (CPU), a memory that stores a program executed by the central processing unit and provides a work area, and a memory controller that controls the memory I / F units 310a and 310b. Thus, various calculations, processing, control, and the like are performed. Here, a configuration in which one core circuit unit 300 is provided for two memory I / F units 310a and 310b is illustrated, but a core circuit unit 300 may be provided for each I / F unit 310a and 310b. It is. The I / F unit 305 is an I / F through which the core circuit unit 300 transmits and receives a signal such as data with an external device, and is connected to the core circuit unit 300 and the terminal 190.

  The memory I / F unit 310a of the SOC 182 is connected to the I / F unit 380 of the SDRAM 92a via the wiring 350. A wiring 350 connecting the SOC 182 and the SDRAM 92 a is branched in the middle, and the branched wiring 358 is connected to the terminal 190 or the land 200.

  Here, the wirings 350 and 358 are signal transmission wirings, that is, signal lines, and the signal line 358 drawn from the signal line 350 to the terminal 190 or the land 200 is called a signal lead-out line. In the signal line 350, a portion from the SOC 182 to the connection point (or branch point) 354 of the signal lines 350 and 358 is called a signal line 352, and a portion from the connection point 354 to the SDRAM 92a is called a signal line 356. .

  At this time, referring to FIG. 1 and FIG. 2 in addition to FIG. 5, the signal line 352 corresponds to a path (wiring path, conductive path) including the gold bump 188 and the wiring 152 of the wiring board 120. The signal line 356 corresponds to a path including the ball electrode 110, the wirings 80 and 84 of the wiring board 60, and the bonding wire 98, and the signal lead-out line 358 is the wirings 152, 146, 140, 160, of the wiring board 120. 166 and 172. Further, the wiring connection point 354 corresponds to the upper surface electrode 154 of the wiring board 120.

  On the other hand, the other SDRAM 92b is not shown in FIG. 5, but has the same configuration as the SDRAM 92a. Further, the SDRAM 92b is connected to the I / F unit 310b of the SOC 182 and also connected to the terminal 190 or the land 200 in the same manner as the SDRAM 92a.

  Further, as illustrated in FIG. 5, the semiconductor device 50 includes a ground voltage VSS as a low-potential-side power supply voltage and power-supply voltages VCCQa, VCCQb, VCCMA, VCCMb, VCC, and VCCQc as high-potential-side power supply voltages. Each is supplied via a terminal 190. The voltages VCCQa, VCCQb, VCCMA, VCCMb, VCC, and VCCQc correspond to the so-called VDD voltage of the voltage supply destination circuit, and are supplied by electrically separated wirings in the semiconductor device 50, respectively.

  Specifically, the ground voltage VSS is supplied to the SOC 182 and the SDRAMs 92a and 92b via a wiring forming a ground line.

  In the SOC 182, the power supply voltage VCCQa is supplied to the I / F unit 310 a through the wiring that forms the power supply line. Similarly, the power supply voltage VCCQb is supplied to the I / F unit 310 b, and the core circuit unit 300 is supplied to the core circuit unit 300. The power supply voltage VCC is supplied, and the power supply voltage VCCQc is supplied to the I / F unit 305.

  In SDRAM 92a, power supply voltage VCCMA is supplied to I / F unit 380 and memory cell unit 390. Note that the power supply lines of the I / F unit 380 and the memory cell unit 390 are connected inside the package, for example, on the wiring board 60, and the power supply voltage VCCMa is applied to the common power supply line from the outside of the package. Similarly, the power supply voltage VCCMb is supplied to the SDRAM 92b.

  According to this power supply configuration, since the terminals 190 are provided for the power supply voltages VCCQa, VCCQb, VCCMA, VCCMb, VCC, VCCQc as described above, the core circuit unit 300 and the I / F unit 305 of the SOC 182 Power supply voltages can be independently supplied to the 310a and 310b and the I / F units 380 of the SDRAMs 92a and 92b.

  Note that the voltages VCCQa, VCCQb, VCCMA, and VCCMb are the same (for example, 1.8V), and the voltage value of the voltage VCC is lower than the voltages VCCQa, VCCQb, VCCMA, and VCCMb (for example, 1.0V to 1.2V). ), The voltage value of the voltage VCCQc is different from the voltage VCC and / or the voltages VCCQa, VCCQb, VCCMA, and VCCMb (in either case of high or low).

  FIG. 6 is a plan view illustrating the function assignment of each terminal 190 and each land 200 of the lower package 54, and FIG. 7 is a plan view illustrating the function assignment of each upper surface electrode 154 of the lower package 54. 6 and 7, each terminal and the like is schematically represented by a square grid. In FIG. 6, the land 200 is represented by a thick grid (all outermost grids and innermost grids Y-10 to Y-13). Reference). Note that the contact of the meshes in the drawing does not mean electrical connection between adjacent terminals or the like. In addition, in order to make the position of each cell easy to understand, numerals and alphabets are written on the outer periphery of the drawing for convenience.

  In FIG. 6 and FIG. 7, the assigned functions, in other words, the types of signals and the like are represented by various symbols in the above-described cells. Further, various black symbols indicate signals for the SDRAM 92a, and indicate white signals for the SDRAM 92b.

  In each SDRAM 92a and 92b, data input / output with respect to the SOC 182, that is, data writing / reading, is performed according to a clock signal, an address / command signal, and a data input / output control signal. At this time, data is input / output in the SOC 182 (see FIG. 5) via the I / F units 310a and 310b (see FIG. 5), and the clock system signal, the address / command system signal, and the data input / output control signal. Is generated by the SOC 182 (see FIG. 5) and output from the I / F units 310a and 310b (see FIG. 5).

  These clock signal, address / command signal, data input / output control signal, and data (data signal) are internal signals transmitted between the SOC 182 and the SDRAMs 92a and 92b via the signal line 350. The generic term for the data input / output control signal and the data signal is referred to as a data system signal.

  Here, the clock signals include differential clock signals (CK, CK #). It should be noted that the signal with “#” indicates that it is a low-active signal, and this notation method will be used in the following. 6 and 7, the clock signals are indicated by circle symbols, and in each of FIGS. 6 and 7, there are two black circle symbols (for SDRAM 92a) and white circle symbols (for SDRAM 92b). CK and CK #) are shown.

  The address / command system signal includes an address system signal and a command system signal. Here, the former address system signal includes an address signal (A), a bank address signal (BA), and the like, and the latter command system signal includes a row address strobe signal (RAS #) and a column address strobe signal (CAS #). ), A write enable signal (WE #), a clock enable signal (CKE), a chip selection signal (CS #), and the like. 6 and 7, the address / command signals are indicated by square symbols. In each of FIGS. 6 and 7, black square symbols (for SDRAM 92a) and white square symbols (for SDRAM 92b) are respectively shown. 16 (address signal: A0 to A13, bank address signal: BA0 to BA1, row address strobe signal: RAS #, column address strobe signal: CAS #, write enable signal: WE #, clock enable signal: CKEA, CKEB, chip Selection signals: CSA, CSB) are shown.

  Here, the data input / output control signal includes a data strobe signal (DQS, DQS #), a data mask signal (DM), and the like. 6 and 7, data system signals that collectively refer to the data input / output control signal and the data signal (DQ) are indicated by triangle symbols. In each of FIGS. 6 and 7, black triangle symbols (for SDRAM 92 a) are shown. And 40 white triangle symbols (for SDRAM 92b) (data signals: DQ0 to DQ31, data strobe signals: DQS0 to DQS3, data mask signals: DM0 to DM3) are illustrated.

  6 and 7, the rhombus symbols indicate that the power supply voltages VCCQa and VCCQb (see FIG. 5) of the SOC 182 are assigned. In FIG. 6, black rhombus symbols (for SDRAM 92a) and white diamond symbols ( 12 for the SDRAM 92b). 6 and 7, the star symbols indicate the power supply voltages VCCMA and VCCMb (see FIG. 5) of the SDRAMs 92a and 92b. In each of FIGS. 6 and 7, black star symbols (for the SDRAM 92a) and Eight white star symbols (for SDRAM 92b) are illustrated. 6 and FIG. 7, the asterisk symbol represents the ground voltage VSS (see FIG. 5).

  6 are terminals for signals exchanged between an external device and the SOC 182, power supply voltages for the core circuit unit 300 of the SOC 182, and other power supply voltages for the IF unit 305. It is.

  As illustrated in FIG. 6, the data system signal indicated by the triangle symbol and a part of the address / command system signal indicated by the square symbol are extracted to the land 200. That is, a signal lead line 358 is provided for each of these signal paths. Examples of the address / command system signal extracted to the land 200 include an address signal, a bank address signal, a row address strobe signal, and a column address strobe signal. On the other hand, as an address / command system signal (see grids C-26 to F-26, D-25, AE-8, AE-7, AD-6 to AD-4 in FIG. 6) connected to the terminal 190, Of the system signals, a clock enable signal, a chip selection signal, and a write enable signal are exemplified. Further, according to the example of FIG. 6, the clock signal indicated by a circle symbol is assigned to the terminal 190.

  A terminal 190 (ball electrode 190) to which a clock enable signal, a chip selection signal, a write enable signal, and a clock system signal are connected is joined to a land of the mounting board 56 (see FIG. 1). It is not connected to this wiring and is in a floating state. Note that at least a part of the ball electrode 190 connected to the clock enable signal, the chip selection signal, the write enable signal, and the clock signal can be replaced with the land 200. In this case, a plurality of lands 200 are also provided in the array of ball electrodes 190.

  In the above example, since the number of the outermost lands 200 is limited, some signals are drawn out to the ball electrode 190. In other words, if the number of outermost lands 200 is equal to or greater than the total number of data-related signals and address / command-related signals, all of the data-related signals and address / command-related signals can be extracted to the lands 200. is there. If the number of outermost lands 200 is smaller than the total number of data system signals and address / command system signals as shown in the above example, the priority assigned to the land 200 is set to the highest data system signal, and then the address It is preferable to set the system signal to the second highest and the command system signal to the third. According to such prioritization, it is possible to monitor the signal having a high usefulness in the land 200 in the inspection and analysis described later.

  Further, according to the example of FIG. 6, the power supply voltages VCCQa, VCCQb, VCCMa, VCCMb, and VSS are assigned to the terminal 190.

  According to the above configuration, an internal signal transmitted between the SOC 182 and the SDRAMs 92a and 92b via the signal line 350 can be extracted to the land 200, that is, outside the package, by the signal extraction line 358. As a result, the signal drawn out to the land 200 can be monitored and the semiconductor device 50 can be inspected and analyzed. In this respect, the land 200 may be called a signal monitoring terminal (or electrode). When each of the electrodes 190 and 200 is referred to as a lower surface electrode, the above-described configuration can be expressed as the outermost lower surface electrode 200 including a land in an array of a plurality of lower surface electrodes.

  Further, since the upper surface electrode 154 and the land 200 are disposed close to each other at the periphery of the substrate, the signal extraction is performed as compared with the configuration in which the land 200 is disposed on the center side of the substrate, that is, the inner side (inner peripheral side) of the arrangement of the terminals 190. Line 358 can be shortened. For this reason, signal reflection by the signal lead-out line 358 can be suppressed and signal quality can be improved.

  Further, according to the above configuration, the terminal 110 and the signal lead-out line 358 of the upper package 52 are connected to the signal line 352 of the wiring board 120 at the upper surface electrode 154. For this reason, compared with the configuration in which the signal lead-out line 358 is connected to the signal line 352 at a position away from the upper surface electrode 154, the number of electrical connection points that can cause signal reflection can be reduced. Thereby, the signal quality can be improved.

  In general, the reflection of the signal increases as the signal frequency increases. However, according to the semiconductor device 50, the speed of the signal can be increased with the reflection suppression effect.

  Further, since the land 200 is arranged outside the arrangement of the terminals 190, it is possible to prevent the wiring structure from the upper surface electrode 154 to the land 200 via the signal lead-out line 358 from being mixed with other wiring structures. . For this reason, the wiring structure of the wiring board 120 can be simplified as a whole. As a result, it is possible to reduce the size of the semiconductor device 50 by reducing the area of the wiring substrate 120 and the wiring layer.

  Further, according to the above configuration, when electrolytic plating is performed on the upper surface electrode 154, the use of the land 200 facilitates wiring of the plated wire. That is, since the wiring layer L1 on which the upper surface electrode 154 exists has a high wiring density due to the wiring connected to the semiconductor chip 182, it may be difficult to dispose the plating wire on the wiring layer L1. Further, when the land 200 is arranged on the inner side of the arrangement of the terminals 190, the plating wire must be arranged avoiding the terminals 190 and the like, and the distance to the substrate side 126 becomes long. On the other hand, according to the above configuration in which the land 200 electrically connected to the upper surface electrode 154 is disposed outside the terminal 190, wiring in the wiring board 120 can be easily avoided from the land 200 to the side of the board. A plated wire can be drawn out to 126.

  Note that the opening on the land 200 may be closed before the semiconductor device 50 is mounted on the mounting substrate 56 (see FIG. 1) after the inspection using the land 200 is completed. Such an opening can be closed by, for example, applying an insulating resin on the land 200, or by applying an insulating sheet, for example. By covering the land 200 with the insulating member in this manner, it is possible to prevent the land 200 and the wiring of the mounting substrate 56 from being short-circuited through, for example, foreign matter.

  Further, a ball electrode made of a solder ball may be provided on the land 200 to have a structure similar to that of the ball electrode 190 (terminal 190). In this case, the ball electrode on the land 200 is bonded to the land of the mounting substrate 56 (see FIG. 1), but the land is not connected to the wiring in the mounting substrate 56 and is in a floating state.

  Here, the arrangement of the upper surface electrode 154 illustrated in FIG. 7 will be further described with reference to FIG. FIG. 8 is a plan view corresponding to FIG. 3, but each upper surface electrode 154 is indicated by the symbol used in FIG. 7 (the electrode 154 is not formed in the shape of each symbol). In FIG. 8, electrodes 154 to which a clock signal, a data signal, and an address / command signal are assigned are extracted and shown.

  As illustrated in FIG. 8, the memory I / F unit 310a of the SOC 182 is provided at a corner near the chip apex 186ab (hereinafter referred to as a chip corner), and the chip sides that constitute the chip corner 184a and 184b. Another memory I / F unit 310b is provided at a chip corner near the chip apex 186cd at the diagonal position of the chip apex 186ab, and extends over the chip sides 184c and 184d constituting the chip corner. ing.

  The I / F unit 310a is along the substrate sides 126a and 126b adjacent to the I / F unit 310a, in other words, the substrate sides 126a and 126b adjacent to the chip sides 184a and 184b on which the I / F unit 310a is provided. Are connected to an upper surface electrode 154 (shown by a black symbol). Note that the upper surface electrode 154 connected to the I / F unit 310a is collectively referred to as an upper surface electrode group 410a. Similarly, the other I / F unit 310b includes an upper surface electrode 154 (illustrated by white symbols) arranged along the substrate sides 126a and 126b adjacent to the I / F unit 310b. (Referred to as electrode group 410b).

  In FIG. 8, wirings 352 (see FIG. 5) that connect the I / F portions 310a and 310b and the upper surface electrodes 154 are schematically illustrated by arrows in order to avoid complication of the drawing.

  Here, if the I / F unit 310a is concentrated only on the chip side 184b, the electrode group 410a extends not only to the substrate side 126b but also to the substrate sides 126a and 126c. In this case, in order to connect the I / F unit 310a and the electrodes 154 of the substrate sides 126a and 126c, the semiconductor chip 182 is bypassed, and specifically, the wiring configuration is such that the outside of the chip apexes 186ab and 186bc is bent and passes. There must be.

  On the other hand, according to the above arrangement illustrated in FIG. 8 with respect to the I / F portions 310a and 310b and the electrode groups 410a and 410b, the wiring that connects the I / F portions 310a and 310b and the electrode groups 410a and 410b is made of a semiconductor. The chip 182 (semiconductor integrated circuit 180) can be wired without detouring. For this reason, signal quality can be improved by shortening wiring.

  FIG. 9 shows a more detailed view of FIG.

  In the example of FIG. 9, the I / F unit 310a of the SOC 182 includes a clock system I / F unit 311a that outputs a clock system signal and a data system I / F unit (two I / F units) that input and output data system signals. And an address / command system I / F section (divided into two I / F sections 315a and 316a) for outputting an address / command system signal.

  The data system I / F unit 313a and the address / command system I / F unit 315a are provided on the chip side 184a, and the data system I / F unit 313a is more than the address / command system I / F unit 315a. It is located on the side close to the chip apex 186ab. The clock system I / F unit 311a, the data system I / F unit 314a, and the address / command system I / F unit 316a are provided on the chip side 184b. The clock system I / F unit 311a is located closer to the chip apex 186ab than the I / F units 314a and 316a, and the data system I / F unit 314a is more than the address / command system I / F unit 316a. It is located on the side close to the chip apex 186ab. At this time, the clock system I / F unit 311a is arranged between the data system I / F units 313a and 314a in the continuous chip sides 184a and 184b.

  The upper electrode group 410a to which the I / F unit 310a is connected includes a clock system electrode group 411a connected to the clock system I / F unit 311a and data system electrodes connected to the data system I / F units 313a and 314a. A group (divided into two electrode groups 413a and 414a) and address / command system electrode groups 415a and 416a connected to the address / command system I / F units 315a and 316a. In addition, the upper surface electrode 154 belonging to each electrode group 411a, 413a-416a is collected in the predetermined site | part demonstrated below.

  The clock system electrode group 411a is disposed in the vicinity of the clock system I / F unit 311a. In the example of FIG. 9, the substrate side 126b facing the chip side 184b on which the connected clock system I / F unit 311a is disposed. Is provided. The data system electrode group 413a is provided on the substrate side 126a, and the data system electrode group 414a is provided on the substrate side 126b from the vicinity of the substrate vertex 128ab. Address / command system electrode groups 415a and 416a are provided on substrate sides 126a and 126b, respectively. At this time, the data system electrode groups 413a and 414a are located closer to the substrate vertex 128ab than the address / command system electrode groups 415a and 416a.

  On the other hand, the I / F unit 310b of the SOC 182 includes a clock system I / F unit 311b, a data system I / F unit (divided into two I / F units 313b and 314b), and an address / command system I / F. F section (divided into two I / F sections 315b and 316b).

  The clock system I / F unit 311b, the data system I / F unit 313b, and the address / command system I / F unit 315b are provided on the chip side 184c. The clock system I / F unit 311b is located closer to the chip vertex 186cd than the I / F units 313b and 315b, and the data system I / F unit 313b is more than the address / command system I / F unit 315b. It is located on the side close to the chip apex 186cd. The data system I / F unit 314b and the address / command system I / F unit 316b are provided on the chip side 184d, and the data system I / F unit 314b is the address / command system I / F unit 316b. It is located closer to the chip apex 186cd. At this time, the clock system I / F unit 311b is arranged between the data system I / F units 313b and 314b in the continuous chip sides 184c and 184d.

  The upper surface electrode group 410b to which the I / F unit 310b is connected includes a clock system electrode group 411b connected to the clock system I / F unit 311b and data system electrodes connected to the data system I / F units 313b and 314b. A group (divided into two electrode groups 413b and 414b) and address / command system electrode groups 415b and 416b connected to the address / command system I / F units 315b and 316b.

  The clock system electrode group 411b is disposed in the vicinity of the clock system I / F unit 311b. In the example of FIG. 9, the substrate side 126c facing the chip side 184c on which the clock system I / F unit 311b to be connected is disposed. Is provided. The data system electrode groups 413b and 414b are provided on the substrate sides 126c and 126d, respectively, and the address / command system electrode groups 415b and 416b are provided on the substrate sides 126c and 126d, respectively. At this time, the data electrode groups 413b and 414b are located closer to the substrate vertex 128cd than the address / command electrode groups 415b and 416b.

  In FIG. 9, wiring 352 (see FIG. 5) for connecting the I / F portions 311a, 313a to 316a, 311b, 313b to 316b and the respective upper surface electrodes 154 is schematically shown by arrows in order to avoid complication of the drawing. It is shown in the figure.

  Here, since the upper surface electrode 154 is larger than the pads (not shown) of the I / F portions 311a and 313a to 316a in the semiconductor chip 182, the I / F portions 311a and 313a to 316a are corners near the chip apex 186ab. The corresponding electrode groups 411a and 413a to 416a are spread over the substrate sides 126a and 126b.

  Therefore, according to the above configuration, the data system I / F is more than the wiring (address / command system wiring) connecting the address / command system I / F units 315a and 316a and the address / command system electrode groups 415a and 416a. It is possible to shorten the wiring (data wiring) for connecting the portions 313a and 314a and the data system electrode groups 413a and 414a.

  In general, in a DDR-SDRAM, a data system signal is transmitted in synchronization with the rise and fall of a clock signal, whereas an address / command system signal is transmitted in synchronization with only the rise (or fall) of a clock signal. Therefore, the data system signal has a higher signal speed than the address / command system signal (ie, the signal level transition period unit is short, in other words, the operating frequency is high). For this reason, according to the said structure, the wiring which transmits a high-speed signal can be shortened and signal quality can be improved. In general, the data system signal and the clock system signal have the same signal speed.

  Further, according to the above configuration, since the clock system I / F unit 311a is connected to the clock system electrode group 411a arranged in proximity, the wiring that connects the clock system I / F unit 311a and the clock system electrode group 411a. The (clock system wiring) can be made shorter than the address / command system wiring and the data system wiring.

  In general, in an SDRAM or the like, an address / command system signal is output based on the timing of a clock system signal, and a data strobe signal is generated based on a clock system signal. For this reason, the clock signal plays a more fundamental role in operation than the address / command signal and the data signal. For this reason, according to the said structure, the wiring which transmits the signal with a high fundamental role can be shortened, and signal quality can be improved.

  Such an improvement in signal quality can also be obtained by the arrangement form of the I / F units 311b and 313b to 316b and the electrode groups 411b and 413b to 416b.

  In addition, since the wiring length difference is reduced (wiring length is uniform) as the wiring is shortened, the signal delay difference, that is, the signal timing difference is reduced, and the signal quality can be made uniform. As a result, operation reliability is improved.

  In the above description, the I / F portion of the semiconductor chip 182 is not limited to the above two (310a, 310b). That is, if the semiconductor chip 182 is a quadrangle, there are four chip corners, so that up to four I / F parts can be provided. Further, if the semiconductor chip 182 is a pentagon or more polygon, it is possible to provide five or more I / F portions. In addition, the semiconductor integrated circuit 180 can also be constituted by a plurality of semiconductor chips, and in this case, more chip corners are provided as I / F portion arrangement locations. The plurality of semiconductor chips may be stacked, or each may be disposed on the upper surface 122 of the substrate.

  FIG. 10 illustrates a circuit diagram outlining the power supply system of the semiconductor device 50. In the example of FIG. 10, the output terminal of the output buffer 312a provided in the I / F unit 310a of the SOC 182 (see FIG. 5) and the input buffer 382a provided in the I / F unit 380 of the SDRAM 92a (see FIG. 5). The input terminal is connected by a signal line 350. As a result, various signals such as clock signals are transmitted from the output buffer 312a to the input buffer 382a.

  The output buffer 312a is connected to the terminal 190 of the ground voltage VSS through the wiring 500 forming the ground line, and is connected to the terminal 190 of the power supply voltage VCCQa through the wiring 600 forming the power supply line. Similarly, the input buffer 382 is connected to the terminal 190 of the ground voltage VSS through the wiring 520 and is connected to the terminal 190 of the power supply voltage VCCMa through the wiring 620.

  When the wiring 350 between the buffers 312a and 382 is charged / discharged, for example, a signal output from the output terminal of the output buffer 312a transitions between a high level (H level) and a low level (L level). In this case, a return current (feedback current) flows as schematically shown by arrows A and B in FIG.

  Specifically, a current (discharge current) due to the discharge of the charge of the wiring 350 between the buffers 312a and 382 flows through the path 540 connected between the wirings 500 and 520 as a return path (feedback current path) ( (See arrow A in FIG. 10). On the other hand, a current (charging current) due to the charging of the wiring 350 between the buffers 312a and 382 flows through a path 640 connected between the wirings 600 and 620 as a return path (see arrow B in FIG. 10).

  By providing the paths 540 and 640 as return paths, the charging / discharging is performed more quickly. As a result, the signal level transition becomes steep, thereby improving the signal quality and speeding up.

  The discharge return path 540 can be configured using, for example, a ground plane provided in the wiring layer L3 (see FIG. 2). Specifically, by forming the wirings 500 and 520 via the same ground plane in the wiring substrate 120 (see FIG. 2), it is possible to provide a return path 540 using a ground plane between the wirings 500 and 520. is there. According to the planar ground plane, the impedance of the return path 540 can be made lower than that of the linear wiring, so that the discharge can be performed more quickly, and the improvement in signal quality and the speeding up can be further promoted. .

  The charging return path 640 can be configured using, for example, a power plane provided in the wiring layer L4 (see FIG. 2). According to the planar power plane, like the above-described ground plane, the impedance of the return path 640 can be reduced to further improve signal quality and speed.

  Here, in addition to FIG. 10, the charging return path 640 will be described with reference to a cross-sectional view of the semiconductor device 50 illustrated in FIG. 11. For the sake of explanation, FIG. 11 shows a state in which the semiconductor device 50 is mounted on the mounting substrate 56.

  As described above, the power supply voltages VCCQa and VCCMA are assigned to different terminals 190 to enable independent supply (see FIGS. 5 and 6). For this reason, if the wirings 600 and 620 are connected to the same power supply plane in the wiring board 120, such voltage independent supply cannot be ensured.

  In view of this point, in the semiconductor device 50, the charging return path 640 is configured using the path 642 by the power plane in the wiring board 120 and the wiring 644 of the mounting board 56. Specifically, the power plane constituting the path 642 is connected to the wiring 600 of the power supply voltage VCCQa and a predetermined terminal 190, and the predetermined terminal 190 and the terminal 190 of the power supply voltage VCCMA are connected to the wiring 644 of the mounting board 56. is doing.

  10 and 11, a bypass capacitor 646 is inserted in the wiring 644 of the mounting substrate 56. The bypass capacitor 646 is mounted on the mounting board 56 as illustrated in FIG. By bypass capacitor 646, power supply voltages VCCQa and VCCMA can be short-circuited in an alternating current while being separated in a direct current manner. That is, it is possible to ensure both the independent supply of the DC voltages VCCQa and VCCMA and the formation of the return path 640 in the high frequency region during charging.

  In the example of FIG. 11, the wiring 600 of the power supply voltage VCCQa includes the gold bump 188 and the wiring 602 of the wiring board 120, and the wiring 620 of the power supply voltage VCCMa is the wiring 622 of the wiring board 120 and the upper surface electrode 154. And the terminal 110, the wiring 624 in the wiring substrate 60, and the bonding wire 98. The wirings in the substrates 60, 120, and 56 are simply illustrated in FIG. 11, but are configured by connecting predetermined conductive patterns in each wiring layer in the same manner as illustrated in FIG.

  As shown in the circuit diagram of FIG. 12 and the cross-sectional view of FIG. 13, the bypass capacitor 646 in the wiring 644 may be removed from the configuration of FIG. 10 and FIG. In the above description, the connection portion between the output buffer 312a of the I / F unit 310a of the SOC 182 and the input buffer 382a of the I / F unit 380 of the SDRAM 92a is illustrated, but the input buffer and the I / F unit 380 of the I / F unit 310a are illustrated. The connection portion with the output buffer can be similarly configured. The connection portion between the I / F unit 310b of the SOC 182 and the SDRAM 92b can be similarly configured.

  Here, the structure of the wiring board 120 of the lower package 54 will be described with reference to schematic plan views of FIGS. 14 to 17. FIGS. 14 and 15 are plan views similar to FIGS. 3 and 4, except that the upper surface electrode 154 and the terminal 190 for the power sources VCCMA, VCCMb, VCCQa, and VCCQb are indicated by symbols used in FIG. 6 and the like. In FIG. 14, the upper surface electrode 154 for the power source VSS is also indicated by a symbol. FIG. 16 is a plan view in which FIGS. 14 and 15 are overlapped, and an upper surface electrode 154 and a terminal 190 for power supply are extracted and shown. FIG. 17 is a plan view similar to FIG. 15, in which a power supply terminal 190 is extracted and illustrated.

  14 to 16, the upper surface electrode 154 for the power source VCCMA supplied to the upper package 52 is provided on the outermost periphery closest to the substrate side 126, as indicated by the black star, and the terminal for the power source VCCMA 190 is arranged in the range of 1 to 3 rows counting from the outermost periphery of the arrangement of the terminals 190. Further, the power supply VCCMA terminal 190 is arranged within a range in which the arrangement length of about 3 to 4 terminals 190 is set to have a radius immediately below the upper surface electrode 154 for the power supply VCCMA. This arrangement relationship is the same for the upper surface electrode 154 for the power supply VCCMb supplied to the upper package 52 and the terminal 190 (indicated by a white star).

  The arrangement relationship will be described with reference to FIGS. Taking the upper surface electrode 154 for the power source VCCMA of the grid AA-22 in FIG. 7 as an example, an area AR122 in a range of two pitches (two grids) in the vertical and horizontal directions around the electrode 154 is shown in FIG. When projected onto 124, area AR124 corresponds. The projection area AR124 is a range including grids AE-29 to AJ-29, AE-28 to AJ-28, AE-27 to AJ-27, and AE-26 to AJ-26 in view of the arrangement pitch illustrated above. It is. The sand hatching in FIGS. 6 and 7 is given to make the areas AR124 and AR122 easier to understand. As can be seen from FIGS. 6 and 7, the power supply VCCMA terminal 190 is disposed in the area AR124 corresponding to (opposed to) the area AR122 centered on the power supply VCCMA upper surface electrode 154 (grid AF-28, AF). -27). The same applies to the other upper surface electrodes 154 and the terminals 190 for the power source VCCMA, and the same applies to the upper surface electrodes 154 and the terminals 190 for the power source VCCMb.

  Here, the arrangement relationship between the upper electrode 154 of the data system signal (illustrated by a triangle symbol) and the terminal 190 will be described using the same area as the above-mentioned areas AR122 and AR124. The electrode 154 is connected to the land 200 in the region of the substrate lower surface 124 corresponding to the region having a pitch larger than the above-described two pitches (for example, six pitches) with respect to the power sources VCCMA and VCCMb. The arrangement relationship between the data system signal upper surface electrode 154 and the data system signal land 200 is applicable to all data system signals (DQ, DQS, DM).

  Further, in the wiring board 120, the plurality of power supply VCCMA upper surface electrodes 154 and the plurality of power supply VCCMA terminals 190 are connected to the same power supply plane, so that each power supply VCCMA upper surface electrode 154 and the plurality of power supply VCCMA terminals 190 are connected. There are a plurality of power supply paths between the two. At this time, the plurality of power supply paths include the shortest path. For example, the power supply path between the upper surface electrode 154 of the grid AA-22 in FIG. 7 and the terminal 190 of the grid AF-28 in FIG. 6 is the shortest.

  At this time, according to the arrangement relationship between the upper surface electrode 154, the terminal 190, and the land 200, the shortest power supply path for each of the upper surface electrodes 154 for the power source VCCMA is the upper surface electrode 154 for data system signals on the wiring board 120. Among the wiring paths connecting the lands 200 and the lands 200 (corresponding to the signal lead lines 358), the length is shorter than the longest wiring path. Note that the upper electrode 154 for data signals and the land 200 are connected one-to-one on the wiring board 120 and have the wiring path therebetween. The number of wiring paths related to the data system signals is the same as the number of data system signals in the wiring board 120 (40 for each of the SDRAM 92a and the white SDRAM 92b in the above example). The above relationship between the shortest power supply path and the longest wiring path is the same for each upper surface electrode 154 for the power supply VCCMb.

  By connecting the upper surface electrode 154 and the terminal 190 that are arranged close to each other in this manner, the wiring 622 (see FIG. 10) for the power supply VCCMA and VCCMb can be shortened. As a result, the impedance of the power supply line 622 (see FIG. 10), in other words, a voltage drop caused by the power supply line 622 can be reduced. In other words, the power supply capability can be increased.

  Further, regarding the lowering of the impedance of the power supply line, in the upper package 52 (see FIG. 10), the terminal 110 connected to the upper surface electrode 154 for the power supply VCCMa and VCCMb and the input terminals for the power supplies VCCMA and VCCMb of the SDRAMs 92a and 92b. It is also preferable to shorten the path between them (consisting of the wiring 624 and the bonding wire 98 in the wiring board 60).

  For example, the terminal 110, the path, and the input ends of the SDRAMs 92 a and 92 b are arranged in a substantially normal direction of the outer edge of the upper package 52, that is, the substrate side of the wiring board 60 in the plan view of the upper package 52 (wiring board 60). It is possible to make the route shortest by arranging them in a line.

  For reducing the impedance of the return path 640, it is more effective to use a planar power plane than the linear wiring as described above. In view of this point, it is preferable that the terminal 190 for the return path 640 connected via the wiring 644 of the mounting substrate 56 and the terminal 190 for the power source VCCMa and VCCMb are arranged adjacent to the terminal 190 for the power source VCCMA and VCCMb. This is because the ratio of the path 642 by the power plane in the return path 640 can be increased.

  FIG. 17 schematically shows a power supply plane for the path 642. In FIG. 17, the semiconductor chip 182 is shown with a one-dot chain line for explanation.

  According to the illustration of FIG. 17, the power plane for the path 642 extends so as to include the supply terminal 190 and the return path terminal 190 for the power supplies VCCQa and VCCQb, but the power supply VCCMA not directly connected to the power supply plane. , VCCCMb terminal 190 and wiring 622 (see FIG. 11) are arranged.

  Further, as illustrated in FIGS. 17 and 11, the power supply plane for the path 642 extends below the power supply VCCQa and VCCQb input ends of the semiconductor chip 182. For this reason, the wiring 600 for the power supply VCCQa and VCCQb is formed from the input end of the semiconductor chip 182 to the terminal 190 immediately below or near the input end, thereby shortening (and minimizing) the wiring 600. It is possible to connect to the power plane for the path 642 in the middle of the wiring.

  In FIG. 11 and the like, the outermost upper surface electrode 154 is illustrated as the power source VCCMA and VCCMb electrode 154, but the second uppermost electrode 154 from the outermost periphery may be used for the power sources VCCMA and VCCMb. Further, it is possible to supply the power supply voltages VCCQa and VCCQb from the return terminal 190.

  Note that the relationship between the upper electrode 154 and the terminal 190 for power supply and the upper electrode 154 and the land 200 for data signals is that the clock signal (CK, CK #) is sent from the outside of the package of the semiconductor device 50 to the SDRAM 92a of the upper package 52. , 92b can also be applied. Specifically, the wiring board 120 includes a plurality of clock supply paths for connecting the plurality of clock top electrodes 154 and the plurality of clock terminals 190, respectively, and the plurality of wiring paths for data system signals. It is. In this case, for each of the plurality of clock upper surface electrodes 154, the shortest clock supply path among the plurality of clock supply paths is larger than the longest wiring path among the plurality of wiring paths for the data system signal. Set short. With this relationship, the clock supply path can be shortened to improve the signal quality of the clock signal.

  In the above-described configuration, the clock enable signal, the chip selection signal, and the write enable signal are drawn to the terminal 190. According to this, the clock enable signal transmitted from the SOC 182 to the SDRAMs 92a and 92b can be inspected and analyzed. Is possible.

  On the other hand, if a clock enable signal or the like is applied not from the SOC 182 but from the outside of the semiconductor device 50, the SDRAMs 92a and 92b can be inspected alone. At this time, if a circuit such as the SOC 182 is connected to the SDRAMs 92a and 92b, the single unit inspection of the SDRAMs 92a and 92b may not be performed accurately.

  In view of this point, a configuration capable of more accurately performing a single inspection of the SDRAMs 92a and 92b will be described below with reference to FIG. FIG. 18 is a cross-sectional view of the semiconductor device 50 outlining the configuration, and illustrates a state in which the semiconductor device 50 is mounted on the mounting substrate 56 for explanation.

  As shown in FIG. 18, the output terminals of the clock enable signal, the chip selection signal, and the write enable signal included in the SOC 182 are connected to the terminal (first terminal) 190 of the lower package 54 via the wiring (first signal line) 700. Has been. The wiring 700 includes the gold bump 188 and the wiring 702 of the wiring board 120 in the example of FIG. Further, the SDRAM 92 a is connected to another terminal (second terminal) 190 through a wiring (second signal line) 720. In the example of FIG. 18, the wiring 720 includes the bonding wire 98, the wiring 724 of the wiring substrate 60, the terminal 110 of the upper package 52, the upper surface electrode 154 and the wiring 722 of the wiring substrate 54. . Further, the terminal 190 to which the wirings 700 and 720 are connected is connected via the wiring 740 of the mounting substrate 56.

  The wirings in the substrates 60, 120, and 56 are simply illustrated in FIG. 18, but are configured by connecting predetermined conductive patterns in each wiring layer in the same manner as illustrated in FIG. In addition, the SOC 182 and another SDRAM 92b are electrically connected with the same configuration as illustrated in FIG.

  According to the above configuration, when the semiconductor device 50 is mounted on the mounting board 56, the clock enable signal, the chip selection signal, and the write enable signal output from the SOC 182 are connected to the SDRAMs 92 a and 92 b via the wiring 740 of the mounting board 56. Is input. On the other hand, before mounting on the mounting board 56, it is possible to input a clock enable signal, a chip selection signal, and a write enable signal from a terminal 190 electrically connected to the SDRAMs 92a and 92b. At this time, since the SDRAMs 92 a and 92 b are electrically separated from the SOC 182, the SDRAM 92 a and 92 b can be accurately inspected without being affected by the SOC 182.

  The SOC 182 can also be electrically separated from the SDRAMs 92a and 92b by inserting, for example, a switch component using a mechanical contact into the wiring 740 of the mounting board 56 and turning off the switch component.

  The terminal 190 connected to the SOC 182 via the wiring 700 is called a signal lead terminal 190, and the terminal 190 connected to the SDRAMs 92a and 92b via the wiring 720 is called an external input terminal 190.

  An arrangement example of the signal lead-out terminal 190 and the external input signal 190 will be described with reference to FIGS. FIGS. 19 and 21 are enlarged plan views outlining the functional assignment of the terminals 190 and 200, and FIGS. 20 and 22 are enlarged plan views outlining the functional assignment of the upper surface electrode 154. FIG. 19 to 22 are illustrated in the same manner as in FIG. 6 and the like. 19 and 21 schematically show the wiring 740 of the mounting board 56 (see FIG. 18) for the sake of explanation.

  19 to 22, reference numerals CKEA1 to CKEA4, CKEB1 to CKEB4 are assigned clock enable signals, reference signs CSA1 to CSA4 and CSB1 to CSB4 are assigned chip selection signals, and reference signs WE1 to WE4 are assigned write enable signals. Indicates that Description of other function assignments is omitted.

  Further, the terminal 190 and the upper surface electrode 154 with numerals “1” and “2” at the end of the code are for the SDRAM 92a, and the terminal 190 and upper surface electrode 154 with the numerals “3” and “4” are for the SDRAM 92b.

  Further, the terminal 190 whose code ends are “1” and “3”, for example, the terminal 190 whose code ends are CKEA1 and CKEA3, is a signal lead-out terminal 190, and the terminal 190 whose code ends is “2” and “4”, such as reference numerals CKEA2 and CKEA4. The terminal 190 is an external input terminal 190.

  Further, the terminal 190 having the same character string excluding the number at the end of the code and having the code end of “1” and the terminal 190 having “2” are connected by the wiring 740 of the mounting board 56. For example, the signal lead terminal 190 denoted by reference numeral CKEA1 and the external connection terminal 190 denoted by reference numeral CKEA2 are connected by a wiring 740. Similarly, the terminal 190 having the same character string excluding the number at the end of the code and having the code end of “3” and the terminal 190 of “4”, for example, the signal extraction terminal 190 of the code CKEA3 and the external connection terminal 190 of the code CKEA4 Are connected by a wiring 740. The upper surface electrode 154 is connected to the external input terminal 190 having the same symbol.

  In the example of FIGS. 19 and 21, the pair of terminals (first terminal and second terminal) 190 connected by the wiring 740 are arranged adjacent to each other. According to such an arrangement form, the wiring 740 can be shortened (minimized), so that the arrangement range of the wiring 740 on the mounting substrate 56 can be suppressed.

  In the example of FIGS. 19 and 21, the terminals 190 connected by the wiring 740 are aggregated for each of the SDRAMs 92a and 92b. According to this aggregated arrangement, other wirings on the mounting substrate 56 can easily avoid the wiring 740, and the arrangement of the other wirings is facilitated.

  In view of the fact that the upper surface electrode 154 is arranged in the peripheral region of the wiring board 120, the signal lead-out terminal 190 and the external input terminal 190 are arranged at or near the outermost periphery of the arrangement of the terminals 190 (for example, 1 counted from the outermost periphery). (Within ˜5 rounds) and in the vicinity of the upper electrode 154 to be connected. That is, according to such an arrangement, the route for the clock enable signal, the chip selection signal, and the write enable signal (in the example of FIG. 18, the wiring “700” → “740”) with respect to the wiring length and the wiring route (wiring topology). → "720" route) to another address / command system signal route ("352"-> "354"-> "358"-> "200"-> "358" drawn in the land 200) The route “→” 354 ”→“ 356 ”) can be used. As a result, the clock enable signal, the chip select signal, and the write enable signal have a smaller signal delay difference, that is, a signal timing difference from other address / command signals, and the signal quality is uniformized for the address / command signals. can do. As a result, the reliability of the semiconductor device 50 can be improved.

  Note that a stacked semiconductor device can be configured by stacking and joining three or more semiconductor packages. Even in such a case, the various effects described above can be obtained by including the above-described exemplary configuration in the semiconductor device.

It is sectional drawing which outlines the structure of the laminated semiconductor device which concerns on embodiment. It is sectional drawing which outlines the structure of the laminated semiconductor device which concerns on embodiment. It is a typical top view (plan view seen from the board | substrate upper surface side) which outlines the structure of the lower package which concerns on embodiment. FIG. 3 is a schematic plan view outlining the structure of the lower package according to the embodiment (a plan view seen through the substrate lower surface from the substrate upper surface side). 1 is a block diagram outlining a stacked semiconductor device according to an embodiment. It is a top view which outlines the function allocation of the terminal of the lower package which concerns on embodiment, and a land. It is a top view which outlines the function allocation of the upper surface electrode of the lower package which concerns on embodiment. It is a top view which outlines arrangement | positioning of the upper surface electrode of the lower package which concerns on embodiment. It is a top view which outlines arrangement | positioning of the upper surface electrode of the lower package which concerns on embodiment. 1 is a circuit diagram outlining a power supply system of a stacked semiconductor device according to an embodiment. 1 is a cross-sectional view outlining a power supply system of a stacked semiconductor device according to an embodiment. 1 is a circuit diagram outlining a power supply system of a stacked semiconductor device according to an embodiment. 1 is a cross-sectional view outlining a power supply system of a stacked semiconductor device according to an embodiment. It is a typical top view (plan view seen from the board | substrate upper surface side) which outlines a power supply system about the upper surface electrode of the lower package which concerns on embodiment. It is a typical top view (plan view which saw through the substrate undersurface from the substrate upper surface side) which outlines a power supply system about the terminal of the lower package concerning an embodiment. FIG. 16 is a schematic plan view (plan view in which FIG. 14 and FIG. 15 are superimposed) outlining a power supply system for the lower package according to the embodiment. It is a typical top view (plan view which saw through a substrate undersurface and a power supply plane from the substrate upper surface side) which outlines a power supply system about a lower package concerning an embodiment. It is sectional drawing which outlines the structure of the laminated semiconductor device which concerns on embodiment. It is a top view which outlines the function allocation of the terminal of the lower package which concerns on embodiment. It is a top view which outlines the function allocation of the upper surface electrode of the lower package which concerns on embodiment. It is a top view which outlines the function allocation of the terminal of the lower package which concerns on embodiment. It is a top view which outlines the function allocation of the upper surface electrode of the lower package which concerns on embodiment.

Explanation of symbols

  50 stacked semiconductor device, 52 upper semiconductor package, 54 lower semiconductor package, 90 upper semiconductor integrated circuit, 92a, 92b SDRAM (memory circuit), 120 wiring board, 122 substrate upper surface, 124 substrate lower surface, 126, 126a, 126b, 126c, 126d substrate side, 128, 128ab, 128cd substrate apex, 152, 352 signal line, 154, 354 upper surface electrode, 180 lower semiconductor integrated circuit, 182 semiconductor chip, 184, 184a, 184b, 184c, 184d chip side, 186 , 186ab, 186cd Chip apex, 358 Signal lead-out line, 190 ball electrode (terminal), 200 land, 310a, 310b interface unit, 311a, 311b Clock system interface unit, 313a, 314a, 13b, 314b Data system interface unit, 315a, 316a, 315b, 316b Address / command system interface unit, 410a, 410b Upper surface electrode group, 411a, 411b Clock system electrode group, 413a, 414a, 413b, 414b Data system electrode group, 415a , 416a, 415b, 416b Address / command system electrode group.

Claims (11)

A lower semiconductor package;
An upper semiconductor package stacked on the lower semiconductor package;
With
The lower semiconductor package is
A wiring substrate having a substrate upper surface facing the upper semiconductor package and a substrate lower surface having a front-back relationship with the substrate upper surface;
A semiconductor integrated circuit mounted on the upper surface of the substrate;
Including
The wiring board is
An upper surface electrode provided outside the semiconductor integrated circuit on the upper surface of the substrate and connected to the upper semiconductor package;
A signal line connecting the upper surface electrode and the semiconductor integrated circuit;
A plurality of terminals provided on the lower surface of the substrate;
A land that is provided outside the outermost periphery of the array of the plurality of terminals on the lower surface of the substrate and is disposed in proximity to the upper surface electrode;
A signal lead line connecting the land and the upper surface electrode;
A stacked semiconductor device comprising: The stacked semiconductor device according to claim 1,
The upper semiconductor package has a memory chip,
The semiconductor integrated circuit of the lower semiconductor package has a logic chip that accesses the memory chip to read and write data;
A stacked semiconductor device, wherein the signal lead-out line is provided for a path for reading and writing data. The stacked semiconductor device according to claim 2,
The logic chip transmits an address signal that specifies a memory address of an access destination,
The stacked semiconductor device, wherein the signal lead-out line is provided for the address signal path. The stacked semiconductor device according to claim 3,
The logic chip transmits a command signal for controlling the memory chip,
The stacked semiconductor device, wherein the signal lead-out line is provided for the command signal path. The stacked semiconductor device according to claim 1,
The upper semiconductor package includes a plurality of terminals bonded to the wiring board of the lower semiconductor package,
The stacked semiconductor device, wherein an arrangement pitch of the plurality of terminals of the lower semiconductor package is smaller than an arrangement pitch of the plurality of terminals of the upper semiconductor package. The stacked semiconductor device according to claim 1,
The plurality of terminals are each constituted by a ball electrode, and no ball electrode is provided on the land. The stacked semiconductor device according to claim 1,
The plurality of terminals on the lower surface of the substrate includes a plurality of power supply terminals for supplying power for the upper semiconductor package from the outside of the package,
The wiring board has a plurality of the upper surface electrodes and the lands, respectively.
The plurality of upper surface electrodes are:
A plurality of power supply upper surface electrodes for supplying the upper semiconductor package power supply to the upper semiconductor package;
A plurality of data system signal upper surface electrodes for transmitting data between the lower semiconductor package and the upper semiconductor package;
Including
The plurality of lands include a plurality of data system signal lands connected to the plurality of data system signal upper surface electrodes, respectively.
The wiring board is
A plurality of power supply paths between the power top electrode and the plurality of power terminals for each of the plurality of power top electrodes;
A plurality of wiring paths respectively connecting the plurality of data system signal upper surface electrodes and the plurality of data system signal lands;
Have
For each of the plurality of power supply upper surface electrodes, the shortest power supply path among the plurality of power supply paths satisfies a relationship of being shorter than the longest wiring path among the plurality of wiring paths. A stacked semiconductor device. The stacked semiconductor device according to claim 1,
The plurality of terminals on the lower surface of the substrate includes a plurality of clock terminals for supplying a clock signal for the upper semiconductor package from the outside of the package,
The wiring board has a plurality of the upper surface electrodes and the lands, respectively.
The plurality of upper surface electrodes are:
A plurality of clock top electrodes respectively connected to the plurality of clock terminals;
A plurality of data system signal upper surface electrodes for transmitting data between the lower semiconductor package and the upper semiconductor package;
Including
The plurality of lands include a plurality of data system signal lands connected to the plurality of data system signal upper surface electrodes, respectively.
The wiring board is
A plurality of clock supply paths respectively connecting the plurality of clock top electrodes and the plurality of clock terminals;
A plurality of wiring paths respectively connecting the plurality of data system signal upper surface electrodes and the plurality of data system signal lands;
Have
For each of the plurality of clock upper surface electrodes, the shortest clock supply path among the plurality of clock supply paths satisfies the relationship that it is shorter than the longest wiring path among the plurality of wiring paths. A stacked semiconductor device. A lower semiconductor package;
An upper semiconductor package stacked on the lower semiconductor package;
With
The lower semiconductor package is
A wiring board having a substrate upper surface facing the upper semiconductor package;
A semiconductor integrated circuit including at least one semiconductor chip mounted on the upper surface of the substrate and having a plurality of interface portions provided on the at least one semiconductor chip;
Including
The wiring board is
A plurality of upper surface electrodes provided around the semiconductor integrated circuit on the upper surface of the substrate;
A plurality of wirings connecting the plurality of upper surface electrodes and the plurality of interface units;
Have
Each interface unit is
Provided at a corner of the at least one semiconductor chip;
2. A stacked semiconductor device comprising: a plurality of upper surface electrodes connected to an upper surface electrode group disposed along two substrate sides of the wiring substrate adjacent to the interface unit. The stacked semiconductor device according to claim 9, wherein
The upper semiconductor package is connected to the interface unit through the upper surface electrode group, and inputs / outputs data according to a clock signal, an address / command signal, and a data input / output control signal output from the interface unit. Including multiple circuits,
Each interface unit is
An address / command interface unit that outputs the address / command system signal that is divided into two chip sides that form the chip corner where the interface unit is disposed;
Divided into the two chip sides, arranged on the chip apex side formed by the two chip sides with respect to the address / command interface unit, and performs the input / output of the data and the output of the data input / output control signal. , Data system interface part,
A clock system interface unit arranged between the divided data system interface units and outputting the clock system signal;
Including
Each upper surface electrode group includes:
A group of electrodes connected to the clock system interface unit of the interface unit of the connection destination, the clock system electrode group disposed in the vicinity of the clock system interface unit;
An electrode group connected to the address / command system interface unit of the interface unit of the connection destination, the address / command system electrode group arranged separately on the two substrate sides;
A group of electrodes connected to the data system interface unit of the connection destination interface unit, the substrate vertex being divided into the two substrate sides and formed by the two substrate sides with respect to the address / command system electrode group A data system electrode group disposed on the side of
A stacked semiconductor device comprising: A lower semiconductor integrated circuit comprising: a lower semiconductor integrated circuit; and a wiring board on which the lower semiconductor integrated circuit is mounted;
An upper semiconductor package stacked on the lower semiconductor package and bonded to the wiring substrate, including an upper semiconductor integrated circuit;
A signal line for transmitting a signal between the lower semiconductor integrated circuit and the upper semiconductor integrated circuit;
With
The wiring board has a plurality of terminals provided on the lower surface of the substrate forming a front-back relationship with the upper surface of the substrate to which the upper semiconductor package is bonded;
The signal line is
A first signal line connecting the lower semiconductor integrated circuit and a first terminal of the plurality of terminals;
A second signal line connecting the upper semiconductor integrated circuit and a second terminal adjacent to the first terminal among the plurality of terminals;
A stacked semiconductor device comprising:

Images