JP2016061857A - Source driver IC - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a source driver IC that applies a voltage stress to a gradation voltage line and performs a stress test reliably in a short time.SOLUTION: The source driver IC has: a gradation voltage generation circuit for generating j pieces of gradation voltages (j is an integer equal to or greater than 2); a decoder circuit for selecting a drive voltage corresponding to n pieces of data from the j pieces of gradation voltages on the basis of an inputted gradation signal and outputting the selected drive voltage; and a gradation voltage line group juxtaposed in a wiring layer and comprising j pieces of gradation voltage lines for transmitting each of the j gradation voltages to the decoder circuit. The gradation voltage line group is arranged so that gradation voltage lines for transmitting gradation voltages indicating (k+j/2) gradation levels are disposed adjacent to gradation voltage lines for transmitting gradation voltages indicating k gradation levels (k is an integer satisfying the relationship 0≤k<j/2), and gradation voltage lines for transmitting gradation voltages indicating (k+1) gradation levels are disposed adjacent to gradation voltage lines for transmitting gradation voltages indicating (k+j/2) gradation levels.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a display driver, and more particularly to a source driver that supplies a gradation voltage corresponding to an input video signal to each of a plurality of data lines (source lines) formed on a display panel.

  For example, a two-dimensional display panel such as a liquid crystal display panel has a plurality of data lines (source lines) extending in the vertical direction in the in-plane direction of the screen and a plurality of scanning lines (gate lines) extending in the horizontal direction. ing. The display panel is installed on a glass substrate, for example. Further, a display driver, which is a display panel driving device, is provided, for example, in the outer peripheral region of the display panel on the substrate.

  The display driver generates a gradation voltage corresponding to a luminance level for each pixel in the display panel based on a video signal input from the outside, and applies the gradation voltage to each source line of the display panel have.

  For example, Patent Document 1 discloses a DA converter 28 having a gradation adjustment circuit 32, a level conversion circuit 40, a decoder 42, an output circuit 44, and an output pad 46 for each channel, and a signal line driver for a liquid crystal display using the DA converter 28. S1 is disclosed.

JP 2000-137467 A

  The source driver includes, for example, a generation circuit that generates a plurality of gradation voltages corresponding to each luminance level (gradation level), and a gradation corresponding to the luminance level of each pixel from the plurality of gradation voltages. A selection circuit that selects a voltage; and an output circuit that supplies a driving pulse including the selected gradation voltage to each of the source lines.

  For example, in the case of a display panel capable of displaying with 256 gradations, 256 gradation voltages are generated and supplied to the selection circuit. That is, 256 wirings are connected between the generation circuit and the selection circuit. In addition, for the purpose of protecting the liquid crystal cell that carries each pixel, when generating and outputting the negative gradation voltage and the positive gradation voltage alternately, the generation circuit generates the negative gradation voltage and the positive polarity. Are generated. In addition, between the generation circuit and the selection circuit, wiring twice as many as the number of gradations, that is, 512 wirings are connected. Hereinafter, each of these wirings is referred to as a gradation voltage line.

  Although many wirings are provided in the source driver IC, the gradation voltage line is often the longest wiring extending over almost the entire area of the chip. In order to prevent a failure of the gradation voltage line, a stress test is performed by applying a voltage larger than that during normal use to each of the gradation voltage lines. The stress test is performed by applying a stress voltage larger than the normal time to a generation circuit that generates a gradation voltage for a certain period of time.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a source driver IC that can efficiently apply a voltage stress to a gradation voltage line and perform a stress test reliably in a short time. Yes.

  A source driver IC according to the present invention includes a substrate having a wiring layer, a gradation voltage generation circuit that generates j gradation voltages indicating gradation levels of j stages (j is an integer of 2 or more), and an input A decoder circuit that selects and outputs a driving voltage corresponding to n pieces of data from j pieces of gradation voltages based on the gradation signal, and a j number of gradation voltages provided in parallel in the wiring layer. And a grayscale voltage line group consisting of j grayscale voltage lines that transmit each of the grayscale voltage lines to the decoder circuit, and the grayscale voltage line group has a k level (k is 0 ≦ k <j / 2). A gradation voltage line for transmitting a gradation voltage indicating a gradation level of (k + j / 2) is disposed adjacent to a gradation voltage line for transmitting a gradation voltage indicating a gradation level of (integer integer), (k + 1) level adjacent to the gradation voltage line for transmitting the gradation voltage indicating the gradation level of k + j / 2) level. It is characterized in that the gradation voltage lines for transmitting gray level voltage indicating the gradation level of is arranged to be disposed.

  In addition, the source driver IC according to the present invention includes a substrate having first and second wiring layers, j positive grayscale voltages indicating j grayscale levels (j is an integer of 2 or more), and j A grayscale voltage generation circuit comprising a positive polarity grayscale voltage generation circuit and a negative polarity grayscale voltage generation circuit that respectively generate negative polarity grayscale voltages, and j positive electrodes based on the input grayscale signal And a decoder circuit that selects and outputs positive and negative drive voltages corresponding to n pieces of data from the positive and negative grayscale voltages, and is provided in the first and second wiring layers. Of positive polarity gradation voltage lines composed of j positive polarity gradation voltage lines for transmitting each of the positive polarity gradation voltages to the decoder circuit, and j pieces in the first and second wiring layers. Each of the negative polarity grayscale voltage lines is composed of j negative grayscale voltage lines for transmitting to the decoder circuit. A polarity gradation voltage line group, and a positive gradation voltage line group and a negative gradation voltage line group are connected to the first wiring layer at k level (k is a relation of 0 ≦ k <j / 2). A positive gray scale voltage line for transmitting a positive gray scale voltage indicating a gray level of k) and provided with a positive gray scale voltage line for transmitting a positive gray scale voltage indicating a gray scale level A positive gradation voltage line for transmitting a positive gradation voltage indicating a gradation level of (k + j / 2) level is disposed in a region of the second wiring layer on the voltage line, and the first wiring layer includes A polarity gradation voltage line for transmitting a negative gradation voltage indicating a k-level gradation level is provided, and a negative gradation voltage line for transmitting a negative gradation voltage indicating a k-level gradation level is provided on the negative gradation voltage line. Negative polarity for transmitting a negative gradation voltage indicating a gradation level of (k + j / 2) level to the second wiring layer region Scale voltage lines are arranged to be disposed, and is characterized in that each of the respective and negative gradation voltage lines of the positive gradation voltage lines are arranged to be adjacent to each other.

  In addition, the source driver IC according to the present invention includes a substrate having first and second wiring layers, j positive grayscale voltages indicating j grayscale levels (j is an integer of 2 or more), and j A grayscale voltage generation circuit comprising a positive polarity grayscale voltage generation circuit and a negative polarity grayscale voltage generation circuit that respectively generate negative polarity grayscale voltages, and j positive electrodes based on the input grayscale signal And a decoder circuit that selects and outputs positive and negative drive voltages corresponding to n pieces of data from the positive and negative grayscale voltages, and is provided in the first and second wiring layers. Of positive polarity gradation voltage lines composed of j positive polarity gradation voltage lines for transmitting each of the positive polarity gradation voltages to the decoder circuit, and j pieces in the first and second wiring layers. Each of the negative polarity grayscale voltage lines is composed of j negative grayscale voltage lines for transmitting to the decoder circuit. A polarity gradation voltage line group, and a positive gradation voltage line group and a negative gradation voltage line group are connected to the first wiring layer at k level (k is a relation of 0 ≦ k <j / 2). A positive gray scale voltage line for transmitting a positive gray scale voltage indicating a gray level of k) and provided with a positive gray scale voltage line for transmitting a positive gray scale voltage indicating a gray scale level A negative gradation voltage line for transmitting a negative gradation voltage indicating a gradation level of (k + j / 2) level is disposed adjacent to the voltage line, and a positive polarity level indicating a gradation level of k level is disposed. A negative gradation voltage line for transmitting a negative gradation voltage indicating a gradation level of k level is disposed in a region of the second wiring layer on the positive gradation voltage line for transmitting the regulated voltage, and the second In the wiring layer, adjacent to the negative gradation voltage line for transmitting the negative gradation voltage indicating the k gradation level, + J / 2) positive gradation voltage lines for transmitting positive gradation voltage indicating the gradation level of the level is characterized by being arranged to be disposed.

  In addition, the source driver IC according to the present invention includes a substrate having l wiring layers, j positive gradation voltages indicating j gradation levels (j is an integer of 2 or more), and j negative electrodes. A grayscale voltage generation circuit comprising a positive polarity grayscale voltage generation circuit and a negative polarity grayscale voltage generation circuit, respectively, and j positive polarity and negative polarity based on the inputted grayscale signal A positive polarity and a negative polarity driving voltage corresponding to n pieces of data from the positive gradation voltage, and a decoder circuit provided in the wiring layer, each of the j positive gradation voltages Are provided in the wiring layer, and each of j negative gradation voltages is transmitted to the decoder circuit. a negative polarity gradation voltage line group composed of j negative polarity gradation voltage lines, and a positive polarity The voltage regulation line group and the negative polarity gradation voltage line group are positive polarity levels for transmitting a positive polarity gradation voltage indicating a gradation level of k level (k is an integer satisfying a relation of 0 ≦ k <j / 2). A positive gradation voltage line that transmits a positive gradation voltage indicating a gradation level of (k + j / l) level is arranged on the adjustment voltage line, and the positive gradation voltage line Each of the negative gradation voltage lines is arranged so as to be adjacent to each other.

  The source driver IC according to the embodiment of the present invention can generate a relatively large potential difference between adjacent gradation voltage lines. Therefore, a large voltage stress can be applied between adjacent gradation voltage lines in a short time, and the wiring quality can be evaluated efficiently.

FIG. 3 is a diagram illustrating a configuration of a display driver of Example 1. FIG. 3 is a diagram illustrating a configuration of a source driver IC in the display driver according to the first embodiment. FIG. 6 is a diagram illustrating a relationship between a gradation level of a gradation voltage generated by a positive gradation voltage generation circuit and a negative gradation voltage generation circuit in the gradation voltage generation circuit of the source driver IC according to the first exemplary embodiment. (A) is a top view of the source driver IC of Example 1, and (b) and (c) are sectional views thereof. (A) And (b) is a figure which shows the detail of the positive polarity gradation voltage generation circuit in the source driver IC of Example 1, and a negative polarity gradation voltage generation circuit, respectively. It is sectional drawing of the source driver IC of a comparative example. FIG. 6 is a cross-sectional view illustrating a configuration of a source driver IC according to a modification example of Example 1. (A), (b), and (c) are sectional drawings which show the structure of the source driver IC which concerns on Example 2, 3, and 4, respectively.

  Examples of the present invention will be described in detail below.

  FIG. 1 is a diagram illustrating a configuration of a display driver 10 according to the first embodiment of the present invention. The display driver 10 displays an image on a display panel PNL such as a liquid crystal panel, a plasma panel, and an organic EL (Electro Luminescence) panel, for example, based on a video signal VS input from the outside. A display panel (hereinafter simply referred to as a panel) PNL is a panel that displays a two-dimensional image.

The panel PNL has m scanning lines C _{1 to} C _m each extending in the horizontal direction of the two-dimensional screen (m is an integer of 2 or more) and n lines (n each extending in the vertical direction of the two-dimensional screen. Is an integer of 2 or more) source lines S _{1 to} S _n . Further, display cells DS serving as pixels of the panel PNL are provided at intersections between the scanning lines C1 to Cm and the source lines S1 to Sn. In the present embodiment, a case will be described in which the display panel PNL is made of, for example, a TFT (Thin Film Transistor) liquid crystal panel.

The display driver 10 includes a drive control unit 20, a scan driver 30, and a source driver IC (hereinafter simply referred to as a source driver) 40. Based on the video signal VS, the drive control unit 20 generates a scan control signal SCS for sequentially applying a scan pulse to each of the scan lines C _{1 to} C _n , and supplies this to the scan driver 30. The scan driver 30 generates a scan pulse at a timing according to the scan control signal SCS, and alternately applies the scan pulse to each of the scan lines C _{1 to} C _n of the panel PNL.

Further, the drive control unit 20 generates pixel data PD representing a luminance level (gradation level) in each pixel based on the video signal VS, and converts this into a scan clock signal in serial form for each scan line. The source driver 40 is supplied at a synchronized timing. Based on the pixel data PD, the source driver 40 generates gradation voltages V _{1 to} V _n corresponding to the gradation levels of each pixel (n) in one scanning line. The source driver 40 has n grayscale voltage output terminals (not shown), and a drive pulse having each of the grayscale voltages V _{1 to} V _n is sent from the respective output terminals to the source lines S _{1 to} S. Applicable to each of _n .

  FIG. 2 is a diagram showing a detailed configuration of the source driver 40. The source driver 40 includes a substrate 41, a gradation voltage generation circuit 42, a decoder circuit 43, and a selector circuit 44. The gradation voltage generation circuit 42 includes a positive gradation voltage generation circuit 42P that generates j (j is an integer of 2 or more) different positive gradation voltages, and j different negative gradation voltages. And a negative polarity gradation voltage generation circuit 42N to be generated.

The decoder circuit 43, the drive control unit 20, the tone signal GS ₁ ~GS _n of n is a digital signal (the number of source lines) are input. Further, between the grayscale voltage generation circuit 42 and the decoder circuit 43, a positive grayscale voltage line group W composed of j positive grayscale voltage wirings (hereinafter referred to as positive grayscale voltage lines). _p is connected to a negative gradation voltage line group W _n composed of j negative gradation voltage wirings (hereinafter referred to as negative gradation voltage lines). The decoder circuit 43, based on the input tone signal GS ₁ ~GS _n, from the gradation voltage generated by the gradation voltage generating circuit 42, the n-number to be applied to each of the source lines S ₁ to S _n Positive drive voltages DV _{P1 to} DV _Pn and negative drive voltages DV _{N1 to} DV _Nn corresponding to the display data are respectively selected and output.

Specifically, the decoder circuit 43 includes a positive gray scale voltage decoder group 43 _{P including} n positive gray scale voltage decoders 43 _P1 to 43 _Pn to which the positive gray scale voltage line group W _p is connected. A negative gradation voltage decoder group 43 _N composed of n negative gradation voltage decoders 43 _N1 to 43 _Nn connected to the negative gradation voltage line group W _n .

For example, the polarity inversion signal IS having two types of logic values of H level or L level is input to the selector circuit 44 from the drive control unit 20. The selector circuit 44 selects each of the positive drive voltages DV _{P1 to} DV _Pn from the decoder circuit 43 or the negative drive voltages DV _{N1 to} DV _Nn based on the polarity inversion signal IS, and outputs this Output as drive voltages DV _{1 to} DV _n . Specifically, the selector circuit 44 includes a selector SV ₁ that selects _one of the positive drive voltage DV _P1 and the negative drive voltage DV _N1 and outputs it as the output drive voltage DV ₁ . Similarly, the selector circuit 44 has n selectors SV _{1 to} SV _n . The source driver 40, the drive pulses each having an output driving voltage DV ₁ ~DV _n, is applied to each of the source lines S ₁ to S _n of the panel PNL.

  FIG. 3 is a diagram showing the relationship between the gradation voltage generated by the gradation voltage generation circuit 42 (the positive gradation voltage generation circuit 42P and the negative gradation voltage generation circuit 42N) of the source driver 40 and the gradation level. It is. In the figure, the horizontal axis indicates the gradation level, and the vertical axis indicates the gradation voltage. The gradation voltage generation circuit 42 performs gamma correction based on the gamma value according to the characteristics of the panel PNL and the like, and generates a corrected gradation voltage. Specifically, each of the positive gradation voltage generation circuit 42P and the negative gradation voltage generation circuit 42N performs gamma correction based on the reference gradation voltage applied to each of the positive gradation voltage generation circuit 42P and the negative gradation voltage generation circuit 42N. A positive gradation voltage and a negative gradation voltage are generated.

Hereinafter, a case where the gradation voltage generation circuit 42 generates a gradation voltage indicating a gradation of 256 gradations (when j = 256) will be described. In other words, in this embodiment, the positive polarity gradation voltage generation circuit 42P has the 255th level (255th number, 255th) from the positive polarity gradation voltage V _P001 indicating the 0th level (0th, 0th) grayscale level. ) 256 different gradation voltages up to the positive gradation voltage _VP256 indicating the gradation level are generated. Further, the negative gradation voltage generation circuit 42N has 256 pieces of negative gradation voltage V _N001 indicating the gradation level of 0 level to negative gradation voltage V _N256 indicating the gradation level of 255. Different gradation voltages are generated. Although not shown, the source driver 40 generates gradation voltages indicating 256 gradations for each of red (R), green (G), and blue (B), and performs full-color display driving. .

  FIG. 4A is a top view of the source driver 40. FIG. 4B and FIG. 4C are cross-sectional views of the source driver 40. The source driver 40 has a semiconductor substrate (hereinafter simply referred to as a substrate) 41. The positive gradation voltage generation circuit 42P and the negative gradation voltage generation circuit 42N are formed in and on the substrate 41. In the present embodiment, the substrate 41 has a rectangular shape in a top view, and the positive polarity gradation voltage generation circuit 42P and the negative polarity gradation voltage generation circuit 42N are respectively formed in end regions in the longitudinal direction of the substrate 41. The case will be described.

As shown in FIGS. 4A to 4C, the source driver 40 has a wiring layer WL having a two-layer structure including a first wiring layer WL1 and a second wiring layer WL2 on a substrate 41. doing. That is, the source driver 40 has a substrate 41 having a wiring layer WL, and the wiring layer WL has a first wiring layer WL1 and a second wiring layer WL2. Each of the positive gray scale voltage lines W _{P001 to} W _P256 in the positive gray scale voltage line group W _p is juxtaposed to the first wiring layer WL1 on the substrate 41, and from the positive gray scale voltage generation circuit 42P to the substrate 41. It extends along the longitudinal direction. In addition, each of the negative gradation voltage lines W _{N001 to} W _N256 in the negative gradation voltage line group W _n is juxtaposed to the second wiring layer WL2 on the first wiring layer WL1, and the negative gradation voltage The generation circuit 42N extends along the longitudinal direction of the substrate 41.

FIG. 4B is a cross-sectional view taken along line XX in FIG. As shown in FIG. 4B, in this embodiment, the positive gradation voltage generation circuit 42P, the negative gradation voltage generation circuit 42N, the positive gradation voltage decoders 43 _P1 to 43 _Pn, and the negative gradation. The voltage decoders 43 _N1 to 43 _Nn are formed in the substrate 41.

The positive gradation voltage line W _P001 is connected to the positive gradation voltage generation circuit 42P through the via wiring VW _P0 . Further, the positive gradation voltage line W _P001 is connected to each of the positive gradation voltage decoders 43 _P1 to 43 _Pn of the decoder circuit 43 through the via wirings VW _{P1 to} VW _Pn . Similarly, each of the positive gradation voltage lines W _P002 to _W-P256 are connected via a via wiring to each of the positive gradation voltage generating circuit 42P and positive gradation voltage decoder 43 _P1 ~ 43 _Pn .

The negative gradation voltage line W _N001 is connected to the negative gradation voltage generation circuit 42N via the via wiring VW _N0 . The negative gradation voltage line W _N001 is connected to each of the negative gradation voltage decoders 43 _N1 to 43 _Nn of the decoder circuit 43 through the via wirings VW _{N1 to} VW _Nn . Similarly, each of the negative gradation voltage lines W _{N002 to} W _N256 is _connected to each of the negative gradation voltage generation circuit 42N and the negative gradation voltage decoders 43 _N1 to 43 _Nn through via wiring. . In FIG. 4B, for ease of understanding, the negative gradation voltage line W _N001 and the via wiring connected to the negative gradation voltage line W _N001 are indicated by broken lines.

FIG. 4C is a cross-sectional view taken along line YY in FIG. FIG. 4 (c), as an example, the selector SV n _{/ 2} for outputting a positive drive voltage DV _{Pn / 2} positive gradation voltage generating decoder for outputting a 43 _{Pn / 2} and the output drive voltage DV n _{/ 2} of A cross-sectional view is shown. As shown in FIG. 4C, in this embodiment, the selector SV _{n / 2} is formed in the substrate 41.

  As shown in FIG. 4A and FIG. 4C, the positive polarity gradation voltage line group Wp indicates a gradation level of k level (k is an integer satisfying a relationship of 0 ≦ k <j / 2). Adjacent to the positive polarity gradation voltage line for transmitting the gradation voltage, the positive polarity gradation voltage line for transmitting the gradation voltage indicating the gradation level of (k + j / 2) level is arranged. Yes. Further, adjacent to the positive polarity gradation voltage line for transmitting the gradation voltage indicating the gradation level of (k + j / 2) level, the positive polarity level for transmitting the gradation voltage indicating the gradation level of (k + 1) level. It arranges so that a regulated voltage line may be arranged. That is, the gradation voltage lines that transmit gradation voltages indicating gradation levels different from each other by half gradation are arranged so as to be adjacent to each other.

Specifically, in the first wiring layer WL1, a positive polarity adjacent to the positive polarity gradation voltage line W _P001 (a positive polarity gradation voltage line transmitting the gradation voltage V _P001 indicating a gradation level of 0 level). The positive gradation voltage line W _P129 (a positive gradation voltage line transmitting a gradation voltage V _P128 indicating a gradation level of 128 (= 0 + 128)) is adjacent to the positive gradation voltage line W _P129 and is positive. The gradation voltage line W _P002 (positive gradation voltage line that transmits the gradation voltage V _P002 indicating one gradation level) is disposed adjacent to the other.

In addition, a negative gradation voltage line that transmits a negative gradation voltage indicating the same gradation level is disposed on each of the positive gradation voltage lines in the first wiring layer WL1. Specifically, for example, on the positive gradation voltage line W _P001 (the positive gradation voltage line transmitting the gradation voltage V _P001 indicating the gradation level of 0 level), the negative gradation voltage line W P _N001 (a negative gradation voltage line for transmitting a negative gradation voltage V _N001 indicating a gradation level of 0 level) is arranged. Further, on the positive gradation voltage lines W _P129 are disposed negative gradation voltage lines W _N129.

Each gradation voltage line in each wiring layer WL1 and WL2 is insulated by an insulating layer. Specifically, positive gradation voltage lines W _{P001 to} W _P256 are formed on the substrate 41 as the first wiring layer WL1, and the first gradation layer voltage lines W _{P001 to} W _P256 are covered so as to cover the positive gradation voltage lines W _{P001 to} W _P256 . One insulating layer ISL1 is formed. Further, on the first insulating layer ISL1, as the second wiring layer WL2, negative gradation voltage lines W _{N001 to} W _N256 are formed so as to cover the negative gradation voltage lines W _{N001 to} W _N256. A second insulating layer ISL2 is formed.

FIG. 5A is a diagram showing a configuration of the positive gradation voltage generation circuit 42P. The positive gradation voltage generation circuit 42P includes a ladder resistor R _P in which (j−1) resistors R _{P1 to} R _Pj are connected in series between the terminals T1 and T2. In this embodiment, j = 256, and 255 resistors R _P1 , R _P2 ,... And R _P255 are connected in series between the terminals T1 and T2 in this order. Further, as shown in FIG. 5A, positive gradation voltage lines W _{P001 to} W _P256 are connected to each of adjacent resistors. Specifically, a positive gradation voltage line W _P001 that transmits a positive gradation voltage V _P001 indicating a gradation level of 0 level to the decoder circuit 43 is connected between the terminal T1 and the resistor R _P1. Yes. Connected between the resistor R _P1 and the resistor R _P2 is a positive polarity gradation voltage line W _P002 that transmits a positive polarity gradation voltage V _P002 indicating one gradation level. As described above, the positive gray scale voltage generation circuit 42P generates the positive gray scale voltages V _{P001 to} V _P256 by _dividing the reference gray scale voltage (positive reference gray scale voltage) between the terminals T1 and T2. To do.

FIG. 5B is a diagram showing a configuration of the negative polarity gradation voltage generation circuit 42N. Negative gradation voltage generating circuit 42N consists (j-1) pieces of resistors R _N1 to R _Nj connected in series between the terminals T3 and T4 have been the ladder resistor R _N. In this embodiment, j = 256, and 255 resistors R _N1 , R _N2 ,... And R _N255 are connected in series between the terminals T3 and T4 in this order. Further, as shown in FIG. 5B, each of the negative gradation voltage lines W _{N001 to} W _N256 is connected between the adjacent resistors. Specifically, for example, a negative gradation voltage line W _N001 for transmitting a negative gradation voltage V _N001 indicating a gradation level of 0 level to the decoder circuit 43 is connected between the terminal T3 and the resistor R _N1. Has been. Between resistor R _N1 and the resistor R _N2, negative gradation voltage lines W _N002 are connected to transmit one level negative gradation voltage V _N002 indicating the gradation level of. As described above, the negative gradation voltage generation circuit 42N generates the negative gradation voltages V _{N001 to} V _N256 by _dividing the reference gradation voltage (negative reference gradation voltage) between the terminals T3 and T4. To do.

  Next, with reference to FIGS. 5A and 5B, a voltage stress test of each gradation voltage line will be described. The voltage stress test is performed by applying a voltage higher than that during normal use between the terminals T1 and T2 and between the terminals T3 and T4 for a predetermined time.

The voltage levels of the gradation voltages V _{P001 to} V _P256 and V _{N001 to} V _N256 generated by the gradation voltage generation circuit 42 take values as shown in FIG. Also, in order to apply voltage stress to each adjacent gradation voltage line efficiently, it is sufficient to apply a voltage significantly higher than in normal use. However, considering the protection of the entire chip, a slightly higher test voltage is required. Will be applied. That is, in many cases, it is difficult to apply a test voltage that is greatly different from the normal voltage between the gradation voltage lines of the same polarity.

In this embodiment, gradation voltage lines (for example, positive gradation voltage lines W _P001 and W _P129 ) that transmit gradation voltages indicating gradation levels different in half gradation are arranged adjacent to each other. Therefore, a relatively large potential difference can be generated between the adjacent gradation voltage lines. Therefore, a large voltage stress can be applied between adjacent gradation voltage lines in a short time, and the wiring quality can be evaluated efficiently.

FIG. 6 is a cross-sectional view illustrating a configuration of a source driver 100 according to a comparative example of the present embodiment. FIG. 6 is a cross-sectional view similar to FIG. The source driver 100 has the same configuration as the source driver 40 except for the arrangement form of the positive polarity gradation voltage lines W _{P001 to} W _P256 and the negative polarity gradation voltage lines W _{N001 to} W _N256 . In this comparative example, on the substrate 41, a positive gradation voltage line _{W P001, W P002, ··· W} P256 are arranged in this order. _Further , the negative gradation voltage lines W _{N001 to} W _N256 are arranged in this order on the positive gradation voltage lines W _{P001 to} W _P256 . That is, a gradation voltage line indicating a (k + 1) level gradation level is disposed adjacent to a gradation voltage line indicating a gradation level of k level.

  When a voltage stress test is performed in this comparative example, a potential difference similar to the potential difference caused by the gradation voltage generated in the normal state is generated between adjacent gradation voltage lines. Therefore, compared with the source driver 40 of the present embodiment, voltage stress cannot be applied between the adjacent gradation voltage lines efficiently. Therefore, the time for the stress test is longer than that in the present embodiment, and the time required for evaluating the wiring quality is increased.

  Note that between adjacent gradation voltage lines of different polarities (between gradation voltage lines adjacent in the vertical direction in this embodiment and this comparative example), the test voltage applied between the terminals T1 and T2, the terminals T3 and By controlling the test voltage applied during T4, the stress test time between adjacent gradation voltage lines of the same polarity in this comparative example can be made shorter. Therefore, for the voltage stress test between adjacent different gradation voltage lines, the test time is rarely a bottleneck.

  In addition, when the gradation voltage line is formed and arranged using the wiring layer WL including a plurality of wiring layers (two wiring layers WL1 and WL2 in this embodiment), the chip size can be reduced. Become. However, on the other hand, the number of adjacent gradation voltage lines increases, and it becomes difficult to generate a desired potential difference between all adjacent gradation voltage lines. However, in this embodiment, by optimizing the arrangement of the gradation voltage lines, a relatively large potential difference can be generated between all the gradation voltage lines in the stress test. Therefore, it is possible to evaluate the wiring quality efficiently and in a short time.

In the present embodiment, the case where the display driver 10 displays an image on the display panel PNL as a liquid crystal panel has been described. Therefore, the gradation voltage generation circuit 42 has the positive gradation voltage generation circuit 42P and the negative gradation voltage. The case where the generation circuit 42N is provided has been described. However, for example, in the case of a display driver that displays an image on a plasma panel and an organic EL panel, it is not necessary to provide the negative polarity gradation voltage generation circuit 42N. In this case, the positive gradation voltage line group Wp functions as a gradation voltage line group, and the negative gradation voltage lines W _{N001 to} W _N256 are not necessary. Further, the negative gradation voltage decoder group 43 _N in the decoder circuit 43 does not need to be provided, and the selector circuit 44 does not need to be provided. In this case, the drive voltages DV _{P1 to} DV _Pn selected by the decoder circuit 43 are output as the output drive voltages DV _{1 to} DV _n .

  In this embodiment, the case where each gradation voltage line is provided in the two wiring layers WL1 and WL2 has been described. However, all the gradation voltage lines are used as the wiring layer WL, for example, the first wiring layer on the substrate 41. It may be provided only in the wiring layer WL1.

  FIG. 7 is a diagram illustrating a configuration of a source driver 40A according to a modification of the present embodiment. FIG. 7 is a cross-sectional view similar to FIG. 4C of the source driver 40A. The source driver 40A is a configuration example in the case where a gradation voltage is applied to a source line of a display panel as a plasma panel or an organic EL panel.

The source driver 40A has the positive gradation voltage generation circuit 42P in the first embodiment as a gradation voltage generation circuit, and positive gradation voltage lines W _{P001 to} W _P256 are formed on the substrate 41 as gradation voltage lines. Is provided. Although not shown, the source driver 40A has the positive polarity gradation voltage decoders 43P1 to 43Pn of the first embodiment as a decoder circuit. The source driver 40A does not have the selector circuit 44 of the source driver 40. Also in the source driver 40A, positive gradation voltage lines W _{P001 to} W _{P256 as} gradation voltage lines are arranged in the same manner as the source driver 40 of the first embodiment. Therefore, a potential difference can be efficiently generated between adjacent gradation voltage lines, and a voltage stress test can be efficiently performed in a short time.

  Further, in the present embodiment and the modification, the case where the gradation voltage lines indicating gradation levels different in half gradation are arranged adjacent to each other has been described, but the arrangement form of the gradation voltage lines is limited to this. Not. Each of the gradation voltage lines includes a gradation voltage line that transmits a gradation voltage indicating a gradation level of k level and a gradation voltage line that transmits a gradation voltage indicating a gradation level of (k + 1) level. It is sufficient that at least one gradation voltage line for transmitting a gradation voltage indicating another gradation level is interposed between them.

  When the positive gradation voltage line and the negative gradation voltage line are formed in the same layer, the negative gradation voltage line is arranged adjacent to the positive gradation voltage line. Even so, the same effect can be obtained.

FIG. 8A is a cross-sectional view illustrating a configuration of the source driver 50 according to the second embodiment. FIG. 8A is a cross-sectional view of the source driver 50 similar to FIG. 4C. The source driver 50 has the same configuration as the source driver 40 except for the arrangement form of the positive gradation voltage lines W _{P001 to} W _P256 and the negative gradation voltage lines W _{N001 to} W _N256 .

In the present embodiment, on the positive gradation voltage line (for example, the positive gradation voltage line W _P001 ) that transmits the positive gradation voltage indicating the gradation level of the k level, (k + _2/2 / j) A positive gradation voltage line (for example, a positive gradation voltage line W _P129 ) for transmitting a positive gradation voltage indicating a gradation level is formed. Specifically, the positive gradation voltage line W _P129 is formed in a region on the positive gradation voltage line W _P001 in the second wiring layer WL2. Further, the positive gradation voltage line (for example, positive gradation voltage line W _P001 ) and the negative gradation voltage line (for example, negative gradation voltage line W _N001 ) are arranged adjacent to each other.

  In the present embodiment, in the voltage stress test in the same layer, the grayscale voltage lines having different polarities are adjacent to each other, so that the stress test time is unlikely to be long. On the other hand, gradation voltage lines having the same polarity are adjacent in the layer direction (stacking direction). However, since the gradation voltage lines adjacent to each other in the hierarchical direction are gradation voltage lines having gradation levels different from each other by half gradation, a potential difference can be efficiently generated between the gradation voltage lines. Therefore, a voltage stress test can be performed efficiently in a short time.

FIG. 8B is a cross-sectional view illustrating a configuration of the source driver 60 according to the third embodiment. FIG. 8B is a cross-sectional view of the source driver 60 similar to FIG. The source driver 60 has the same configuration as the source driver 40 except for the arrangement form of the positive polarity gradation voltage lines W _{P001 to} W _P256 and the negative polarity gradation voltage lines W _{N001 to} W _N256 .

In this embodiment, the positive gradation voltage line (for example, the positive gradation voltage line W _P001 ) that transmits the positive gradation voltage indicating the k gradation level, and the positive gradation voltage line. A negative gradation voltage line (for example, negative gradation voltage lines W _N001 and W _{N129, respectively} ) that transmits a negative gradation voltage is formed adjacent to W _P001 . In addition, a negative gradation voltage line (for example, a negative polarity gradation line) adjacent to a positive gradation voltage line (for example, a positive gradation voltage line W _P001 ) that transmits a positive gradation voltage indicating a gradation level of k level. A positive gradation voltage line (for example, positive gradation voltage line W _P129 ) for transmitting a positive gradation voltage indicating a gradation level of (k + j / 2) level is formed on the adjustment voltage line WN129. Yes.

  In this embodiment, since the different polarity gradation voltage lines are arranged next to and above one gradation voltage line, the stress test time is unlikely to be long. On the other hand, a gradation voltage line having the same polarity is formed on the different polarity gradation voltage, that is, diagonally opposite (upwardly or downwardly) in the cross section. However, the gradation voltage line of the same polarity opposite to the diagonal line is a gradation voltage line that transmits gradation voltages of gradation levels different in half gradation, and can generate a potential difference between gradation voltage lines efficiently. It becomes. Therefore, a voltage stress test can be efficiently performed in a short time.

FIG. 8C is a cross-sectional view illustrating a configuration of the source driver 70 according to the fourth embodiment. FIG. 8C is a cross-sectional view of the source driver 70 similar to FIG. The source driver 70 is the same as the source driver 40 except that the positive gradation voltage lines W _{P001 to} W _P256 and the negative gradation voltage lines W _{N001 to} W _N256 are arranged and the wiring layer has a three-layer structure. It has the same configuration.

In the present embodiment, the wiring layer WL has a three-layer structure including a first wiring layer WL1, a second wiring layer WL2, and a third wiring layer WL3. Specifically, the first wiring layer WL1 is formed on the substrate 41, the second wiring layer WL2 is formed on the first wiring layer WL1, and the third wiring layer WL3 is formed on the second wiring layer WL2. ing. The positive gradation voltage lines W _{P001 to} W _P256 and the negative gradation voltage lines W _{N001 to} W _N256 are formed in this three-layer wiring layer.

  When each of the gradation voltage lines is divided into three layers as in the present embodiment, the gradation voltage lines having the same polarity have gradation levels different from each other by 1 gradation, that is, 1/3 gradation. May be arranged so that the grayscale voltage lines indicating are adjacent to each other. Even when the wiring layer WL is composed of four or more wiring layers, the same effect can be obtained by arranging the gradation voltage lines indicating gradation levels different by one gradation corresponding to the number of layers adjacent to each other. Can be obtained.

  For example, a positive polarity gradation voltage line WP086 (a gradation voltage line that generates a gradation voltage indicating a gradation of (1 + 256/3) level) on the positive polarity gradation voltage line WP001, and a positive polarity gradation voltage line WP086. A positive polarity gradation voltage line WP172 is formed thereon. Thereby, in the stress test, it is possible to generate a relatively large potential difference between the adjacent gradation voltage lines having the same polarity. Therefore, it is possible to evaluate the wiring quality efficiently and in a short time.

  In the above, the gradation voltage line group transmits gradation voltages indicating gradation levels of k levels (k is an integer satisfying a relationship of 0 ≦ k <j / 2), and (k + 1) At least one gradation voltage line for transmitting a gradation voltage indicating another gradation level is interposed between the gradation voltage line for transmitting a gradation voltage indicating a gradation level of the level. . Therefore, it is possible to generate a relatively large potential difference between adjacent gradation voltage lines in the voltage stress test. Therefore, it is possible to evaluate the wiring quality in a short time.

10 Display driver 40, 40A, 50, 60, 70 Source driver IC
41 Substrate 42 Gradation voltage generation circuit 42P Positive gradation voltage generation circuit 42N Negative gradation voltage generation circuit 43 Decoder circuit Wp Positive gradation voltage line group Wn Negative gradation voltage line group

Claims (6)

A substrate having a wiring layer;
a gradation voltage generating circuit for generating j gradation voltages indicating gradation levels of j stages (j is an integer of 2 or more);
A decoder circuit that selects and outputs a driving voltage corresponding to n pieces of data from the j pieces of gradation voltages based on the inputted gradation signal;
A gradation voltage line group including j gradation voltage lines provided in parallel in the wiring layer and transmitting each of the j gradation voltages to the decoder circuit;
The grayscale voltage line group is adjacent to the grayscale voltage line that transmits a grayscale voltage indicating a grayscale level of k level (k is an integer satisfying a relationship of 0 ≦ k <j / 2) (k + j / 2) The gradation voltage line that transmits the gradation voltage indicating the gradation level of the level is disposed, and is adjacent to the gradation voltage line that transmits the gradation voltage indicating the gradation level of (k + j / 2) level. Then, the source driver IC is characterized in that the gradation voltage lines for transmitting the gradation voltage indicating the gradation level of (k + 1) level are arranged. The grayscale voltage generation circuit includes a positive grayscale voltage generation circuit and a negative polarity that generate j positive grayscale voltages and j negative grayscale voltages indicating the j grayscale levels, respectively. It consists of a gradation voltage generation circuit,
The decoder circuit selects and outputs positive and negative drive voltages corresponding to n pieces of data from the j positive and negative gray scale voltages based on the input gray scale signal. And
The grayscale voltage line group is provided in juxtaposition in the wiring layer, and a positive electrode composed of j positive grayscale voltage lines for transmitting each of the j positive grayscale voltages to the decoder circuit. A negative polarity voltage line group and a negative polarity voltage line which is provided in parallel in the wiring layer and which transmits j negative gray scale voltages to the decoder circuit. Sexual gradation voltage line group,
The positive gradation voltage line group and the negative gradation voltage line group include the positive gradation voltage line that transmits the positive gradation voltage indicating the gradation level of the k level, and the (k + 1) level. The positive gradation voltage line for transmitting a positive gradation voltage indicating another gradation level or the positive gradation voltage line for transmitting a positive gradation voltage indicating the gradation level of 2. The source driver IC according to claim 1, wherein at least one negative gradation voltage line in the negative gradation voltage line group is arranged to be interposed. The wiring layer has first and second wiring layers,
The grayscale voltage generation circuit includes a positive grayscale voltage generation circuit and a negative polarity that generate j positive grayscale voltages and j negative grayscale voltages indicating the j grayscale levels, respectively. It consists of a gradation voltage generation circuit,
The decoder circuit selects and outputs positive and negative drive voltages corresponding to n pieces of data from the j positive and negative gray scale voltages based on the input gray scale signal. And
The grayscale voltage line group is provided in parallel in the first wiring layer, and j positive grayscale voltage lines for transmitting each of the j positive grayscale voltages to the decoder circuit. And j negative polarity levels that are arranged in parallel in the second wiring layer and transmit each of the j negative grayscale voltages to the decoder circuit. A negative gradation voltage line group consisting of a regulated voltage line,
The positive polarity gradation voltage line group is adjacent to the positive polarity gradation voltage line transmitting the positive polarity gradation voltage indicating the k level gradation level, and the gradation level of the (k + j / 2) level. The positive polarity gradation voltage line which transmits the positive polarity gradation voltage indicating the gradation level of the (k + j / 2) level, the positive polarity gradation voltage line transmitting the positive polarity gradation voltage indicating The positive gradation voltage line that transmits the positive gradation voltage indicating the gradation level of (k + 1) level is arranged adjacent to the line, and is arranged.
The negative polarity gradation voltage line group is adjacent to the negative polarity gradation voltage line transmitting the negative polarity gradation voltage indicating the gradation level of the k level, and the gradation level of the (k + j / 2) level. The negative polarity gradation voltage line that transmits the negative polarity gradation voltage indicating the (k + j / 2) level gradation level is disposed, and the negative polarity gradation voltage that transmits the negative polarity gradation voltage indicating the (k + j / 2) level is disposed. 2. The negative polarity gradation voltage line for transmitting a negative polarity gradation voltage indicating the (k + 1) level gradation level is arranged adjacent to the line so as to be arranged. Or the source driver IC of 2. A substrate having first and second wiring layers;
Positive polarity gradation voltage generation circuit and negative polarity step for generating j positive gradation voltages and j negative gradation voltages indicating gradation levels of j stages (j is an integer of 2 or more), respectively. A gradation voltage generation circuit comprising a voltage adjustment generation circuit;
A decoder circuit that selects and outputs positive and negative drive voltages corresponding to n pieces of data from the j positive and negative grayscale voltages based on the input grayscale signal;
A positive gradation voltage line comprising j positive gradation voltage lines provided in the first and second wiring layers and transmitting each of the j positive gradation voltages to the decoder circuit. Group,
A negative gradation voltage line formed of j negative gradation voltage lines provided in the first and second wiring layers and transmitting each of the j negative gradation voltages to the decoder circuit. A group, and
The positive gradation voltage line group and the negative gradation voltage line group are:
The positive polarity gradation voltage line for transmitting a positive polarity gradation voltage indicating a gradation level of k level (k is an integer satisfying a relation of 0 ≦ k <j / 2) is provided in the first wiring layer. The (k + j / 2) level gradation level is indicated in the region of the second wiring layer on the positive polarity gradation voltage line transmitting the positive gradation voltage indicating the k level gradation level. The positive polarity gradation voltage line transmitting positive polarity gradation voltage is arranged,
The first wiring layer is provided with the negative gradation voltage line for transmitting a negative gradation voltage indicating a k-level gradation level, and a negative gradation indicating the k-level gradation level. The negative gradation voltage line for transmitting a negative gradation voltage indicating a gradation level of (k + j / 2) level to the region of the second wiring layer on the negative gradation voltage line for transmitting a voltage. Are arranged so that
The source driver IC is characterized in that each of the positive polarity gradation voltage lines and each of the negative polarity gradation voltage lines are arranged adjacent to each other. A substrate having first and second wiring layers;
Positive polarity gradation voltage generation circuit and negative polarity step for generating j positive gradation voltages and j negative gradation voltages indicating gradation levels of j stages (j is an integer of 2 or more), respectively. A gradation voltage generation circuit comprising a voltage adjustment generation circuit;
A decoder circuit that selects and outputs positive and negative drive voltages corresponding to n pieces of data from the j positive and negative grayscale voltages based on the input grayscale signal;
A positive gradation voltage line comprising j positive gradation voltage lines provided in the first and second wiring layers and transmitting each of the j positive gradation voltages to the decoder circuit. Group,
A negative gradation voltage line formed of j negative gradation voltage lines provided in the first and second wiring layers and transmitting each of the j negative gradation voltages to the decoder circuit. A group, and
The positive gradation voltage line group and the negative gradation voltage line group are:
The positive polarity gradation voltage line for transmitting a positive polarity gradation voltage indicating a gradation level of k level (k is an integer satisfying a relation of 0 ≦ k <j / 2) is provided in the first wiring layer. Adjacent to the positive polarity gradation voltage line transmitting the positive polarity gradation voltage indicating the k level gradation level, and the negative polarity gradation voltage indicating the (k + j / 2) level gradation level. The negative gradation voltage line for transmitting
A negative gradation voltage indicating a k level gradation level in the region of the second wiring layer on the positive gradation voltage line transmitting a positive gradation voltage indicating the k level gradation level. The negative gradation voltage line for transmitting
In the second wiring layer, a (k + j / 2) level gradation level is shown adjacent to the negative polarity gradation voltage line that transmits the negative polarity gradation voltage indicating the k level gradation level. A source driver IC, characterized in that the positive driver grayscale voltage lines for transmitting a positive grayscale voltage are arranged. a substrate having l wiring layers;
Positive polarity gradation voltage generation circuit and negative polarity step for generating j positive gradation voltages and j negative gradation voltages indicating gradation levels of j stages (j is an integer of 2 or more), respectively. A gradation voltage generation circuit comprising a voltage adjustment generation circuit;
A decoder circuit that selects and outputs positive and negative drive voltages corresponding to n pieces of data from the j positive and negative grayscale voltages based on the input grayscale signal;
A positive grayscale voltage line group comprising j positive grayscale voltage lines provided in the wiring layer and transmitting each of the j positive grayscale voltages to the decoder circuit;
A negative gray scale voltage line group comprising j negative gray scale voltage lines provided in the wiring layer and transmitting each of the j negative gray scale voltages to the decoder circuit. ,
The positive gradation voltage line group and the negative gradation voltage line group are:
A level of (k + j / l) level is transmitted on the positive polarity gradation voltage line for transmitting a positive polarity gradation voltage indicating a gradation level of k level (k is an integer satisfying a relationship of 0 ≦ k <j / 2). Arranged so that the positive gradation voltage line for transmitting the positive gradation voltage indicating the gradation level is disposed,
The source driver IC is characterized in that each of the positive polarity gradation voltage lines and each of the negative polarity gradation voltage lines are arranged adjacent to each other.

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