JP2016058998A - Feedback type pulse width modulation a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-resolution feedback type pulse width modulation A/D converter that can reduce quantization noise folded to a neighborhood of DC by thinning-out processing.SOLUTION: A feedback type pulse width modulation A/D converter containing a feedback type pulse width modulator for converting an analog signal to a pulse width signal has a folding preventing filter which is connected to a rear stage of the feedback type width modulator to remove noise which is folded to a DC side due to thinning-out, a thinning-out circuit for thinning out the output data of the folding preventing filter at a pre-determining thinning-out frequency, and a digital filter which is connected to the thinning-out circuit and remove noise of an unnecessary band from the output data of the thinning-out circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a feedback type pulse width modulation A / D converter, and more particularly to improvement of the resolution.

  Feedback type pulse width modulation A / D converters are widely used in various measuring instruments as high-precision A / D converters.

  4A and 4B are block diagrams showing an example of a conventional feedback type pulse width modulation device. FIG. 4A is a detailed configuration diagram, and FIG. 4B is a schematic configuration diagram of FIG. In FIG. 4, the feedback type pulse width modulation apparatus generally includes a clock generation that outputs a feedback type pulse width modulator (hereinafter also referred to as PWM) 10, a counter 20, a digital filter 30, and a clock pulse fCLK having a predetermined frequency. And a carrier wave generator 50 for outputting a predetermined rectangular wave.

  The PWM 10 includes an operational amplifier 11 that functions as an integrator, a comparator 12, a flip-flop 13, a gate 14, and the like.

  A carrier wave generator 50 is connected to the inverting input terminal of the operational amplifier 11 via a series circuit of an inverter INV, a resistor R1, and a capacitor C1, and an input terminal Tin to which an input signal Vin is input via a resistor R2. A changeover switch SW is connected via a resistor R3. Note that the resistance values of the resistors R2 and R3 are set equal to R.

  The reference voltage + Vs is input to one fixed contact of the changeover switch SW, and the reference voltage -Vs is input to the other fixed contact.

  An integrating capacitor C2 is connected between the inverting input terminal and the output terminal of the operational amplifier 11, and the non-inverting input terminal is connected to a common potential point.

  The output terminal of the operational amplifier 11 is connected to the non-inverting input terminal of the comparator 12, the inverting input terminal is connected to the common potential point, and the output terminal is connected to the D terminal of the flip-flop 13 configured as a D type. Yes.

  The clock signal fCLK output from the clock generator 40 is input to the clock terminal of the flip-flop 13, the output terminal Q is connected to the switching control terminal of the changeover switch SW, and the edges constituting the gate 14 and the digital filter 30. It is connected to the input terminal of the overflow detector 34.

  The gate 14 has three input terminals and one output terminal. The clock signal fCLK, the output signal of the flip-flop 13 and the gate signal GATE are input to each input terminal, and the output terminal is the clock input of the counter 20. Connected to the terminal.

  The digital filter 30 includes a multiplier 31, an adder 32, a register 33, an edge overflow detector 34, a coefficient generator 35, a timing control circuit 36, and the like.

  The output terminal of the counter 20 is connected to one input terminal of the multiplier 31, and the output terminal of the coefficient generator 35 is connected to the other input terminal. The output terminal of the multiplier 31 is connected to one input terminal of the adder 32.

  The other input terminal of the adder 32 is connected to the output terminal of the register 33. The output terminal of the adder 32 is connected to the input terminal of the register 33 and to the outside.

  The output terminal of the edge overflow detector 34 is connected to the counter 20, the coefficient generator 35, and the timing control circuit 36.

  The output terminal of the coefficient generator 35 is connected to the other input terminal of the multiplier 31.

  The output terminal of the timing control circuit 36 is connected to the control terminal of the register 33 and the control terminal of the coefficient generator 35.

  In such a configuration, the input signal Vin is converted into a pulse width signal by the PWM 10, and then the pulse width signal is converted into a digital value by the counter 20 for each PWM carrier period output from the carrier generator 50. The digital filter 30 removes noise components from the pulse width signal converted into a digital value and improves the resolution.

  Specifically, the output pulse width of the PWM modulator is quantized to an integral multiple of the period of the counter clock fCLK by the D-type flip-flop 13 that forms the feedback loop of the modulator. At this time, the input converted quantization noise is divided by the “gain of the integrator 11” by the integrator 11 provided in the previous stage of the flip-flop 13, so that the primary noise shaping characteristic (6 dB / oct) and It has become.

  On the other hand, obtaining the pulse width for each period of the PWM carrier by the counter 20 is obtaining a value proportional to the section average value of the PWM signal, which is a simple moving average type FIR low-pass filter (the averaging time is This operation is equivalent to the case where re-sampling (decimation) is performed at the frequency of the PWM carrier wave after removing the carrier wave component by the PWM carrier wave period).

JP-A-9-205368

  Patent Document 1 discloses an invention related to a feedback type pulse width modulation A / D converter.

  However, in such a conventional feedback type pulse width modulation A / D converter, since the pulse width modulator has a first-order noise shaping characteristic, even if the subsequent digital filter has a steep characteristic, it is within the passband. The quantization noise is relatively large, and it is difficult to improve the resolution.

  Even when high-order noise shaping characteristics are given to the pulse width modulator, the value obtained by using the counter for the pulse width for each carrier period is used as the input of the digital filter. Noise in the vicinity of harmonics is folded back into the pass band of the digital filter, and higher-order noise shaping characteristics are lost, so that the resolution cannot be improved.

  Here, obtaining a pulse width for each carrier period using a counter is equivalent to performing a simple moving average type filter operation and a thinning operation for each carrier period simultaneously. The frequency characteristic of the filter is sin (f) / f. In addition to the low-pass characteristic of approximately 6 dB / oct, there is a first-order transmission zero (attenuation pole) in the decimation frequency and its harmonics. It is a characteristic to do.

  As described above, since there is transmission zero at the thinning frequency and the harmonic frequency thereof, the noise component matching the frequency is removed, and even if the thinning operation is performed, it is not folded back to DC.

  On the other hand, noise at a frequency slightly away from the thinning frequency remains with an amplitude proportional to the frequency difference Δf from the thinning frequency. Then, by performing a thinning operation, the frequency is converted (turned back) in the vicinity of the direct current and appears in the pass band of the subsequent digital filter.

  This phenomenon is caused by the resolution of the A / D converter when the noise shaping characteristic of the PWM modulator is the first order (6 dB / oct) characteristic as in the conventional example, and the amplitude is about the same as the original noise. There is no big impact.

  However, if the PWM modulator transfer function is second order or higher and the noise shaping characteristic of second order (12 dB / oct) or higher is given to the quantization noise, the noise that is folded back to the vicinity of the direct current by decimation It is overwhelmingly larger than the noise in the vicinity of the direct current, and the overall S / N ratio is determined by the noise caused by the aliasing regardless of the noise shaping characteristics of the modulator.

  As a result, the effect of giving the second or higher order noise shaping characteristics to the modulator is lost.

  The present invention solves such a problem, and an object of the present invention is to provide a high-resolution feedback pulse width modulation A / D converter by reducing quantization noise that is turned back to the vicinity of DC by thinning processing. It is to provide.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a feedback type pulse width modulation A / D converter including a feedback type pulse width modulator that converts an analog signal into a pulse width signal,
An anti-aliasing filter that is connected to the subsequent stage of the feedback type pulse width modulator and removes noise that is aliased to the DC side as a result of decimation;
A decimation circuit that decimates output data of the anti-aliasing filter at a predetermined decimation frequency, and a digital filter that is connected to the decimation circuit and removes unnecessary band noise from the output data of the decimation circuit.

The invention according to claim 2
In the feedback type pulse width modulation A / D conversion device according to claim 1,
The feedback pulse width modulator has at least a second-order noise shaping characteristic.

The invention described in claim 3
In the feedback type pulse width modulation A / D conversion device according to claim 1,
A filter process of the anti-folding filter and a thinning process of the thinning circuit are performed in combination.

  According to the present invention, it is possible to realize a high-resolution feedback pulse width modulation A / D converter by reducing quantization noise that is turned back to the vicinity of a direct current in thinning processing.

It is a block diagram which shows one Example of this invention. It is a block diagram of a moving average type FIR filter. It is a characteristic example figure of a digital filter. It is a block diagram which shows an example of the conventional feedback type pulse width modulator.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals are given to portions common to FIG. In FIG. 1, the anti-aliasing filter 60 is connected to the output terminal of the PWM 10, the thinning circuit 70 is connected to the output terminal of the anti-aliasing filter 60, and the digital filter 80 is connected to the output terminal of the thinning circuit 70. .

  The PWM carrier generator 50 generates and outputs a PWM carrier signal EC having a predetermined frequency that determines the frequency of the PWM signal, and the output signal EC is input to the PWM 10.

  The feedback pulse synchronization signal generator 90 generates and outputs a feedback pulse synchronization signal fCLK corresponding to a conventional count clock, and the output signal fCLK is input to the PWM 10 and the anti-aliasing filter 60.

  The decimation clock generator 100 generates and outputs a decimation clock signal fDEC for decimation of data output from the anti-aliasing filter 60 to the digital filter 80, and the clock signal fDEC is input to the decimation circuit 70 and the digital filter 80. Has been.

The apparatus configured as shown in FIG. 1 operates in the following four steps S1 to S4.
S1) An analog input signal is input to the PWM 10 and converted into a PWM signal.
S2) The PWM signal is input to the anti-aliasing filter 60.
S3) The output of the anti-folding filter 60 is input to the thinning circuit 70 and thinned.
S4) The output of the thinning circuit 70 is input to the digital filter 100 to remove unnecessary band noise, and the quantization noise biased to the high band side due to the effect of the noise shaping characteristics of the PWM 10 is also removed.

The operations of these steps S1 to S4 will be described in detail.
S1) An analog input signal is input to the PWM 10 and converted into a PWM signal.
As in FIG. 4, a PWM carrier signal EC having a predetermined frequency that determines the frequency of the PWM signal is input to the PWM 10 from the PWM carrier generator 50.

  The PWM 10 is supplied with a feedback pulse synchronization signal fCLK corresponding to a conventional count clock from the feedback pulse synchronization signal generator 90, and the pulse width is quantized to an integral multiple of the feedback pulse synchronization signal fCLK.

  Although quantization noise is generated by this quantization, it is possible to give a noise shaping characteristic of the second or higher order by cascading two or more integrators in the PWM 10, for example. Can be attenuated.

S2) The PWM signal is input to the anti-aliasing filter 60.
The input to the anti-aliasing filter 60 is a 1-bit PWM signal, but the output is a multi-bit signal.

  The anti-folding filter 60 removes the frequency of the subsequent thinning circuit 70 and its harmonics or noises in the vicinity of those frequencies while passing a direct current, thereby preventing noise caused by the folding caused by the thinning process.

  The frequency characteristic of the moving average type FIR filter is sin (f) / f, which is a so-called comb filter that allows a DC component to pass and blocks a frequency component having a period of 1 / integer of the averaging time. Since it has both characteristics and low-pass characteristics, it is close to the desired characteristics, but sufficient attenuation characteristics cannot be obtained with one stage.

  The characteristic necessary for the “anti-folding filter” block can be obtained, for example, by cascading two or more moving average FIR filters. It is desirable that the number of cascaded stages of the FIR filter is equal to or slightly larger than the noise shaping order of the PWM 10.

  FIG. 2 is a diagram illustrating the configuration of a moving average FIR filter having a width of n, and is an example of one stage of moving average. Here, n is equal to the thinning rate or is an integer multiple thereof.

  As a result, noise that is turned back to the direct current side when a thinning operation is performed by the thinning circuit 70 in the subsequent stage is removed, and the noise shaping characteristics of the PWM 10 become effective.

S3) The output of the anti-folding filter 60 is input to the thinning circuit 70 and thinned.
The decimation circuit 70 receives the decimation clock fDEC from the decimation clock generator 100 and decimates data accordingly. By performing data thinning by the thinning circuit 70, the calculation amount of the digital filter 80 at the subsequent stage of the thinning circuit 70 can be suppressed.

  In the conventional configuration shown in FIG. 4, the value of the counter 20 is input to the digital filter 30 at every change timing of the PWM carrier signal EC input from the PWM carrier generator 50. This is because the PWM carrier signal EC is thinned out. It is thought that he also served as a clock.

  In the present invention shown in FIG. 1, the PWM carrier signal EC and the thinned-out clock fDEC can be matched as in FIG. 4, but even if they do not match, the PWM carrier signal EC or Since a characteristic that sufficiently attenuates the aliasing component can be provided, the PWM carrier signal EC and the thinning-out clock fDEC do not need to have the same frequency.

  S4) The output of the thinning circuit 70 is input to the digital filter 100 to remove unnecessary band noise, and the quantization noise biased to the high band side due to the effect of the noise shaping characteristics of the PWM 10 is also removed.

  In order to effectively remove the quantization noise, it is desirable that the cutoff characteristic of the digital filter 100 matches the order of noise shaping of the PWM 10 or is a low-pass characteristic having a slightly higher order.

  When the present invention is applied to a measuring instrument, it has a desired characteristic by operating in the same manner as in the prior art with the same configuration as in FIG. 4, that is, by operating to obtain the sum of products for each period of output data. A filter can be realized.

  In general, a feedback type pulse width A / D converter using PWM has a lower switching frequency than a ΔΣ A / D converter using a ΔΣ modulator, and thus is likely to be highly accurate.

  A feedback type PWM that is a component of this feedback type pulse width A / D converter is used with a secondary (or higher) noise shaping characteristic, and the PWM signal obtained from the feedback type PWM is thinned out by an anti-aliasing filter. By sufficiently attenuating the frequency, its harmonics, and nearby noise components, and performing the thinning operation on the signal, the amount of data can be reduced while preventing the introduction of aliasing noise due to thinning, and the feedback type PWM Can be input to the digital filter while maintaining the secondary (or higher) noise shaping characteristics.

  As a result, the quantization noise biased to a high frequency by noise shaping can be effectively removed by the subsequent digital filter, and an A / D converter having a high S / N ratio, that is, a high resolution can be obtained. .

  Further, since the amount of data can be reduced by thinning, it is possible to reduce the amount of calculation required to obtain a desired filter characteristic when a digital filter is configured.

  As the anti-aliasing filter 60, an FIR filter that obtains an impulse response from its frequency characteristics and performs a convolution operation of the impulse response can be used. In this case, it is only necessary to perform decimation at the same time as the filter operation and to perform a product-sum operation for convolution only on data remaining after decimation. Here, if the fact that the PWM signal is binary of 1.0 is used, it can be realized without using a multiplier.

  Also, a filter known as a CIC filter (cascaded integrator comb) that simplifies the filter operation widely used for the same purpose in the ΔΣ A / D converter by combining the subsequent thinning process and the filter operation. However, the anti-folding filter 60 used in the present invention is not limited to these configurations.

When the A / D converter is applied to a DC measuring instrument such as a digital voltmeter, it is particularly necessary to remove the noise of the commercial power supply frequency. This commercial power supply frequency has a 50 Hz region and a 60 Hz region. Conventionally, it has been supported by at least one of the following methods a) to c).
A) Use a 100 ms interval average that can obtain a high attenuation rate for both 50 Hz and 60 Hz. B) Enable the user to select the frequency to be removed. C) Switch the filter characteristics by measuring the power supply frequency.

  Here, by setting the coefficient of the digital filter 100 to a value based on the impulse response when a moving average of 20 ms, 16.67 ms, and 12.91 ms is cascaded, as shown in the characteristic example diagram of FIG. Although it is relatively fast at 50 ms, a high attenuation rate can be obtained at 50 Hz, 60 Hz, 77.5 Hz and its harmonics, so switching by the power supply frequency is not required, and favorable characteristics can be obtained for a DC measuring instrument.

  As described above, according to the present invention, it is possible to realize a high-resolution feedback pulse width modulation A / D converter by reducing the quantization noise that is turned back to the vicinity of the direct current by the thinning process. Suitable for a DC signal generator or the like.

DESCRIPTION OF SYMBOLS 10 Feedback type pulse width modulator 60 Anti-folding filter 70 Decimation circuit 80 Digital filter 90 Feedback pulse synchronous signal generator 100 Decimation clock generator

Claims (3)

In a feedback type pulse width modulation A / D converter including a feedback type pulse width modulator that converts an analog signal into a pulse width signal,
An anti-aliasing filter that is connected to the subsequent stage of the feedback type pulse width modulator and removes noise that is aliased to the DC side as a result of decimation;
A thinning circuit for thinning out the output data of the anti-aliasing filter at a predetermined thinning frequency;
A feedback-type pulse width modulation A / D converter characterized by comprising a digital filter connected to the thinning circuit and removing unwanted band noise from the output data of the thinning circuit.   2. The feedback type pulse width modulation A / D converter according to claim 1, wherein the feedback type pulse width modulator has at least a secondary noise shaping characteristic.   2. The feedback type pulse width modulation A / D converter according to claim 1, wherein filtering processing of the anti-folding filter and thinning processing of the thinning circuit are performed in combination.