JP2004007827A - Analog / digital converter and analog / digital converting method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog / digital converter for avoiding occurrence of an idle tone by adding a DC component to an analog input signal wherein no added DC component is included in an outputted digital output signal. <P>SOLUTION: The analog / digital converter includes: a conversion means 5 for converting an analog input signal and outputting a noninverting signal and an inverting signal; a first analog summing means 6 applying summation processing to the noninverting signal and the DC component; a balancing circuit 3 comprising a second analog summation means 7 for applying summation processing to the inverting signal and the DC component; a first ΔΣanalog / digital conversion circuit 1 for receiving the noninverting signal outputted from the balancing circuit 3; a second ΔΣanalog / digital conversion circuit 2 for receiving the inverting signal outputted from the balancing circuit 3; and a digital subtraction means 4 for applying subtraction processing to the digital signals outputted from the first and second ΔΣanalog / digital conversion circuits 1 and 2. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an A / D (analog / digital) converter for converting an analog signal to a digital signal and a conversion method thereof, and more particularly to an improvement in noise characteristics of a ΔΣ A / D conversion circuit.

As one of the 装置 A / D converters, an A / D converter using a ΔΣ A / D converter has been proposed. For example, there is an A / D conversion circuit as disclosed in Patent Document 1. Hereinafter, an A / D conversion device using a conventional ΔΣ A / D conversion circuit will be described.

FIG. 5 is a block diagram showing a configuration of a conventional A / D converter. 50 is a ΔΣ A / D conversion circuit, 51 is an analog subtractor, 52 is an integrator, 53 is a quantizer that quantizes an input signal into 1 bit, 54 is a D-type flip-flop (hereinafter, referred to as DFF), 55 is a D / A converter.

FIG. 6 is a block diagram showing the configuration of the integrator 52. In FIG. 6, reference numeral 56 denotes an analog adder, and 57 denotes a delay unit that delays by one sampling period. The input signal from the analog subtractor 51 outputs an output signal to the quantizer 53 via the analog adder 56, and is positively fed back to the analog adder 56 via the delay unit 57. That is, the input signal is cumulatively added for each sampling period, and the transfer characteristic Hi (z) is represented by a Z function as shown in (Equation 1).

Hi (z) = 1 / (1-z-1) (Equation 1)
Where z = cos θ−j · sin θ
j: Imaginary unit The operation of the conventional A / D converter configured as described above will be described below with reference to FIGS. The analog input signal is input to an integrator 52 via an analog subtractor 51, is cumulatively added by an analog adder 56 in the integrator 52, and then is quantized by a quantizer 53 at +1 and −1 every sampling period. It is quantized to a digital signal of a value (1 bit). The quantized digital signal is output as a digital output signal, is input to the D / A converter 55 via the DFF 54, and is converted into a binary (1 bit) analog signal of + Vt and -Vt. Thereafter, the signal is fed back to the analog subtractor 51.

When the analog input signal of the ΔΣ type A / D conversion circuit 50 is X, the digital output signal is Y, and the quantization error generated by the quantizer 53 (the difference between the input and output of the quantizer 53) is Vqn, Is described by the Z function as (Equation 2).

Y = X + (1-z-1) Vqn (Formula 2)
As is apparent from (Equation 2), the digital output signal Y includes a term of the quantization error Vqn in addition to the analog input signal component X, but is multiplied by the first-order differential characteristic (1-z-1). Therefore, the noise due to Vqn decreases as the frequency decreases, and a wide dynamic range can be obtained in the low frequency region even with only 1-bit quantization.

To obtain a wider dynamic range, A / D conversion is performed with a shorter sampling period (higher sampling frequency) than the digital output signal to be obtained, and the output is digitally processed to use only the low frequency region. do it. For this reason, this method is also called an oversampling method, and is widely applied especially in the digital audio field.
JP-A-2-126727

However, in the above-described conventional configuration, when a DC component (DC voltage) is applied to an analog input signal, the digital output signal has a characteristic of having a periodicity, and as a result, originally does not have a frequency characteristic (white). There is a problem that a specific frequency component (idle tone) appears in the noise Vqn.

発 生 The principle of occurrence of this problem will be briefly described with reference to FIG. FIG. 7 is a waveform diagram of an input signal and an output signal of the quantizer 53 of the ΔΣ A / D conversion circuit 50.

{First, when the DC component Vdc is input to the ΔΣ type A / D conversion circuit 50, the DC component Vdc is cumulatively added by the integrator 52 and input to the quantizer 53. When the input signal exceeds a predetermined threshold value, the quantizer 53 inverts the output signal and feeds it back to the analog subtractor 51, so that the input waveform of the quantizer 53 becomes a sawtooth wave as shown in FIG. , And the output waveform is a pulse train.

パ ル ス The pulse interval at this time is a fixed period determined by the ratio of the input DC component Vdc to the quantized output Vt, and the period t0 is represented by (Equation 3).

t0 = Ts × Vt / Vdc (Equation 3)
However, Vdc: DC component (DC voltage)
Ts: Sampling period Since the pulse train has a constant period t0 as described above, a fundamental frequency 1 / t0 and an integer multiple (harmonic) noise appear in the digital output signal. This is generally called an idle tone. This idle tone does not appear unless there is a DC component in the input signal, but it is extremely difficult to completely remove the DC component from the analog input signal, and the DC component of the A / D converter circuit itself has a DC component. The effects are also difficult to avoid.

The simplest way to avoid the idle tone is to add the DC component Vdc so that the frequency of the idle tone determined by (Equation 3) falls outside the desired signal band.

As described above, in the ΔΣ A / D converter circuit, a low frequency region in which a wide dynamic range can be obtained is used as a signal band. Therefore, the fundamental frequency 1 / t0 of the idle tone is higher than the upper limit frequency of this signal band. Higher is better.

However, if this means is simply used, the digital output signal naturally includes the added DC component Vdc, and a problem arises in that digital processing for removing the DC component Vdc is required separately. In order to remove the DC component Vdc contained in the digital output signal, it is necessary to first obtain the DC value. However, when the DC value is obtained only from the digital output signal and removed, the DC component contained in the original analog input signal is removed. Until it is removed. It is also possible in principle to obtain the DC value included in the digital output signal in advance from the ratio of the DC component Vdc to be added and the quantized output Vt and to remove the DC value. It is not easy to remove the DC component with sufficient accuracy by, for example, the following. It is even more difficult considering the current situation in which various means are taken to remove the DC component of the A / D conversion circuit itself.

The present invention solves the above-mentioned conventional problems, and avoids an idle tone by adding a DC component to an analog input signal, and includes an added digital component in the output digital output signal. It is an object of the present invention to provide an A / D conversion device that does not have a function.

A first A / D converter according to the present invention, which converts an analog signal into a positive-phase signal and a negative-phase signal, and then adds the same DC component to the positive-phase signal and the negative-phase signal; A first ΔΣ type A / D converter circuit that receives a positive-phase signal output from the balance circuit and a second ΔΣ type A / D converter circuit that receives a negative-phase signal output from the balance circuit And digital subtraction means for subtracting digital signals output from the first and second ΔΣ-type A / D conversion circuits, wherein the first and second ΔＡ-type A / D conversion circuits are the same. It has a circuit configuration.

According to the first configuration, after converting an analog signal into a positive-phase signal and a negative-phase signal, the same DC component is added to the positive-phase signal and the negative-phase signal, and A / D conversion is performed. Since the frequency of the idle tone component included in the output of the / D conversion circuit is out of the predetermined signal band, the idle tone (noise) can be avoided. Moreover, the DC component added to the positive-phase signal and the negative-phase signal is canceled by the subtraction processing by the digital subtraction means, so that a digital output signal that does not include the added DC component can be obtained.

In a second A / D converter according to the present invention, the first A / D converter converts an analog signal of a quantization error component output from the first and second ΔΣ-type A / D conversion circuits. Analog subtraction means for performing subtraction processing, a third ΔΣ-type A / D conversion circuit which receives an analog signal output from the analog subtraction means, and a digital signal output from the third ΔΣ-type A / D conversion circuit It is characterized by comprising a differentiating means for receiving a signal and differentiating the digital signal, and a digital adding means for adding an output from the digital subtracting means and an output from the differentiating means.

According to the second configuration, the operation and effect of the first configuration can be achieved only by adding a third ΔΣ A / D conversion circuit, a differentiating unit, an analog subtracting unit, and a digital adding unit to the first configuration. In addition, an A / D conversion circuit having a second-order differential characteristic can be configured.

A third A / D converter according to the present invention is the above-mentioned second A / D converter, wherein the fourth to n-th ΔΣ A / D conversion circuits and the fourth to n-th ΔΣ A / D conversion circuit, which is connected to the output of the / D conversion circuit, respectively, for differentiating the digital signal output from the fourth to nth ΔΣ A / D conversion circuits into a predetermined differential characteristic. And a differentiating means (an integer of n ≧ 4), wherein the fourth to n-th ΔΣ A / D conversion circuits are output from the third to (n−1) th ΔΣ A / D conversion circuits. An analog signal of a quantization error component is input, and outputs from the fourth to n-th differentiating means are input to a digital adding means for addition processing.

According to the third configuration, the second A / D converter includes the ΔΣ A / D conversion circuit and the differentiating means for the ΔΣ A / D conversion circuit as one set of circuits. When added, a circuit having a third-order differential characteristic is formed, and when two sets are added, a circuit having a fourth-order differential characteristic can be formed. That is, if the (n-3) sets of circuits including the fourth to n-th ΔΣ A / D conversion circuits and the fourth to n-th differentiating means are added, in addition to the effects of the second configuration, An A / D conversion circuit having (n-1) th order differential characteristics can be configured.

Any one of the balance circuits of the first to third A / D converters converts an analog input signal to output a positive-phase signal and a negative-phase signal; First analog adding means for performing addition processing and outputting the result to the first ΔΣ A / D conversion circuit; and performing second addition processing of the antiphase signal and the DC component to perform second ΔΣ A / D conversion. And a second analog adding means for outputting to the circuit.

Using this balance circuit, after converting an analog signal into a positive-phase signal and a negative-phase signal, the same DC component can be added to the positive-phase signal and the negative-phase signal by analog adding means. At this time, the DC component superimposed on the analog input signal is subjected to A / D conversion as it is and is included in the digital output signal and output.

The balance circuit of any of the first to third A / D converters may include a capacitor for inputting an analog input signal, an output from the capacitor being an input of an inverting input terminal, and a DC component being a non-inverting input. A first inverting amplifier circuit having a first operational amplifier as an input of a terminal, an output from the first inverting amplifier circuit being an input of an inverting input terminal, and a DC component identical to the DC component being a non-inverting input. A second inverting amplifying circuit having a second operational amplifier as an input of a terminal, wherein the first and second inverting amplifying circuits have the same circuit configuration. A negative-phase signal to which the DC component is added is output, and a positive-phase signal to which the DC component is added is output from the second inverting amplifier circuit. Further, the input resistance and the feedback resistance included in the first and second inverting amplifier circuits have the same resistance value.

If this balanced circuit is used, the DC component superimposed on the analog input signal is removed by a capacitor, and the same DC component is used for the positive-phase signal and the negative-phase signal with a simple circuit configuration without using an adder. Can be added. Therefore, after the A / D conversion, a digital output signal of only the AC component not including the DC component superimposed on the analog input signal is obtained.

An A / D conversion method for an A / D conversion device according to the present invention is the A / D conversion method for an A / D conversion device having a ΔΣ A / D conversion circuit. And adding the same DC component to the positive-phase signal and the negative-phase signal, and then performing A / D conversion, and performing a subtraction process between the A / D-converted positive-phase signal and the negative-phase signal. The DC component added is removed.

According to this A / D conversion method, after converting an analog signal into a normal-phase signal and a negative-phase signal, the same DC component is added to the normal-phase signal and the negative-phase signal, and then A / D-converted. The frequency of the idle tone component included in the / D conversion output falls outside the predetermined signal band, and the idle tone can be avoided. In addition, the DC component added to the positive-phase signal and the negative-phase signal is canceled by subtraction before obtaining a digital output signal, so that a digital output signal that does not include the added DC component can be obtained.

{Circle around (2)} The A / D conversion method is characterized in that, after removing a DC component superimposed on the analog input signal with a capacitor, the analog input signal is converted into a positive phase signal and a negative phase signal.

According to this A / D conversion method, the DC component superimposed on the analog input signal is removed by the capacitor, and after the A / D conversion, only the AC component not including the DC component superimposed on the analog input signal is removed. Is obtained.

According to the A / D converter and the A / D conversion method of the present invention, a DC component is added to an analog input signal to effectively avoid an idle tone, and the added DC component obtains a digital output signal. Since the digital output signal is canceled and removed by the subtraction process before, it has an excellent feature that the added DC component is not included in the output digital output signal.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of the A / D converter according to Embodiment 1 of the present invention. In FIG. 1, reference numerals 1 and 2 denote ΔΣ A / D conversion circuits having the same circuit configuration, 3 denotes a balance circuit, and 4 denotes a digital subtractor. The ΔΣ A / D conversion circuits 1 and 2 are blocks having the same configuration and function as the A / D conversion circuit 50 shown in FIG. The balance circuit 3 adds an inverting amplifier circuit 5 that outputs a positive-phase (in-phase) signal of the analog input signal and a negative-phase signal whose sign is inverted, and adds the positive-phase signal and the DC component Vdc to perform ΔΣ A / D conversion. It comprises an analog adder 6 that outputs to the circuit 1, and an analog adder 7 that adds the negative phase signal and the DC component Vdc and outputs the result to the A / D converter 2. The digital subtractor 4 subtracts the outputs from the ΔΣ A / D converter 1 and the ΔΣ A / D converter 2 and outputs the result.

一 An example of the operation of the A / D converter according to the first embodiment configured as described above will be described below.

First, the analog input signal is converted into a positive-phase signal and a negative-phase signal by the inverting amplifier circuit 5 of the balance circuit 3, and then the positive-phase signal and the DC component Vdc are added by the analog adder 6. , The negative-phase signal and the DC component Vdc are added.

Therefore, assuming that the analog input signal is X, the positive-phase signal input to the ΔΣ A / D conversion circuit 1 is (X + Vdc), and the negative-phase signal input to the ΔΣ A / D conversion circuit 2 is (− X + Vdc). These signals are converted into digital signals by the ΔΣ A / D conversion circuit 1 and the ΔΣ A / D conversion circuit 2, and then output to the digital subtractor 4. Since the input signal is subtracted in the digital subtractor 4, the DC component Vdc added by the balance circuit 3 is canceled out and included in the output of the signal component of the digital output signal as is apparent from (Equation 4). No longer.

(X + Vdc)-(-X + Vdc) = 2X (Equation 4)
Moreover, even if the DC component Vdc fluctuates due to a manufacturing error, a temperature drift, or the like, the same DC component Vdc is included in the positive-phase signal and the negative-phase signal output from the balance circuit 3, so that the digital component is processed by the digital subtractor 4. It does not affect the cancellation of the DC component.

In the first embodiment, the balance circuit 3 has been described using the circuit constituted by the inverting amplifier circuit 5 and the analog adders 6 and 7. However, as described above, the analog input signal is converted to the positive-phase signal and the reverse-phase signal. The same effect can be obtained as long as the conversion means has a function of adding the same DC component to the positive-phase signal and the negative-phase signal and outputting the same after conversion into a signal.

(Embodiment 2)
Next, an A / D converter according to a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a configuration of a balanced circuit according to the A / D converter of the second embodiment. By using the balance circuit 12 shown in FIG. 2 instead of the balance circuit 3 in the first embodiment shown in FIG. 1, when the DC component included in the analog input signal is unnecessary, the direct current can be easily corrected without using an adder. The same DC component can be added to the phase signal and the negative phase signal.

に お い て In FIG. 2, 13 and 14 are operational amplifiers (operational amplifiers), 15 and 16 are input resistors, 17 and 18 are feedback resistors, and 19 is a capacitor. The input resistors 15, 16 and the feedback resistors 17, 18 are all resistors having the same resistance value R.

The balance circuit 12 includes a first inverting amplifier circuit 20 including three elements of an operational amplifier 13, an input resistor 15 and a feedback resistor 17, and a second inverting amplifier circuit including three elements of an operational amplifier 14, an input resistor 16, and a feedback resistor 18. 21 are connected in series, and the analog input signal is supplied to the first inverting amplifier circuit 20 via the capacitor 19. The same DC component Vdc is input to the non-inverting input terminals of the operational amplifiers 13 and 14.

With the above configuration, the inverted signal is output from the first inverting amplifier circuit 20 as an output signal, and is also input as an input signal of the second inverting amplifier circuit 21 connected in series, and 21 outputs a normal-phase signal as an output signal.

動作 An example of the operation of the balanced circuit 12 according to the second embodiment configured as described above will be described below.

Since the input resistor 15 and the feedback resistor 17 of the first inverting amplifier circuit 20 and the input resistor 16 and the feedback resistor 18 of the second inverting amplifier circuit 21 are all resistors having the same resistance value R, the amplification factor (Gain) is “1”. Further, since the analog input signal is input to the first inverting amplifier circuit 20 via the capacitor 19, the DC component superimposed on the analog input signal is removed by the capacitor 19, and the analog input signal output from the capacitor 19 Assuming that the AC component is Xo, the positive-phase signal output and the negative-phase signal output are signals shown in (Equation 5), and the DC component Vdc can be added to be equal to the AC component Xo of the analog input signal.

Normal phase signal output = + Xo + Vdc
Negative phase signal output = −Xo + Vdc (Equation 5)
In the second embodiment, for the sake of simplicity, the description has been made using the resistors having the same resistance value R so that the amplification factor becomes “1”. A different circuit configuration may be used as long as the addition function is not impaired. For example, the gain can be changed by changing the resistance value of the resistor 15, and the frequency characteristic can be provided by connecting a capacitor in parallel with any one of the resistors.

In the description of the first embodiment and the second embodiment, the accuracy of each analog element and the DC component of the operational amplifier are ignored. The output signal contains a DC component. Particularly, in an operational amplifier of a CMOS integrated circuit, a DC component generated due to a manufacturing error, a temperature drift, or the like is at a level that cannot be ignored. Conventionally, when an A / D converter is configured by a CMOS integrated circuit, digital processing is performed. It is almost indispensable to remove the DC component. However, if analog elements are arranged close to each other on the same integrated circuit, it is possible to obtain a relative accuracy much higher than the absolute accuracy. Utilizing this feature, if the above-mentioned ΔΣ A / D conversion circuit 1, ΔΣ A / D conversion circuit 2 and balance circuit 3 or balance circuit 12 are arranged close to each other on the same integrated circuit, generation by analog elements is achieved. The DC components are very close in relative value, and can be accurately canceled by the digital subtractor 4.

(Embodiment 3)
In the A / D converter shown in FIG. 5, the differential characteristic multiplied by Vqn is a first-order characteristic as shown in (Equation 2), and the noise suppression amount in the low frequency region is not always sufficient. Circuits having up to fourth order differential characteristics are often used. Needless to say, the circuit configuration of the third to fourth order differential characteristics is more complicated and large-scale than the circuit configuration of the first order differential characteristics. Therefore, if a circuit using two identical ΔΣ-type A / D conversion circuits as shown in FIG. 1 and simply obtaining a differential characteristic higher than the secondary characteristic is formed, the circuit scale becomes twice or more. . Therefore, in the A / D converter according to the third embodiment, a circuit configuration in which the A / D converter shown in FIG. 1 is used as a basic circuit and a secondary or higher-order differential characteristic can be obtained by adding only a small number of circuits. provide.

FIG. 3 is a block diagram showing a configuration of an A / D converter according to Embodiment 3 of the present invention. 3, blocks having the same configurations and functions as those in FIG. 1 are denoted by the same reference numerals. Reference numerals 1, 2, and 8 denote ΔΣ A / D conversion circuits having the same circuit configuration, 3 is a balance circuit, 4 is a digital subtractor, 9 is a differentiator, 10 is an analog subtractor, and 11 is a digital adder. The balancing circuit 3 adds the positive-phase signal and the DC component Vdc to the inverting amplifier circuit 5 that outputs a positive-phase (in-phase) signal of the analog input signal and a negative-phase signal whose sign is inverted, as in FIG. And an analog adder 7 that adds the negative-phase signal and the DC input Vdc and outputs the result to the ΔΣ A / D conversion circuit 2. I have.

The ΔΣ-type A / D conversion circuits 1, 2, and 8 convert analog signals input to the respective circuits into digital signals under the same sampling clock and output the digital signals, and simultaneously perform quantization error components (quantizer 53 Are output as analog signals Vq1, Vq2, Vq8 (Vq8 is not shown). The digital subtractor 4 receives digital output signals output from the ΔΣ A / D conversion circuit 1 and the ΔΣ A / D conversion circuit 2, performs subtraction processing, and outputs the result to the digital adder 11. The analog subtractor 10 receives the analog signals Vq1 and Vq2 of the quantization error component output from the ΔΣ A / D conversion circuit 1 and the ΔΣ A / D conversion circuit 2, performs a subtraction process, and then performs a ΔΣ A / D conversion. Output to the conversion circuit 8. The differentiator 9 receives the digital output signal output from the A / D conversion circuit 8 as input, performs ideal first-order differentiation, and outputs the result to the digital adder 11.

FIG. 4 is a block diagram showing the configuration of the differentiator 9 according to the present invention. In FIG. 4, 22 is a digital subtractor, and 23 is a DFF. The input signal from the ΔΣ type A / D conversion circuit 8 is directly input to the digital subtractor 22, and is input to the digital subtracter 22 after passing through the DFF 23, and is input from the input signal directly input to the digital subtracter 22. The signal input via the DFF 23 is subtracted and output to the digital adder 11. The transfer characteristic Hd of the differentiator 9 is represented by (Equation 6) using a Z function.

Hd (z) = 1−z−1 (formula 6)
In the A / D converter of FIG. 3, the operations and functions of the balance circuit 3, the ΔΣ A / D conversion circuit 1, the ΔΣ A / D conversion circuit 2, and the digital subtractor 4 are shown in FIG. The digital output signal Y1 from the digital subtractor 4 is as shown in (Equation 7).

Y1 = 2X + (1-z-1) (Vq1-Vq2) (Equation 7)
The digital output signal Y2 from the ΔΣ A / D conversion circuit 8 is as shown in (Equation 8).

Y2 = (Vq1-Vq2) + (1-z-1) Vq8 (Expression 8)
Further, the digital output signal Y2 from the ΔΣ A / D conversion circuit 8 is output to the digital adder 11 via the differentiator 9 and is added to the digital output signal Y1 from the digital subtractor 4 to obtain the digital output signal Y3 It becomes. Therefore, from (Equation 6), (Equation 7) and (Equation 8), the digital output signal Y3 is expressed by (Equation 9).

Y3 = Y1 + Hd * Y2 = 2X + (1-z-1) 2Vqn (Equation 9)
That is, as can be seen from (Equation 9), an A / D converter having secondary characteristics can be obtained. As described above, an A / D converter having a second-order differential characteristic can be realized by adding a small number of circuits to the A / D conversion circuit 50 of FIG.

Accordingly, the digital signal output obtained by subtracting the output from the ΔΣ A / D conversion circuit 1 and the ΔΣ A / D conversion circuit 2 by the digital subtractor 4 is converted into the ΔΣ A / D conversion circuit 8 and the differential signal. If the technical idea of obtaining a digital output signal having a second-order differential characteristic by adding digital output signals obtained by the detector 9 is developed, a digital output signal having a third-order differential characteristic can be easily obtained by adding a small number of circuits. be able to.

For example, a circuit configuration for obtaining a digital output signal having a third-order differential characteristic will be briefly described. A / D converter of FIG. 3 includes a ΔΣ A / D conversion circuit for a third-order characteristic and a differential A set of circuits consisting of a circuit is added, and the quantization error output Vq8 of the ΔΣ A / D conversion circuit 8 is input to the Δ 特性 A / D conversion circuit for tertiary characteristics, and the ΔΣ A / D conversion for tertiary characteristics is performed. The output from the circuit is output to the digital adder 11 via the tertiary characteristic differentiator and subjected to addition processing. In order to cancel the term of the quantization error Vq8 included in the digital output signal of the differentiator 9, the third-order characteristic differentiator needs to obtain the second-order differential characteristic. It is configured by connecting them in series.

That is, in the A / D converter shown in FIG. 3, a ΔΣ type A / D conversion circuit and a differentiator for the conversion circuit are provided as one set of circuits, and if one set is added, a circuit having a third-order differential characteristic is configured. By adding two sets, a circuit having fourth-order differential characteristics can be configured. Therefore, (n-3) sets of circuits including the fourth to n-th ΔΣ A / D conversion circuits and the fourth to n-th differentiating means are added, and the (n-3) sets of conversion circuits are output. By inputting the output to the digital adder 11 and performing an addition process, an A / D conversion circuit having (n-1) th-order differential characteristics can be configured (an integer of n ≧ 4).

In the third embodiment, the A / D conversion circuits shown in FIG. 5 have been described as the same circuits using the A / D conversion circuits 1, 2, and 8 as ΔΣ A / D conversion circuits. The point is that the DC component is canceled by subtracting the outputs of the / D conversion circuits 1 and 2 so that the ΔΣ A / D conversion circuits 1 and 2 need only be the same circuit, in order to obtain secondary characteristics or higher. The ΔΣ type A / D conversion circuit is not limited to this. For example, the ΔΣ A / D conversion circuit 8 may be a double integration circuit.

In the third embodiment, when a DC component included in an analog input signal is unnecessary, a balanced circuit 12 shown in FIG. 2 may be used instead of the balanced circuit 3 as in the second embodiment.

The A / D conversion device and the A / D conversion method of the present invention effectively avoid idle tones by adding a DC component to an analog input signal, and the added DC component is obtained before a digital output signal is obtained. The digital output signal, which is canceled and removed by the subtraction processing and output, does not include the added DC component, and is useful for improving the noise characteristics of the ΔΣ A / D conversion circuit.

FIG. 1 is a block diagram showing a configuration of an A / D converter according to Embodiment 1 of the present invention. FIG. 4 is a block diagram showing a configuration of a balanced circuit of an A / D converter according to Embodiment 2 of the present invention. FIG. 4 is a block diagram showing a configuration of an A / D converter according to Embodiment 3 of the present invention. FIG. 3 is a block diagram showing the configuration of the differentiator 9 in FIG. FIG. 1 is a block diagram showing a configuration of a conventional A / D converter. FIG. 5 is a block diagram showing a configuration of the integrator 52 in FIG. Waveform diagram of input signal and output signal of quantizer 53 in FIG.

Explanation of reference numerals

1, 2, 8 ΔΣ type A / D conversion circuit 3, 12, balance circuit 4, digital subtractor 5, inverting amplifier circuit for outputting positive-phase (in-phase) signal and reverse-phase signal 6, 7, analog adder 9 differentiator 10 analog subtraction Unit 11 Digital adder 13, 14 Operational amplifier 15, 16 Input resistance 17, 18 Feedback resistance 19 Capacitor 20, 21 Inverting amplifier circuit 22 Digital subtracter 23 DFF

Claims (3)

After converting an analog signal into a positive-phase signal and a negative-phase signal, a balanced circuit that adds the same DC component to the positive-phase signal and the negative-phase signal, and a positive-phase signal output from the balanced circuit are input. A first ΔΣ-type A / D conversion circuit, a second ΔΣ-type A / D conversion circuit that receives an anti-phase signal output from the balance circuit, and the first and second ΔΣ-type A / D converters Digital subtraction means for subtracting a digital signal output from the conversion circuit, wherein the first and second ΔΣ-type A / D conversion circuits have the same circuit configuration. . In an A / D conversion method in an A / D converter having a ΔΣ type A / D conversion circuit, an analog input signal is converted into a positive-phase signal and a negative-phase signal, and the same is applied to the positive-phase signal and the negative-phase signal, respectively. A / D conversion, wherein the A / D conversion is performed after adding the DC component, and the added DC component is removed by performing a subtraction process between the A / D converted positive-phase signal and the negative-phase signal. Method. 3. The A / D conversion method according to claim 2, wherein after removing a DC component superimposed on the analog input signal with a capacitor, the analog input signal is converted into a positive-phase signal and a negative-phase signal.

Images