JP2010193282A - A-d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive A-D converter which is provided with the merit of a ΔΣ type A/D converter, and reduced in precision requirements to analog components. <P>SOLUTION: The A-D converter comprises: a difference unit for generating a differential signal between an input analog signal and a feedback signal; an integrator for integrating the differential signal; a level/duty converter for generating a pulse signal having a duty corresponding to an output level of the integrator synchronously with a conversion clock obtained by frequency-dividing a fundamental clock; an oversampler for oversampling the pulse signal synchronously to the fundamental clock; a duty/level converter for outputting to the differential calculation device, as the feedback signal, a signal having a level corresponding to the duty of an output signal from the oversampler; and a digital filter for performing duty/level conversion processing and decimation filtering processing on the output signal of the oversampler. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

 The present invention relates to an A / D converter that converts an analog signal into a digital signal.

  Conventionally, a delta-sigma (ΔΣ) type A / D converter is known as one form of the A / D converter. FIG. 7 shows a configuration example of a general ΔΣ A / D converter. As shown in FIG. 7, a conventional ΔΣ A / D converter 100 includes a difference unit 101, an integrator 102, a comparator (comparator) 103, an oversampler 104, a 1-bit D / A converter 105, and a digital filter. (Decimation filter) 106. Among these, the difference unit 101, the integrator 102, the comparator 103, the oversampler 104, and the 1-bit D / A converter 105 constitute a ΔΣ modulator.

  The difference unit 101 generates a difference signal between the input analog signal and the output analog signal of the 1-bit D / A converter 105 and outputs the difference signal to the integrator 102. The integrator 102 integrates the difference signal input from the difference unit 101. The comparator 103 functions as a 1-bit A / D converter, and outputs a comparison result between the output signal of the integrator 102 and the reference signal to the oversampler 104 as a 1-bit signal.

 The oversampler 104 oversamples the 1-bit signal output from the comparator 103 to generate a 1-bit signal including a high-density pulse train, and outputs the 1-bit signal to the 1-bit D / A converter 105 and the digital filter 106. The 1-bit D / A converter 105 converts the output signal of the oversampler 105 into an analog signal and outputs the analog signal to the difference unit 101. The digital filter 106 generates a digital signal having a necessary resolution by thinning the output signal (high-density 1-bit signal) of the oversampler 105.

JP-A-2-172324

  The ΔΣ A / D converter 100 as described above can suppress quantization noise by oversampling and noise shaping, and can take a trade-off between resolution and conversion speed by setting a thinning rate in the digital filter 106. There are advantages. On the other hand, it is necessary to operate analog circuits such as the integrator 102, the comparator 103, and the 1-bit D / A converter 105 at high speed in accordance with the operation of the oversampler 104, and it is required to use high-speed elements. The Further, since noise at the sampling frequency cannot be removed by the digital filter 106, it is necessary to provide a pre-filter before the input.

  The present invention has been made in view of the above-described circumstances, and provides a low-cost A / D converter having advantages of a ΔΣ A / D converter and low accuracy requirements for analog parts. Objective.

  In order to solve the above problems, an A / D converter according to the present invention includes a difference unit that generates a difference signal between an input analog signal and a feedback signal, an integrator that integrates the difference signal, and a basic clock. A level / duty converter that generates a pulse signal having a duty corresponding to the output level of the integrator in synchronization with the conversion clock obtained in this manner, and oversampling the pulse signal in synchronization with the basic clock. An oversampler, a duty / level converter for outputting a signal having a level corresponding to a duty of an output signal of the oversampler to the differencer as the feedback signal, and a duty / level conversion for the output signal of the oversampler And a digital filter for performing decimation filtering processing It characterized the door (Figure 1).

 In the A / D converter of the present invention, the digital filter includes a duty / level conversion filter that generates a level signal corresponding to a duty of an output signal of the oversampler, and a decimation that performs a thinning process of the level signal. And a filter.

In the A / D converter of the present invention, the duty / level conversion filter is a moving average filter.
In the A / D converter of the present invention, the digital filter includes a filter for removing a specific frequency component in addition to the duty / level conversion filter and the decimation filter.

 According to the present invention, it is possible to realize a low-cost A / D converter that has the high resolution of the ΔΣ A / D converter and has low accuracy requirements for analog components.

1 is a configuration block diagram of an A / D converter 1 of the present invention. 4 is a specific configuration example of a portion corresponding to a ΔΣ modulator in the A / D converter 1. 3 is a first timing chart showing the operation of the A / D converter 1. 4 is a second timing chart showing the operation of the A / D converter 1. It is an example of a frequency characteristic obtained by adding the frequency characteristics of the decimation filter 18b and the commercial frequency elimination filter 18c in the A / D converter 1. FIG. 6 is a notch characteristic diagram of the level / duty converter 15 in the A / D converter 1. 2 is a configuration example of a conventional ΔΣ A / D converter 100.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration block diagram of an A / D converter 1 of the present invention. As shown in FIG. 1, the A / D converter 1 of this embodiment includes an oscillator 11, a frequency divider 12, a difference unit 13, an integrator 14, a level / duty converter 15, an oversampler 16, a duty / level. It comprises a converter 17 and a digital filter 18.

 Examples will now be described. The difference unit 13, the integrator 14, the level / duty converter 15, the oversampler 16 and the duty / level converter 17 constitute a ΔΣ modulator. Although details will be described later, the analog switch circuit 17a and the smoother 17b constitute a duty / level converter 17 (see FIG. 2).

 The oscillator 11 generates a basic clock CL0 having a frequency F0 and outputs the basic clock CL0 to the frequency divider 12, the oversampler 16, and the digital filter 18. In this embodiment, for convenience of explanation, the frequency F0 of the basic clock CL0 is assumed to be 5 kHz. The frequency divider 12 divides the basic clock CL0 input from the oscillator 11 to generate a converted clock CLs having a frequency Fs and outputs the converted clock CLs to the level / duty converter 15. Here, the frequency Fs of the conversion clock CLs is 1 kHz.

 In the present embodiment, the configuration in which the basic clock CL0 and the conversion clock CLs are generated inside the A / D converter 1 using the oscillator 11 and the frequency divider 12 is illustrated. However, the basic clock CL0 and the conversion clock are generated. It is good also as a structure which supplies CLs from the outside.

  The difference unit 13 generates a difference signal between the input analog signal Ain and the output signal of the duty / level converter 17 and outputs the difference signal to the integrator 14. The integrator 14 integrates the difference signal input from the difference unit 13 and outputs a signal corresponding to the integration result to the level / duty converter 15 as an integration signal Iout.

  The level / duty converter 15 generates a pulse signal Pout having a duty corresponding to the level (amplitude) of the integration signal Iout input from the integrator 14, and includes a triangular wave generator 15a and a comparator 15b. Yes. The triangular wave generator 15a generates a triangular wave signal Tri having the same period as the conversion clock CLs based on the conversion clock CLs input from the frequency divider 12, and outputs the triangular wave signal Tri to the inverting input terminal (−) of the comparator 15b. The comparator 15b compares the integration signal Iout input to the non-inverting input terminal (+) with the triangular wave signal Tri input to the inverting input terminal, and the signal corresponding to the comparison result is over-pulsed as the pulse signal Pout. Output to the sampler 16. Note that the cycle of the pulse signal Pout (the conversion cycle of the level / duty converter 15) is the same as the triangular wave signal Tri, that is, the cycle Ts (= 1 / Fs = 1 ms) of the conversion clock CLs.

  The oversampler 16 is, for example, a D-type flip-flop. The oversampler 16 oversamples the pulse signal Pout input from the level / duty converter 15 in synchronization with the basic clock CL0 input from the oscillator 11, and according to the sampling result. The obtained signal is output to the duty / level converter 17 and the digital filter 18 as the sampling signal Sout.

  The analog switch circuit 17a selectively outputs the reference voltage Vref = 5V or 0V according to the sampling signal Sout input from the oversampler 16. Specifically, the analog switch circuit 17a selects the reference voltage Vref = 5V when the sampling signal Sout is high level, and selects and outputs 0V when the sampling signal Sout is low level. The smoother 17 b smoothes the output signal of the analog switch circuit 17 a and outputs the smoothed signal to the differentiator 13.

  The digital filter 18 performs a duty / level conversion process and a decimation filtering process on the sampling signal Sout input from the oversampler 16 in synchronization with the basic clock CL0 input from the oscillator 11. It comprises a level conversion filter 18a, a decimation filter 18b, and a commercial frequency removal filter 18c.

The duty / level conversion filter 18a is configured by a moving average filter such as a Sinc1 filter, for example, and generates a digital signal indicating a level corresponding to the duty of the sampling signal Sout by performing a moving average process on the sampling signal Sout. And
The digital signal is output to the decimation filter 18b as a level signal Lv. The output update decimation rate DF (Decimation Factor) of the duty / level conversion filter 18a needs to be set appropriately to a multiple of Fs / F0.

  Although details will be described later, for example, if the output update thinning rate DF = Fs / F0 = 5, the moving average processing of the sampling signal Sout is performed every period corresponding to five clocks of the basic clock CL0, and the result is a level signal. Output as Lv. Therefore, the output rate of the level signal Lv is the same as the frequency Fs of the conversion clock CLs.

  The decimation filter 18b is composed of, for example, a Sinc2 filter, and has a thinning processing function and a high frequency removal function for the level signal Lv. The output update decimation rate DF of the decimation filter 18b can be arbitrarily set. For example, when DF = P (P is an arbitrary value), the output rate of the decimation filter 18b is expressed by Fs / P. The commercial frequency removal filter 18c is a filter for removing the frequency component of the commercial power supply superimposed on the input analog signal Ain, and is configured by, for example, an FIR filter. The output update decimation rate DF of the commercial frequency removal filter 18c can also be set arbitrarily. For example, if DF = Q (Q is an arbitrary value), the output rate of the commercial frequency elimination filter 18c is expressed by Fs / P / Q.

  The commercial frequency elimination filter 18c is a filter provided to realize frequency characteristics required as an application. When a noise component other than the commercial power supply is superimposed on the input analog signal Ain, the noise is removed. A filter that removes components may be provided as appropriate.

  The digital filter 18 as described above performs duty / level conversion processing and decimation filtering processing on the sampling signal Sout, and a digital signal Dout corresponding to the input analog signal Ain is generated as a result of the processing.

 As shown in FIG. 2, the analog switch circuit 17a and the smoother 17b constitute a duty / level converter 17.

  Next, the operation of the A / D converter 1 of the present embodiment configured as described above will be described with reference to FIGS. FIG. 3 shows a temporal relationship among the basic clock CL0, the triangular wave signal Tri, the integration signal Iout, the pulse signal Pout, and the sampling signal Sout when the level of the input analog signal Ain is 2.0V. It is a timing chart. Here, it is assumed that the output update decimation rate DF of the duty / level conversion filter 18a is set to “5” and the output update decimation rate DF of the decimation filter 18b is set to “10”. To do.

  As shown in FIG. 3, the period T0 of the basic clock CL0 is T0 = 1 / F0 = 0.2 ms, and the period of the triangular wave signal Tri is 1 ms, which is the same as the period of the conversion clock CLs (conversion period Ts). . Here, focusing on the period from time t1 to time t2, since the integral signal Iout is larger than the triangular wave signal Tri, the pulse signal Pout output from the level / duty converter 15 (comparator 15b) is at a high level (5V). It becomes. On the other hand, paying attention to the period from time t2 to t3, the triangular wave signal Tri is larger than the integration signal Iout, so the pulse signal Pout is at a low level (0 V). As described above, the level / duty converter 15 outputs the pulse signal Pout having a duty corresponding to the level of the integration signal Iout, and the cycle thereof is the same as the conversion cycle Ts (1 ms).

  The oversampler 16 samples the pulse signal Pout having the duty as described above in synchronization with the basic clock CL0. Therefore, as shown in FIG. 3, the sampling signal Sout becomes a pulse waveform that becomes high level during a period of two basic clocks and low level during a period of three basic clocks, and the cycle thereof is the same as the conversion cycle Ts (1 ms). ) That is, the duty of the sampling signal Sout is 40%.

  When attention is paid to the period during which the sampling signal Sout is at a high level (period from time t4 to t5), 0 V is selected by the duty / level converter 17 during this period, so that the integration signal Iout output from the integrator 14 is selected. Rises at a constant slope according to the difference value between the input analog signal Ain (2V) and 0V. On the other hand, paying attention to the period during which the sampling signal Sout is at a low level (period from time t5 to t6), since the reference voltage Vref = 5V is selected by the duty / level converter 17 during this period, it is output from the integrator 14. The integration signal Iout decreases with a constant slope corresponding to the difference value between the input analog signal Ain (2V) and 5V. That is, the integration signal Iout becomes a sawtooth wave having the same period as the conversion period Ts.

  When the sampling signal Sout as described above is input to the duty / level conversion filter 18a, the moving average processing of the sampling signal Sout is performed every period corresponding to five clocks of the basic clock CL0, and the result is the level. Output as signal Lv. That is, in the sampling signal Sout, the high level is “1” only during the period corresponding to two basic clocks in the period corresponding to five basic clocks, so the result of the moving average process is 2/5 = 0.4 The level of the input analog signal Ain can be calculated by 5V × 0.4 = 2V. The output of the decimation filter 18b is also a value corresponding to this.

 FIG. 4 shows a temporal relationship among the basic clock CL0, the triangular wave signal Tri, the integration signal Iout, the pulse signal Pout, and the sampling signal Sout when the level of the input analog signal Ain is 2.4V. It is a timing chart.

  The operation of the A / D converter 1 in this case is the same as that in the case where the level of the input analog signal Ain is 2.0 V. However, when FIG. 3 is compared with FIG. 4, the sampling signal of FIG. It can be seen that in Sout, a pulse having a high level period corresponding to one basic clock is generated in the areas indicated by reference numerals S1, S2, S3 and S4. When such a sampling signal Sout is viewed in a period corresponding to 10 conversion clocks (10 Ts), it is at a high level in a period corresponding to 24 basic clocks and at a low level in a period corresponding to 26 basic clocks. Therefore, the output of the decimation filter 18b becomes a value corresponding to 2.4V.

  In this way, if it is necessary to convert the level of the input analog signal Ain to a decimal point or less, an A / D having sufficient conversion accuracy can be obtained by setting the output update thinning rate DF of the decimation filter 18b large. The converter 1 can be realized. In the above description, for ease of explanation, the level of the input analog signal Ain is 2.4 V. However, any input analog signal Ain can be added as long as it is in the range of 0 to 5 V. In the sampling signal Sout, a duty that accurately reflects the level of the input analog signal Ain appears in a long cycle. That is, a ΔΣ type A / D converter is realized by the A / D converter 1 of the present embodiment.

  As described above, in the A / D converter 1 of the present embodiment, the operating frequency Fs of the integrator 14, the level / duty converter 15 and the duty / level converter 17 is independent of the frequency F0 of the basic clock CL0. It can be set low. On the other hand, unlike the case of a simple duty / level converter, the configuration of a ΔΣ A / D converter is adopted, so that the final A / D converter can be obtained without setting Fs extremely low. Resolution can be ensured. That is, an analog circuit can be configured with inexpensive components by setting the frequency Fs of the conversion clock CLs.

  Further, since the latter stage of the digital filter 18, the decimation filter 18b, and the commercial frequency removal filter 18c operate at the sampling rate Fs, they cannot be removed when a signal having an Fs component is input. FIG. 5 is an example of frequency characteristics obtained by adding the frequency characteristics of the decimation filter 18b and the commercial frequency elimination filter 18c. As shown in FIG. 5, it can be seen that if a signal having an Fs component enters the decimation filter 18b and the commercial frequency removal filter 18c, it cannot be removed.

 In this respect, the level / duty converter 15 has a conversion cycle of Ts = 1 / Fs, and the notch characteristic as shown in FIG. 6 causes the same frequency as the frequency Fs to be output from the subsequent duty / level conversion filter 18a. Never appear in the. The overall frequency characteristic of the A / D converter 1 of the present embodiment is a characteristic obtained by multiplying FIG. 5 and FIG. 6, and the Fs component does not pass through. That is, in the A / D converter 1 of this embodiment, aliasing noise does not occur and it is not necessary to provide a special prefilter.

 As described above, the configuration of the A / D converter 1 of the present embodiment combines the simplicity of the integral A / D converter with the high resolution of the ΔΣ A / D converter, and It is possible to realize a low-cost A / D converter with low accuracy requirements for analog parts.

In addition, this invention is not limited to the said embodiment, The following application examples can be considered.
(1) In the above embodiment, the case where the duty / level conversion filter 18a is configured by the Sinc1 filter is exemplified. . Further, the trade-off between the conversion accuracy and the response speed can be determined depending on what filtering process is performed on the output of the duty / level conversion filter 18a. A multi-tap filter can also be created.

 DESCRIPTION OF SYMBOLS 1 ... A / D converter, 11 ... Oscillator, 12 ... Divider, 13 ... Differencer, 14 ... Integrator, 15 ... Level / duty converter, 16 ... Oversampler, 17 ... Duty / level converter, 17a ... Analog switch circuit, 17b ... Smoother, 18 ... Digital filter, 18a ... Duty / level conversion filter, 18b ... Decimation filter, 18c ... Commercial frequency elimination filter

Claims (5)

A differentiator for generating a difference signal between the input analog signal and the feedback signal;
An integrator for integrating the difference signal;
A level / duty converter that generates a pulse signal having a duty corresponding to the output level of the integrator in synchronization with a conversion clock obtained by dividing a basic clock;
An oversampler for oversampling the pulse signal in synchronization with the basic clock;
A duty / level converter that outputs a signal having a level corresponding to the duty of the output signal of the oversampler to the differencer as the feedback signal;
And a digital filter that performs duty / level conversion processing and decimation filtering processing on the output signal of the oversampler. The digital filter is
A duty / level conversion filter that generates a level signal corresponding to the duty of the output signal of the oversampler;
The A / D converter according to claim 1, further comprising: a decimation filter that performs a thinning process of the level signal.   3. The A / D converter according to claim 2, wherein the duty / level conversion filter is a moving average filter.   4. The A / D converter according to claim 2, wherein the digital filter includes a filter for removing a specific frequency component in addition to the duty / level conversion filter and the decimation filter. The level / duty converter is
A triangular wave generator that generates a triangular wave signal in synchronization with the conversion clock; and
The A / D conversion according to any one of claims 2 to 4, further comprising: a comparator that generates the pulse signal by comparing the output signal of the integrator and the triangular wave signal. vessel.

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