JP2013009083A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter that has advantages of a ΔΣ A/D converter and comprises a single chip microcomputer and simple analog components.SOLUTION: A differential element 130 generates a differential signal between an input analog signal and a feedback signal. An integrator 140 integrates the differential signal, and an analog/digital converter 150 generates a digital signal depending on an output of the integrator 140 in synchronism with a conversion clock. A digital/duty converter 160 outputs a pulse signal having a duty depending on the digital signal as the feedback signal to the differential element 130, and a digital filter 180 decimation-filters the digital signal. A frequency divider 120, the analog/digital converter 150, the digital/duty converter 160 and the digital filter 180 are implemented by peripheral functionalities of a single chip microcomputer 190.

Description

  The present invention relates to an A / D converter, and more particularly to a ΔΣ A / D converter.

  Conventionally, an A / D converter called a ΔΣ A / D converter has been proposed, and an improved A / D converter has also been proposed.

  FIG. 2 is a schematic diagram showing the configuration of an improved ΔΣ A / D converter.

  As shown in FIG. 2, the improved ΔΣ A / D converter 10 includes a differencer 11, an integrator 12, an analog / duty converter 13, an oscillator 14, a frequency divider 15, a sampler 16, a duty / analog converter. And a digital filter 18.

  The difference unit 11 outputs a difference signal between the input analog signal and the feedback signal. The integrator 12 integrates the difference signal output from the differentiator.

  The analog / duty converter 13 is a pulse signal having a duty corresponding to the output level of the integrator 12 in synchronization with the conversion clock FS obtained by the frequency divider 15 dividing the basic clock F0 generated by the oscillator 14. Is generated.

  The sampler 16 oversamples the pulse signal generated by the analog / duty converter 13 in synchronization with the basic clock F0.

  The duty / analog converter 17 outputs an analog signal having a level corresponding to the duty of the output signal of the sampler 16 to the difference unit 11 as a feedback signal.

  The digital filter 18 performs duty / level conversion processing and decimation filtering processing on the output signal of the sampler 16.

  The above-described ΔΣ type A / D converter 10 uses an analog / duty converter instead of a comparator of a general ΔΣ type A / D converter, and a duty / analog conversion instead of a 1-bit D / A converter. By using this device, it has the advantages of a general ΔΣ type A / D converter, and can be manufactured at low cost and with low accuracy requirements for analog components (see Patent Document 1).

JP 2010-192382 A

  However, in the above-described ΔΣ A / D converter, the analog / duty converter is operated with the conversion clock FS, and the sampler is operated with the basic clock F0 faster than the conversion clock FS.

  In addition, a moving average filter is provided at the input stage of the digital filter, and a duty / level converter that generates a level signal corresponding to the duty of the output signal of the sampler is provided. The input rate of this duty / level converter is the basic clock F0, and the output rate is the conversion clock FS. The decimation filter provided in the subsequent stage of the duty / level converter is configured to reduce quantization noise by operating with the conversion clock FS and performing decimation filtering processing.

  In such a ΔΣ type A / D converter, the analog / duty converter must perform sampling processing at a high frequency, and this A / D converter is used in a peripheral function built in a single chip microcomputer. In many cases, the operation speed of the analog / duty converter and the sampler portion is insufficient, and there is a problem that the configuration cannot be realized as it is.

  If an A / D converter is to be manufactured using a single-chip microcomputer with this configuration, a hard-wired logic must be configured using PLD, GateArray, etc. to compensate for the operating speed of the single-chip microcomputer. In addition, there is a problem that the advantages of using a single-chip microcomputer, such as improvement in manufacturing efficiency and low manufacturing cost, are impaired.

  The present invention has been made in view of these points, and provides an A / D converter that has the advantages of a ΔΣ A / D converter and includes a single chip microcomputer and simple analog components. For the purpose.

  In the present invention, in order to solve the above problem, a differencer that generates a difference signal between an input analog signal and a feedback signal, an integrator that integrates the difference signal, and a frequency divider divide the basic clock. An analog / digital converter that generates a digital signal corresponding to the output of the integrator in synchronization with the obtained conversion clock, and a pulse signal having a duty corresponding to the digital signal generated by the analog / digital converter A digital / duty converter that outputs to the differencer as a feedback signal; and a digital filter that performs a decimation filtering process on the output signal of the analog / digital converter, the frequency divider and the analog / digital converter. , The digital / duty converter, and the digital filter A / D converter is provided, which comprises implemented using peripherals Le chip microcomputer.

  Thereby, the difference unit generates a difference signal between the input analog signal and the feedback signal, the integrator integrates the difference signal, the analog / digital converter, and the frequency divider divides the basic clock. The digital signal corresponding to the output of the integrator is generated in synchronization with the conversion clock obtained by the above. The digital / duty converter outputs a pulse signal having a duty corresponding to the digital signal generated by the analog / digital converter as the feedback signal to the differencer, and a digital filter is used for the analog / digital converter. The decimation filtering process is performed on the output signal. Further, the frequency divider, the analog / digital converter, the digital / duty converter, and the digital filter are realized by using peripheral functions of a single chip microcomputer.

  According to the A / D converter of the present invention, the frequency divider, the analog / digital converter, the digital / duty converter, and the digital filter are realized by using the peripheral functions of the single chip microcomputer. An A / D converter that has the advantages of a / D converter and is configured with a single chip microcomputer and simple analog components can be realized.

It is a figure which shows the structure of the A / D converter which concerns on this Embodiment. It is the schematic which shows the structure of an improved delta-sigma type A / D converter.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of an A / D converter according to the present embodiment.

  As shown in FIG. 1, the A / D converter 100 includes an oscillator 110, a frequency divider 120, a difference unit 130, an integrator 140, an analog / digital converter 150, a digital / duty converter 160, and a duty / analog converter. 170 and a digital filter 180.

  The differencer 130, the integrator 140, the analog / digital converter 150, the digital / duty converter 160, and the duty / analog converter 170 constitute a ΔΣ modulator, and the frequency divider 120, the analog / digital converter 150, and the like. The digital / duty converter 160 and the digital filter 180 are realized by peripheral functions of the single chip microcomputer 190.

The oscillator 110 generates a basic clock CL0 having a frequency F0 and outputs it to the frequency divider 120.
The frequency divider 120 divides the basic clock CL0 input from the oscillator 110 to generate a converted clock CLs having a frequency FS and outputs the converted clock CLs to the analog / digital converter 150.

  In the present embodiment, the basic clock CL0 and the conversion clock CLs are generated inside the A / D converter 100 using the oscillator 110 and the frequency divider 120. However, the basic clock CL0 and the conversion clock are generated. It is good also as a structure which supplies CLs from the outside.

  The difference unit 130 generates a difference signal between the input analog signal Analogin and the output signal of the duty / analog converter 170 and outputs the difference signal to the integrator 140. The integrator 140 integrates the difference signal input from the difference unit 130 and outputs a signal corresponding to the integration result to the analog / digital converter 150 as an integration signal Iout.

  The analog / digital converter 150 generates a digital signal Dout corresponding to the level (amplitude) of the integration signal Iout input from the integrator 140. The digital / duty converter 160 generates a pulse signal Pout having a duty corresponding to the digital signal Dout input from the analog / digital converter 150.

  The duty / analog converter 170 selectively outputs the reference voltage Vref = 5V or 0V according to the duty of the pulse signal Pout input from the digital / duty converter 160. Specifically, the duty / analog converter 170 includes, for example, an analog switch circuit and a smoother, and the analog switch circuit selects the reference voltage Vref = 5 V while the pulse signal Pout is at a high level. During the period when the pulse signal Pout is low level, 0V is selected and output. The smoother smoothes the output signal of the analog switch circuit and outputs it to the differentiator 130.

  The digital filter 180 performs high-frequency component removal processing such as moving average on the digital signal Dout input from the analog / digital converter 150 to reduce quantization noise and increase the number of effective bits. A frequency characteristic required as an application is realized by a filter or the like.

The digital filter 180 is a CPU (Central
The CPU 191 delivers the digital signal Dout to the digital filter 180 and the digital / duty converter 160 at the same timing. Data transfer from the analog / digital converter 150 to the digital / duty converter 160 is realized by firmware using the bus access function and memory of the CPU 191.

  The digital filter 180 includes a decimation filter and a commercial frequency removal filter.

  The decimation filter is composed of, for example, a Sinc2 filter, and has a thinning processing function and a high frequency removal function for the level signal Lv. The output update decimation rate DF of this decimation filter can be set arbitrarily. For example, when DF = P (P is an arbitrary value), the output rate of the decimation filter is represented by FS / P.

  The commercial frequency elimination filter is a filter for removing the frequency component of the commercial power supply superimposed on the input analog signal Analogin, and is configured by, for example, an FIR filter. The output update decimation rate DF of this commercial frequency removal filter can also be set arbitrarily. For example, if DF = Q (Q is an arbitrary value), the output rate of the commercial frequency elimination filter is represented by (FS / P) / Q.

  The commercial frequency elimination filter is a filter provided for realizing frequency characteristics required as an application. When a noise component other than the commercial power source is superimposed on the input analog signal Analogin, the noise component is removed. A filter that removes the light may be provided as appropriate.

  The digital filter 180 as described above performs decimation filtering processing on the digital signal Dout, and a digital signal Digitalout corresponding to the input analog signal Analogin is generated as a result of the processing.

  If it is necessary to convert the level of the input analog signal Analogin with high resolution, the A / D converter 100 having sufficient conversion accuracy is realized by setting the output update thinning rate DF of the decimation filter large. be able to. In addition, if the level of the input analog signal Analogin is in the range of 0 to 5V, no matter what input analog signal Analogin is added, the digital signal Dout is accurate to the level of the input analog signal Analogin when viewed in a long cycle. The output is proportional to. That is, a ΔΣ type A / D converter is realized by the A / D converter 100 of the present embodiment.

  As described above, in the A / D converter 100 of the present embodiment, the operating frequency FS of the integrator 140, the analog / digital converter 150, the digital / duty converter 160, the duty / analog converter 170, and the digital filter 180. Can be set low independently of the frequency F0 of the basic clock CL0. On the other hand, unlike the case of an integral type duty / analog converter, the configuration of a ΔΣ A / D converter is adopted, so that the final A / D converter can be achieved without setting FS extremely low. High resolution can be secured. That is, an analog circuit can be configured with inexpensive components by setting the frequency FS of the conversion clock CLs.

  Further, in the configuration of the A / D converter 100 of the present embodiment, the input frequency of the analog / digital converter 150 and the output of the digital / duty converter 160 are compared with a normal ΔΣ type A / D converter. The frequency is low. Therefore, the A / D converter 100 of this embodiment can be realized even with a low input / output frequency such as a single chip microcomputer.

  However, in the A / D converter 100 of the present embodiment, the accuracy of the pulse signal Pout output from the digital / duty converter 160 affects the overall accuracy, but the pulse width output is a pure digital circuit. Since the speed can be increased by the recent miniaturization of the IC and accurate time information can be output by this speed increase, the necessary accuracy can be sufficiently secured by the peripheral function of the single chip microcomputer 190.

  Further, in the A / D converter 100 of the present embodiment, the offset of the differencer 130 appears as it is as the accuracy of the A / D converter 100, but it is difficult to ensure the accuracy of the differencer 130. This is not a problem.

  As described above, the configuration of the A / D converter 100 of the present embodiment combines the simplicity of the integral A / D converter with the high resolution of the ΔΣ A / D converter, and It is possible to realize an A / D converter composed of a single chip microcomputer and simple analog parts.

  In the present embodiment, it has been described that the duty / analog converter 170 converts the pulse signal Pout input from the digital / duty converter 160 into an analog signal and outputs the analog signal to the difference unit 130. The / duty converter 160 may directly output the pulse signal Pout to the differentiator 130 without going through the duty / analog converter 170.

  That is, in the present embodiment, since the digital / duty converter 160 is realized by the peripheral function of the single chip microcomputer 190, the voltage value of the pulse signal Pout output from the digital / duty converter 160 is not necessarily constant. There are many cases. Therefore, even if the voltage is not constant, the A / D converter 100 with higher accuracy is obtained by outputting to the difference unit 130 via the duty / analog converter 170.

  Therefore, when the voltage value of the pulse signal Pout output from the digital / duty converter 160 is constant, the A equivalent to the A / D converter 100 according to the present embodiment without using the duty / analog converter 170. A / D converter is realized.

100 A / D Converter 110 Oscillator 120 Divider 130 Differencer 140 Integrator 150 Analog / Digital Converter 160 Digital / Duty Converter 170 Duty / Analog Converter 180 Digital Filter 190 Single-Chip Microcomputer 191 CPU

Claims (4)

A differentiator for generating a difference signal between the input analog signal and the feedback signal;
An integrator for integrating the difference signal;
An analog / digital converter that generates a digital signal corresponding to the output of the integrator in synchronization with a conversion clock obtained by the frequency divider dividing the basic clock;
A digital / duty converter that outputs a pulse signal having a duty according to a digital signal generated by the analog / digital converter to the differencer as the feedback signal;
A digital filter that performs quantization noise removal processing on the output signal of the analog / digital converter;
With
An A / D converter characterized in that the frequency divider, the analog / digital converter, the digital / duty converter, and the digital filter are realized using peripheral functions of a single chip microcomputer. The digital filter is
2. The A / D converter according to claim 1, which is realized by a CPU of the single chip microcomputer.   Duty / analog which is provided between the digital / duty converter and the differencer and outputs an analog signal corresponding to the duty of the pulse signal generated by the digital / duty converter to the differencer as the feedback signal The A / D converter according to claim 1, further comprising a converter.   4. The A / D converter according to claim 3, wherein the duty / analog converter is an RC filter.

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