CN116846400A - Delta-sigma modulator - Google Patents
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- CN116846400A CN116846400A CN202210306153.3A CN202210306153A CN116846400A CN 116846400 A CN116846400 A CN 116846400A CN 202210306153 A CN202210306153 A CN 202210306153A CN 116846400 A CN116846400 A CN 116846400A
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- 239000003990 capacitor Substances 0.000 claims description 39
- 230000010354 integration Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000000737 periodic effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000001914 filtration Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/392—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
Abstract
The invention discloses a delta-sigma modulator, which comprises a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is used for receiving the first analog signal and the second analog signal and outputting an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer selects the first analog signal or the second analog signal as an input signal to be output in a time-sharing manner. The modulation circuit is used for modulating the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and selects either the first output terminal or the second output terminal to output the digital signal in a time-sharing manner.
Description
Technical Field
The present invention relates to a delta-sigma modulator, and more particularly to a delta-sigma modulator capable of processing analog signals of different electrical forms.
Background
Delta-sigma modulators (Sigma Delta Modulator; alternatively referred to as sigma-delta modulators) are commonly used to achieve high resolution analog-to-digital conversion, but none of the delta-sigma modulators currently can handle analog signals of different electrical forms, such as dc and ac signals.
Disclosure of Invention
In view of the shortcomings of the prior art, it is an object of the present invention to provide a delta-sigma modulator that can process analog signals of different electrical forms.
In order to achieve the above objective, an embodiment of the present invention provides a delta sigma modulator, which includes a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is used for receiving the first analog signal and the second analog signal and outputting an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer selects the first analog signal or the second analog signal as an input signal to be output in a time-sharing manner. The modulation circuit is coupled to the multiplexer for modulating the input signal into a digital signal. The demultiplexer is coupled to the modulation circuit, and has a first output terminal and a second output terminal, and is configured to receive the digital signal, and select the first output terminal or the second output terminal to output the digital signal in a time-sharing manner.
For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.
Drawings
Fig. 1 is a functional block diagram of a delta-sigma modulator according to an embodiment of the present invention.
Fig. 2 is a circuit schematic of a continuous-time integrator according to a first embodiment of the present invention.
Fig. 3 is a circuit schematic of a continuous-time integrator according to a second embodiment of the present invention.
Fig. 4 is a circuit schematic of a continuous-time integrator according to a third embodiment of the present invention.
Fig. 5 is a schematic circuit diagram of a discrete-time integrator according to a first embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a discrete-time integrator according to a second embodiment of the present invention.
Symbol description
1: delta-sigma modulator
10: multiplexer
12: modulation circuit
122: arithmetic unit
124: loop filter
126: quantizer
128: digital-to-analog converter
14: demultiplexer
16: decimation filter
18: counter
A1: first analog signal
A2: second analog signal
SIN: input signal
D: digital signal
O1: a first output end
O2: a second output end
D1: a first output signal
D2: a second output signal
AF: analog feedback signal
E: difference signal
F: filtering a signal
RST: reset signal
1242: continuous time integrator
1244: discrete time integrator
201,501: differential amplifier
R21, R22: resistor
C21 to C22, C51 to C54: capacitance device
S21 to S22, S31, S41 to S44, S51 to S59, S61 to S64: switch
P31 to P32, P41 to P42, P51 to P56, P61 to P62: node
GND: ground voltage
Detailed Description
The following embodiments of the present invention are described in terms of specific examples, and those skilled in the art will appreciate the advantages and effects of the present invention from the disclosure provided herein. The invention is capable of other and different embodiments and its several details are capable of modifications and various other uses and applications, all of which are obvious from the description, without departing from the spirit of the invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the content provided is not intended to limit the scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic functional block diagram of a delta-sigma modulator according to an embodiment of the invention. As shown in fig. 1, the delta-sigma modulator 1 includes a multiplexer 10, a modulation circuit 12, and a demultiplexer 14. The multiplexer 10 is configured to receive the first analog signal A1 and the second analog signal A2 and output an input signal SIN. The first analog signal A1 and the second analog signal A2 are in different electrical forms, and the multiplexer 10 selects the first analog signal A1 or the second analog signal A2 as the input signal SIN to be output in a time-sharing manner. In other words, the signal processing time of the delta-sigma modulator 1 may be divided into a plurality of periods, and the multiplexer 10 selects the first analog signal A1 or the second analog signal A2 as the input signal SIN to be output in each period. However, the present invention does not limit the lengths of the periods to be the same, and does not limit the specific implementation manner in which the multiplexer 10 selects the first analog signal A1 or the second analog signal A2 as the input signal SIN, as long as the multiplexer 10 can alternately select the first analog signal A1 and the second analog signal A2 to be output as the input signal SIN.
The modulation circuit 12 is coupled to the multiplexer 10 for modulating the input signal SIN to the digital signal D. Details of the modulation circuit 12 will be described in other paragraphs, and thus will not be repeated here. It should be appreciated that the modulation circuit 12 can modulate the input signal SIN to generate the corresponding digital signal D, regardless of whether the input signal is the first analog signal A1 or the second analog signal A2. In addition, the demultiplexer 14 is coupled to the modulation circuit 12, and has a first output terminal O1 and a second output terminal O2, and is configured to receive the digital signal D, and select the first output terminal O1 or the second output terminal O2 in a time-sharing manner to output the digital signal D. The specific implementation manner of the demultiplexer 14 to select the first output terminal O1 or the second output terminal O2 to output the digital signal D is not limited in the present invention, so long as the demultiplexer 14 selects the first output terminal O1 to output the digital signal D when the modulation circuit 12 modulates the first analog signal A1 as the input signal SIN to output the corresponding digital signal D, and selects the second output terminal O2 to output the digital signal D when the modulation circuit 12 modulates the second analog signal A2 as the input signal SIN to output the corresponding digital signal D.
Specifically, the modulation circuit 12 includes an arithmetic unit 122, a loop filter 124, a quantizer 126, and a digital-to-analog converter 128. The operation unit 122 is configured to receive the input signal SIN and the analog feedback signal AF, and calculate a difference between the input signal SIN and the analog feedback signal AF to output a difference signal E. The loop filter 124 is coupled to the operation unit 122 for processing the difference signal E to generate a filtered signal F. For example, if the input signal SIN and the analog feedback signal AF are respectively at dc voltages of 0.2 v and 1 v, the difference signal E is a dc voltage of 0.2 v minus 1 v (i.e., -0.8 v), and the difference signal E is processed by the loop filter 124 as the filtered signal F. Details regarding the loop filter 124 will be described in other paragraphs, and thus will not be repeated here.
The quantizer 126 is coupled to the loop filter 124 for quantizing the filtered signal F into a digital signal D. Quantization refers to a process of approximating a continuous value of the filtered signal F to a plurality of discrete values, and the quantizer 126 may be implemented by a multi-stage comparator, but the present invention is not limited to the specific embodiment of the quantizer 126. In addition, the digital-to-analog converter 128 is coupled to the quantizer 126 and the operation unit 122, and is configured to perform digital-to-analog conversion on the digital signal D to generate the analog feedback signal AF. Since the operation principle of the digital-to-analog converter 128 is well known to those skilled in the art, the details thereof will not be described in detail herein. It should be noted that the first analog signal A1 may be a dc signal, and the second analog signal A2 may be an ac signal. For example, the dc signal may be a dc voltage output by a temperature sensor, a gravity sensor or a triaxial sensor, and the ac signal may be an audio signal output by a microphone or an audio device, but the invention is not limited thereto. In other embodiments, the first analog signal A1 may be an analog signal (near DC signal) close to a direct voltage, but the invention is not limited thereto.
However, since the dc signal (i.e., the first analog signal A1) is too small, there is a problem of Periodic Tone (Periodic Tone), the loop filter 124 of the modulation circuit 12 can also avoid the Periodic Tone by using a Periodic reset mechanism. In other words, when the modulation circuit 12 modulates the first analog signal A1 as the input signal SIN, the loop filter 124 is further reset according to a reset signal RST. For example, when receiving the reset signal RST at a high level, the loop filter 124 resets, but the present invention is not limited to the specific embodiment for generating the reset signal RST. Conceptually, delta-sigma modulation is an oversampling technique that reduces noise in the operating band, so this embodiment can also use the oversampling rate as the period of the reset signal RST in transitioning from a low level to a high level.
Further, in order to convert the digital signal D after modulating the ac signal (i.e., the second analog signal A2) into a digital signal of higher resolution, the delta-sigma modulator 1 may further include a decimation filter (decimation filter) 16. The decimation filter 16 is coupled to the second output terminal O2 of the demultiplexer 14, and is configured to decimate the digital signal D outputted from the second output terminal O2 to generate a second output signal D2. The decimation filter is used for reducing the sampling frequency of the signal and realizing low-pass filtering. In addition, the decimation filter 16 of the present embodiment can not only reduce the sampling frequency of the digital signal D output by the second output terminal O2, but also filter out the noise with high frequency to generate the second output signal D2 with higher resolution.
On the other hand, the conceptually simplest decimation structure is a counter, except for the decimation filter 16. Therefore, in order to convert the digital signal D after modulating the direct current signal (i.e., the first analog signal A1) into a digital signal of higher resolution, the delta-sigma modulator 1 may further include a counter 18. The counter 18 is coupled to the first output terminal O1 of the demultiplexer 14, and is configured to count the digital signal D output by the first output terminal O1 to generate a first output signal D1. Similarly, the counter 18 can also avoid periodic tones by using a periodic reset mechanism. For example, the counter 18 may perform zero resetting according to the reset signal RST at the start of each predetermined period, and add the number of pulses occurring in the predetermined period. Since the operation principle of the counter 18 is well known to those skilled in the art, details thereof will not be described herein.
Still further, the loop filter 124 may include at least one continuous time integrator 1242 or a discrete time integrator 1244 for integrating the difference signal E, and the filtered signal F is generated according to the integration result output by the continuous time integrator 1242 or the discrete time integrator 1244. Since the operation principle of generating the filtered signal F according to the integration result of the integrator is well known to those skilled in the art, the details thereof will not be described herein. Various embodiments of continuous time integrator 1242 or discrete time integrator 1244 are illustrated by fig. 2 through 6 below.
Referring to fig. 2, fig. 2 is a circuit schematic of a continuous-time integrator according to a first embodiment of the present invention. In the first embodiment, the continuous-time integrator 1242 may include the differential amplifier 201, the resistor R21, the resistor R22, the capacitor C21, and the capacitor C22. The resistor R21 is coupled between the operation unit 122 (not shown in fig. 2) and the inverting input terminal of the differential amplifier 201, and the resistor R22 is coupled between the operation unit 122 and the non-inverting input terminal of the differential amplifier 201. In addition, the capacitor C21 is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier 201, and the capacitor C22 is coupled between the non-inverting input terminal and the inverting output terminal of the differential amplifier 201. Thus, continuous-time integrator 1242 may be used to integrate the difference signal E output by arithmetic unit 122. However, since the operation principles of the differential amplifier 201, the resistor R21, the resistor R22, the capacitor C21 and the capacitor C22 are well known to those skilled in the art, details of integrating the difference signal E by the continuous-time integrator 1242 will not be repeated.
As described above, the loop filter 124 is further reset according to the reset signal RST to avoid the periodic tone (idle tone) of the dc signal. Accordingly, the continuous-time integrator 1242 of the first embodiment may further include a reset switch S21 and a reset switch S22. The reset switch S21 and the capacitor C21 are connected in parallel between the inverting input terminal and the non-inverting output terminal of the differential amplifier 201, and the reset switch S22 and the capacitor C22 are connected in parallel between the non-inverting input terminal and the inverting output terminal of the differential amplifier 201. In addition, the reset signal RST is used to control the reset switch S21 and the reset switch S22. For example, when receiving the reset signal RST at the high level, the reset switch S22 and the reset switch S22 are turned on to reset the loop filter 124 to restore to the initial state.
Referring to fig. 3, fig. 3 is a circuit schematic of a continuous-time integrator according to a second embodiment of the present invention. Since the continuous-time integrator 1242 of the second embodiment is similar to the continuous-time integrator 1242 of the first embodiment, the same parts of the two embodiments will not be repeated. Note that, unlike the reset switch S21 and the reset switch S22 of the first embodiment, the continuous-time integrator 1242 of the second embodiment includes a reset switch S31. As shown in fig. 3, the first terminal of the capacitor C21 is coupled to the non-inverting output terminal of the differential amplifier 201 through the node P31, and the first terminal of the capacitor C22 is coupled to the inverting output terminal of the differential amplifier 201 through the node P32. In addition, the reset switch S31 is coupled between the node P31 and the node P32, and the reset signal RST is used to control the reset switch S31. For example, when receiving the reset signal RST at the high level, the reset switch S31 is turned on to reset the loop filter 124.
Referring to fig. 4, fig. 4 is a circuit schematic of a continuous-time integrator according to a third embodiment of the present invention. Since the continuous-time integrator 1242 of the third embodiment is similar to the continuous-time integrator 1242 of the second embodiment, the same parts of the two embodiments will not be repeated. Note that, unlike the reset switch S31 of the second embodiment, the continuous-time integrator 1242 of the third embodiment includes a set switch S41, a reset switch S42, a set switch S43, and a reset switch S44. The set switch S41 is coupled between the node P31 and the node P41, and an inverted reset signal RST (not shown in fig. 4) is used to control the set switch S41. The reset switch S42 is coupled between the node P31 and the node P42, and the reset signal RST is used to control the reset switch S42. In contrast, the set switch S43 is coupled between the node P32 and the node P42, and the inverted reset signal RST is used to control the set switch S43. The reset switch S44 is coupled between the node P32 and the node P41, and the reset signal RST is used to control the reset switch S44. In operation, when loop filter 124 is not reset, set switch S41 and set switch S43 are turned on, and therefore set switch S41 is controlled to couple node P41 to node P31 and set switch S43 is controlled to couple node P42 to node P32. When the loop filter 124 resets, the reset switch S42 and the reset switch S44 are turned on, and thus the reset switch S42 is controlled to couple the node P42 to the node P31, and the reset switch S44 is controlled to couple the node P41 to the node P32.
On the other hand, referring to fig. 5, fig. 5 is a schematic circuit diagram of a discrete-time integrator according to a first embodiment of the present invention. In the first embodiment, the discrete-time integrator 1244 may include the differential amplifier 501, the capacitances C51 to C54, and the switches S51 to S58. The capacitor C51 is coupled between the operation unit 122 (not shown in fig. 5) and the inverting input terminal of the differential amplifier 501, and the capacitor C52 is coupled between the operation unit 122 and the non-inverting input terminal of the differential amplifier 501. In addition, the capacitor C53 is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier 501, and the capacitor C54 is coupled between the non-inverting input terminal and the inverting output terminal of the differential amplifier 501.
The switch S51 is coupled between the capacitor C51 and the operation unit 122, and the switch S52 is coupled between the capacitor C52 and the operation unit 122. In addition, the switch S53 is coupled between the capacitor C51 and the inverting input terminal of the differential amplifier 501, and the switch S54 is coupled between the capacitor C52 and the non-inverting input terminal of the differential amplifier 501. The switch S55 is coupled between the ground voltage GND and the relay node P51, and the relay node P51 is between the capacitor C51 and the switch S53. The switch S56 is coupled between the ground voltage GND and the relay node P52, and the relay node P52 is between the capacitor C52 and the switch S54. In addition, the switch S57 is coupled between the ground voltage GND and the relay node P53, and the relay node P53 is between the switch S51 and the capacitor C51. The switch S58 is coupled between the ground voltage GND and the relay node P54, and the relay node P54 is between the switch S52 and the capacitor C52. In operation, switches S51, S55 and S52, S56 are on at a first time, and switches S53, S57 and S54, S58 are on at a second time different from the first time. Since the operation principles of the differential amplifier 501, the capacitors C51-C54 and the switches S51-S58 are well known to those skilled in the art, the details of the integration of the differential signal E by the discrete-time integrator 1244 will not be repeated.
As described above, the loop filter 124 is further reset according to the reset signal RST to avoid the periodic sound of the dc signal. Thus, the discrete-time integrator 1244 of the first embodiment may further include a reset switch S59. As shown in fig. 5, the first terminal of the capacitor C53 is coupled to the non-inverting output terminal of the differential amplifier 501 through the node P55, and the first terminal of the capacitor C54 is coupled to the inverting output terminal of the differential amplifier 501 through the node P56. In addition, the reset switch S59 is coupled between the node P55 and the node P56, and the reset signal RST is used to control the reset switch S59. For example, when receiving the reset signal RST at the high level, the reset switch S59 is turned on to reset the loop filter 124.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of a discrete-time integrator according to a second embodiment of the present invention. Since the discrete-time integrator 1244 of the second embodiment is similar to the discrete-time integrator 1244 of the first embodiment, the same points of the two embodiments will not be repeated. Note that, unlike the reset switch S59 of the first embodiment, the discrete-time integrator 1244 of the second embodiment includes a set switch S61, a reset switch S62, a set switch S63, and a reset switch S64. The set switch S61 is coupled between the node P55 and the node P61, and an inverted reset signal RST (not shown in fig. 6) is used to control the set switch S61. The reset switch S62 is coupled between the node P55 and the node P62, and the reset signal RST is used to control the reset switch S62. In contrast, the set switch S63 is coupled between the node P56 and the node P62, and the inverted reset signal RST is used to control the set switch S63. The reset switch S64 is coupled between the node P56 and the node P61, and the reset signal RST is used to control the reset switch S64. In operation, when loop filter 124 is not reset, set switch S61 and set switch S63 are turned on, and therefore set switch S61 is controlled to couple node P61 to node P55 and set switch S63 is controlled to couple node P62 to node P56. When the loop filter 124 resets, the reset switch S62 and the reset switch S64 are turned on, and thus the reset switch S62 is controlled to couple the node P62 to the node P55, and the reset switch S64 is controlled to couple the node P61 to the node P56.
In summary, one of the advantages of the present invention is that the delta-sigma modulator provided by the present invention can process analog signals with different electrical forms through the multiplexer, the modulation circuit and the demultiplexer. In addition, the loop filter of the modulation circuit can also avoid periodic tones by using a mechanism of periodic reset.
The above description is provided for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the appended claims, and all equivalent technical changes that may be made by the practice of the present invention as described in the specification and drawings are intended to be encompassed by the present claims.
Claims (10)
1. A delta-sigma modulator, comprising:
a multiplexer for receiving a first analog signal and a second analog signal and outputting an input signal, wherein the first analog signal and the second analog signal are in different electrical forms, and the multiplexer selects the first analog signal or the second analog signal as the input signal in a time-sharing manner for outputting;
a modulation circuit coupled to the multiplexer for modulating the input signal into a digital signal; and
the demultiplexer is coupled to the modulation circuit and has a first output terminal and a second output terminal for receiving the digital signal, and selects the first output terminal or the second output terminal to output the digital signal in the time-sharing manner.
2. The delta-sigma modulator of claim 1, wherein the modulation circuit comprises:
an operation unit for receiving the input signal and an analog feedback signal and calculating a difference between the input signal and the analog feedback signal to output a difference signal;
a loop filter coupled to the operation unit for processing the difference signal to generate a filtered signal;
a quantizer coupled to the loop filter for quantizing the filtered signal into the digital signal; and
and a digital-to-analog converter coupled to the quantizer and the arithmetic unit for performing digital-to-analog conversion on the digital signal to generate the analog feedback signal.
3. The delta-sigma modulator of claim 2, wherein the first analog signal is a direct current signal and the second analog signal is an alternating current signal.
4. The delta-sigma modulator of claim 3, wherein the loop filter is further reset according to a reset signal when the modulation circuit modulates the first analog signal as the input signal.
5. The delta-sigma modulator of claim 4, further comprising:
a counter coupled to the first output end of the demultiplexer for counting the digital signal outputted from the first output end to generate a first output signal; and
and the decimation filter is coupled with the second output end of the demultiplexer and is used for decimating the digital signal output by the second output end to generate a second output signal.
6. The delta-sigma modulator of claim 4, wherein the loop filter comprises a continuous-time integrator or a discrete-time integrator for integrating the difference signal, and the filtered signal is generated based on an integration result output from the continuous-time integrator or the discrete-time integrator.
7. The delta-sigma modulator of claim 6, wherein the continuous-time integrator comprises:
a differential amplifier;
the first resistor is coupled between the operation unit and an inverting input end of the differential amplifier;
a second resistor coupled between the operation unit and a non-inverting input terminal of the differential amplifier;
a first capacitor coupled between the inverting input terminal and a non-inverting output terminal of the differential amplifier; and
and a second capacitor coupled between the non-inverting input terminal and an inverting output terminal of the differential amplifier.
8. The delta-sigma modulator of claim 7, wherein the continuous-time integrator further comprises:
a first reset switch connected in parallel with the first capacitor between the inverting input terminal and the non-inverting output terminal of the differential amplifier; and
a second reset switch connected in parallel with the second capacitor between the non-inverting input terminal and the inverting output terminal of the differential amplifier;
the reset signal is used for controlling the first reset switch and the second reset switch.
9. The delta-sigma modulator of claim 7, wherein the continuous-time integrator further comprises:
the first reset switch is coupled between a first node and a second node, and the reset signal is used for controlling the first reset switch, wherein a first end of the first capacitor is coupled with the non-inverting output end of the differential amplifier through the first node, and a first end of the second capacitor is coupled with the inverting output end of the differential amplifier through the second node.
10. The delta-sigma modulator of claim 6, wherein the discrete-time integrator comprises:
a differential amplifier;
a first capacitor coupled between the operation unit and an inverting input terminal of the differential amplifier;
a second capacitor coupled between the operation unit and a non-inverting input terminal of the differential amplifier;
a third capacitor coupled between the inverting input terminal and a non-inverting output terminal of the differential amplifier;
a fourth capacitor coupled between the non-inverting input terminal and an inverting output terminal of the differential amplifier;
a first switch coupled between the first capacitor and the operation unit;
a second switch coupled between the second capacitor and the operation unit;
a third switch coupled between the first capacitor and the inverting input terminal of the differential amplifier; and
the fourth switch is coupled between the second capacitor and the non-inverting input terminal of the differential amplifier, wherein the first switch and the second switch are turned on at a first time, and the third switch and the fourth switch are turned on at a second time different from the first time.
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| CN202210306153.3A CN116846400A (en) | 2022-03-25 | 2022-03-25 | Delta-sigma modulator |
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| CN202210306153.3A CN116846400A (en) | 2022-03-25 | 2022-03-25 | Delta-sigma modulator |
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