JPH04233332A - Analog-digital converter - Google Patents

Abstract

PURPOSE: To modify a known integrator and a known analog-digital converter provided with oversampling and noise filtering so that they can be combined. CONSTITUTION: In an analog-digital converter which performs oversampling and has an analog input signal VIN, an analog output signal VOA, and digital output signals VOD and Q and is provided with at least three converter stages U1, U2, and U3 having the same constitution, converter stages U1, U2, and U3 are connected in series with respect to the analog input signal VIN and the analog output signal VOA, and the digital output signal VOD is led through differentiator stages V1, V2, A2, and A3 whose number is equal to the number of preceding connected converter stages and which are connected in series, and their outputs are added.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to oversampling analog-to-digital converters with noise filtering in switched-capacitor technology.

0002

BACKGROUND OF THE INVENTION The realization of high resolution and high linearity analog-to-digital converters with resistor, transistor or capacitor networks is currently only possible with some form of balancing or compensation. Therefore, for many applications, analog-to-digital converters with oversampling and noise filtering represent one viable solution. In this case, it is operated with a higher sampling rate and a lower resolution than is required based on Nyquist theory. A high resolution low frequency signal is then obtained from the low resolution high frequency signal in a subsequent digital, ie essentially non-critical, filter. Oversampling spreads any quantization noise over a larger frequency range, thereby reducing noise within the signal band. During noise filtering, a portion of the quantization noise is shifted from the signal band to another frequency range, thus further improving the signal-to-noise ratio within the signal band.

Integrator circuits are generally used for noise filtering, the signal-to-noise ratio being improved by increasing the order of the integrator. However, third order and higher order integrator circuits are inherently unstable. Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Tsutomu
Paper by Kobayashi, Masayuki Ishikawa, and Takeshi Yoshitome, “16-bit-oversampling-analog-to-digital conversion technology using triple integral noise shaping,” Journal of the Institute of Electrical and Electronics Engineers of America, Solid State Circuits Edition, Vol. SC-2.
From Volume 2, Issue 6, Pages 921-929, December 1978, converting an analog-to-digital converter with oversampling and third-order noise filtering into a first-order three-dimensional
It is known to form it by a cascade connection of two converters, ie also by a first-order integrator. No stability problems arise with these analog-to-digital converters.

In order to further increase the insensitivity to parameter variations, known analog-to-digital converters are not implemented with RC elements for determining the time constant, for example the integrator time constant, but with switched-capacitor technology. be done. In that case, the time constant is no longer the same as the resistance R and the capacitor C.
is not related to the absolute magnitude of , but is related to the ratio of the two capacitors, which is subject to much smaller fluctuations. In principle, analog-to-digital converters with oversampling are operated with high clock frequencies. The bandwidth of the integrator or operational amplifier used therein is again limited above this clock frequency by a certain factor to ensure a sufficiently accurate build-up of the integrator or operational amplifier during each clock period. It should be located. The bandwidth of the integrator or operational amplifier must therefore be located significantly higher than the highest frequency to be processed. Moreover, a high unloaded amplification factor is also required in order to achieve a compensation effect which leads to a reduction of the quantization noise occurring in this converter. High amplification factors, especially in integrated CMOS operational amplifiers, can only be achieved with very high implementation costs and at the expense of speed and thus also of the bandwidth of the operational amplifier. In order to keep the requirements on the operational amplifiers in known analog-to-digital converters low, the capacitance ratio of the two associated capacitors in the integrator was increased. However, this limits the drive range of the analog-to-digital converter.

[0005]K. Nagaraj, T. R. Visw
Anathan, K. Singhal and J. V
Lach's paper “Switched-capacitor circuits with reduced sensitivity to amplifier gain”, Proceedings of the Institute of Electrical and Electronics Engineers, Circuits and Systems, Vol. CAS-34, No. 5, May 1987, No. 571. From pages 574 to 574, switched-capacitor technology is known in which the sensitivity to the effects of the finite no-load amplification factor of operational amplifiers is strongly reduced. In this integrator, the input voltages are stored alternately in each of the two clock phases on one capacitor, ie on the first or second capacitor. In each second phase, an integration step is then already carried out and the first capacitor is discharged via the third capacitor. This integration step is lossy, since due to the finite no-load amplification factor of the operational amplifier, an offset voltage and an offset current occur at its input, which prevent a complete discharge of the first capacitor. Therefore, the voltage occurring across the inputs of the operational amplifier is simultaneously stored in the fourth capacitor. In the subsequent clock phase, the actual integration step then takes place. That is, the second capacitor is discharged via the fifth capacitor. In this case, the second capacitor is not connected directly, but via a fourth capacitor to the negative input of the operational amplifier. The offset voltage at the input of the operational amplifier is thus compensated, so that a complete discharge of the second capacitor takes place. That is, the circuit behaves as if the operational amplifier had infinite no-load amplification.

[0006]

SUMMARY OF THE INVENTION It is an object of the invention to modify the known integrator with oversampling and noise filtering and the known analog-to-digital converter in such a way that a combination of the two is possible. .

[0007]

This object is achieved by an analog-to-digital converter according to claim 1. Advantageous embodiments of the invention are listed in the claims below.

[0008]

The advantages of the analog-to-digital converter according to the invention are high stability, low circuit engineering outlay, low sensitivity to component variations and external disturbance influences, and a larger operating range.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in more detail below with reference to embodiments shown in the drawings. The embodiment according to FIG. 1 has three identically configured converter stages U1 of each first order, with oversampling and third-order noise filtering.
, U2, U3. Two reference potentials VR1, VR2 and five clock signals A, B for each of the three converter stages U1, U2, U3
, C, D, and E are given. In converter stage U1 as input signal the input signal IN of the analog-to-digital converter
However, the output signal VOA of the converter stage U1 is applied to the converter stage U2, and the output signal VOA of the converter stage U2 is applied to the converter stage U3. The output signal VOD of converter stage U3 is applied on the one hand to the input of delay element V2 and on the other hand to one input of adder A3, the other input being connected to the output of delay element V2. has been done. The output of adder A3 is led to one input of adder A1, the other input being driven by the output signal VOD of converter stage U2. The output of the adder A1 is on the one hand the delay element V1
and on the other hand to one input of adder A2, the other input being connected to the output of delay element V1. It is connected at one input to the output of the adder A2 and at the other input to the converter stage U.
The output signal of the adder A4, which is given the output signal VOD of 1, is the output signal OUT of the analog-to-digital converter.
It is used as. Delay element V1 associated with adder A2 or delay element V2 associated with adder A3 each form a digital differentiator stage. The differentiator stages are, in the illustrated embodiment, adjacent converter stages U1, U2,
The output terminals leading to the digital output signal VOD of U3 each pass through a differentiator stage to produce one digital output signal VO.
D and are coupled together to feed each subsequent differentiator stage. A configuration example in which the digital output signals VOD of the converter stages U1, U2, U3 are each conducted via a corresponding number of differentiator stages (equal to the number of previously connected converter stages) and then summed. The advantage compared to is that the total number of differentiator stages and thus also the circuit engineering outlay is reduced. Because especially the adders A1 and A3 or A2 and A4
can each be combined as an adder in a corresponding embodiment.

The converter stages U1, U2, U3 are then identically constructed. An embodiment of such a converter stage U in switched capacitor technology is shown in FIG. The input signal VIN is conducted on the one hand via a controllable electronic switch S3 to one terminal of the capacitor C1 and on the other hand via a controllable electronic switch S4 to one terminal of the capacitor C2. A reference potential VR1 is further connected to the one terminal of the capacitor C1 via a controllable electronic switch S2 and a controllable electronic switch S5 in series.
can be connected. Correspondingly, a reference potential VR2 can also be connected in series to said one terminal of the capacitor C2 via a controllable electronic switch S1 and a controllable electronic switch S6. A controllable electronic switch S7 is provided between the other terminal of capacitor C1 and one terminal of capacitor C3, and a controllable electronic switch S7 is provided between the other terminal of capacitor C2 and the other terminal of capacitor C3. S
8 are connected. Furthermore, the other terminal of the capacitor C1, the other terminal of the capacitor C2 and the one terminal of the capacitor C3 can each be connected to a reference potential via a controllable electronic switch S9, S10 or S11. The other terminal of the capacitor C3 is connected to the inverting input of the operational amplifier OP, its non-inverting input is connected to a reference potential, and its output leads to the output signal VOA. A negative feedback network is connected between the output of operational amplifier OP and its inverting input. It consists of a capacitor C4, one terminal of which can be connected to the reference potential via a controllable electronic switch S12 and to the inverting input via a controllable electronic switch S13, and the other terminal Terminal is operational amplifier OP
is connected to the output end of the Finally, the output of the operational amplifier OP is connected to a capacitor C5 and a controllable electronic switch S
It is connected to the one terminal of the capacitor C3 through 14 series circuits. In the configuration example of the present invention, another negative feedback network is connected in parallel to this negative feedback network. It has a series circuit of two capacitors C6 and C7 between the inverting input and the output of the operational amplifier OP. The mutually connected terminals of capacitors C6 and C7 are further connected to controllable electronic switches S15 or S16, respectively.
can be connected to a reference potential via. This additional negative feedback network prevents the operational amplifier OP from being negatively fed back and thus unstable between the switching phases of the controllable electronic switches S12, S13, S14. The output signal VOA is led to an inverting input terminal of a comparator KO, whose non-inverting input terminal is connected to a reference potential, and whose output terminal is connected to a flip-flop FF provided as a memory element. There is. flip flop F
The inverting and non-inverting outputs of F respectively lead to a clock signal Q (indicated in the figure by an overlined Q) or Q, with the clock signal Q also being used as the output signal VOD.

Clock signals Q and Q are clock signals A
, B, C, D, E as well as electronic switches S1 to S1.
It plays the role of controlling 6. In this case, for controlling electronic switches S3 and S4 and comparator KO, clock signal A is used to control electronic switches S6, S8, S11, S
13, S16 and the flip-flop FF, the clock signal B is used to control the electronic switches S5 and S7.
For the control of the clock signal C, the electronic switch S9
A clock signal D is used for the control of the electronic switches S10, S12, S14 and S15, and a clock signal E is used for the control of the electronic switches S10, S12, S14 and S15. The electronic switch S1 and thus the electronic switch S2 are controlled by the clock signal Q and the electronic switch S2 by the clock signal Q.

The course of the clock signals A, B, C, D and E is shown in FIG. 3 with time t on the horizontal axis. These clock signals are periodic. That is, pulses of a specific duration occur repeatedly at specific time intervals. Clock signals A, B and C are then mutually temporally such that first one pulse occurs during clock signal A, then one pulse occurs during clock signal B, and again following one. Two pulses are arranged to occur during clock signal C. Thereafter, one pulse occurs again in the case of clock signal A (and so on), and at this time clock signals A, B, and C are built up so that they do not overlap. That is, only after the decay of the pulses of one clock signal does the rise of the pulses of the other clock signal take place. Non-overlapping clock signals A, B, C
This eliminates the influence of the finite switching time of the electronic switch on the behavior of the analog-to-digital converter. During clock signal D, a pulse is emitted that starts at the same time as the pulse of clock signal A and ends at the same time as the pulse of clock signal B. Finally, in the case of clock signal E, a pulse is emitted which starts at the same time as the pulse of clock signal C and ends at the same time as the pulse of clock signal A. For clock signals Q and Q, on the other hand, it is not necessary to indicate a precise temporal correspondence. This is because these clock signals are also related to the input signal VIN. Finally, it should be mentioned that by adding another converter stage and an attached differentiator stage, a higher order stable oversampling analog-to-digital converter is realized.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of an analog-to-digital converter according to the invention with oversampling and noise filtering in switched-capacitor technology; FIG.

2 shows a converter stage according to the invention in the analog-to-digital converter according to FIG. 1; FIG.

FIG. 3 shows the time course of the clock signal of the analog-to-digital converter according to FIG. 1;

[Explanation of symbols]

A to E Clock signals A1 to A4 Adder FF Flip-flop KO Comparator OP Operational amplifier Q, bar Q Clock signals S1 to S16 Controllable switches U1 to U3
Converter stage V1, V2 Delay element VIN Input signal VOA Analog output signal VOD Digital output signal VR1, VR2 Reference potential

Claims (4)

[Claims] [Claim 1] Each analog input signal (VIN)
are driven by analog output signals (VO
At least three identically configured converter stages (U1
, U2, U3), the converter stages (U1, U2
, U3) are connected in series with respect to the analog input signal (VIN) and the analog output signal (VOA), and the digital output signal (V
OD) are each conducted through a number of series-connected differentiator stages (V1, V2, A2, A3) equal to the number of converter stages (U1, U2) respectively connected before; and an operational amplifier (OP) which is added and each converter stage (U1, U2, U3) supplies at its output the analog output signal (VOA) of the respective converter stage (U1, U2, U3); A comparator (KO) connected after the amplifier (OP) and a comparator (KO) connected after the comparator (KO) for the respective converter stage (U1, U2,
a memory element (FF) which provides the digital output signal (VOD) of the converter stage (U1, U2
, U3), each analog input signal (VIN)
is connected on the one hand to one terminal of the first capacitor (C1) via the first controllable switch (S3) and on the other hand to the second capacitor (C1) via the fourth controllable switch (S4). C2) and said one terminal of the first capacitor (C1) is further connected in series to a first reference potential via a second and third controllable switch (S2, S5). (VR1) can be connected, and the second
A fifth and a sixth controllable switch (S1, S6) are further connected in series to the one terminal of the capacitor (C2).
A second reference potential (VR2) can be connected via
The other terminal of the first capacitor (C1) in each converter stage (U1, U2, U3) is connected on the one hand to the reference potential via the seventh controllable switch (S9) and on the other hand to the eighth a ninth controllable switch (S11) communicating with the reference potential via a controllable switch (S7);
The third capacitor (C3) is connected to one terminal of the third capacitor (C3), and the other terminal of the third capacitor (C3) is connected to the inverting input terminal of the operational amplifier (OP).
1, U2, U3), the second capacitor (
The other terminal of C2) is connected to the reference potential via a tenth controllable switch (S10) on the one hand and to the first controllable switch (S10) on the other hand.
1 controllable switch (S8) to the operational amplifier (
is connected to the inverting input terminal of the converter stage (U1
, U2, U3), the output of the operational amplifier (OP) is connected in series with a twelfth controllable switch (
S14) and the third capacitor (C5) via the fourth capacitor (C5).
a thirteenth controllable switch (S12) which leads to the reference potential on one terminal of the capacitor (C3) and on the other hand via the fifth capacitor (C4) and the inverting input of the operational amplifier (OP). a fourteenth controllable switch (S13) connected to the end, and the first and fourth switches (S3, S4) in the converter stage (U1, U2, U3) 1 clock signal (A), the sixth, ninth, eleventh and fourteenth switches (S6,
S11, S8, S13) are activated by the second clock signal (B), and the third and eighth switches (S5, S7) are activated by the third clock signal (B).
The clock signal (C) causes the seventh switch (S9) to
is activated by the fourth clock signal (D), the tenth, twelfth, and thirteenth switches (S10, S12, S14) are activated by the fifth clock signal (E), and the fifth switch (S1) is activated by the fifth clock signal (E).
) is inverted by the digital output signal (bar Q),
Also, the second switch (S2) outputs the digital output signal (Q
), and the first, second and third clock signals (A, B, C) are pulses that occur one after another, repeat periodically, and turn on the respective associated switches. The fourth and fifth
The clock signals (D, E) of the first clock signal (A) start with a pulse of the first clock signal (A) and the second clock signal (D, E) starts with a pulse of the first clock signal (A).
B) or starts with a pulse of the third clock signal (C) and starts with a pulse of the first clock signal (C).
An analog-to-digital converter, characterized in that a pulse is used which brings the respective associated switch into conduction, terminating with the pulse of A). 2. In the converter stages (U1, U2, U3), the output terminal of each operational amplifier (OP) is connected to one terminal of a seventh capacitor (C7), and the output terminal of the operational amplifier (OP) is connected to one terminal of a seventh capacitor (C7). The inverting input terminal is connected to the sixth capacitor (C6
), and the other terminals of the sixth and seventh capacitors (C6, C7) are connected to each other, one by the second clock signal (B) and the other by the second clock signal (B). 2 controlled by the clock signal (E) of 5
Claim 1, characterized in that it is connectable to a reference potential via two parallel-connected switches (S15, S16).
The analog-to-digital converter described. 3. Analog-to-digital converter according to claim 1, characterized in that the pulses of the first, second and third clock signals (A, B, C) do not overlap. 4. Adjacent converter stages (U1, U2, U3
) leads to a digital output signal (VOD) through a differentiator stage (V1, V2, A2, A3), respectively.
The output signal of each differentiator stage (V1, V2, A2, A3) is added with the digital output signal (VOD) of the converter stage (U1, U2, U3) and the respective subsequent differentiator stage (V1, A2) 4. Analog-to-digital converters according to claim 1, characterized in that they are connected to each other in such a way that the converters are supplied with one another.