JP2016039348A - 半導体回路装置および半導体回路装置の試験方法 - Google Patents
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Abstract
Description
Claims (7)
- 複数のチップと、前記複数のチップの所定の面に配置された複数の端子を相互に接続する接続部とを有する半導体回路装置において、
前記複数のチップの各々の端子は、複数の第1グループまたは他のグループのいずれかに属し、
前記複数の第1グループのうち、1つの第1グループに属する端子は、所定間隔より大きい間隔で配置され、
前記1つの第1グループに属する複数の端子のうちの第1端子と、前記第1端子に隣接する端子であって、前記複数の第1グループのうちの他の第1グループまたは前記他のグループのいずれかに属する複数の端子のうちの第2端子との間隔は、前記所定間隔であり、
前記複数のチップの各々は、複数の端子のうち、信号を伝達する端子を第1グループ毎に選択する選択部を有することを特徴とする半導体回路装置。 - 請求項1に記載の半導体回路装置において、
前記他のグループは、互いに接続される複数の端子をそれぞれ含む複数の第2グループを含み、
前記複数の第2グループのうち、1つの第2グループに属する複数の端子と、前記複数の第2グループのうち、他の第2グループに属する複数の端子との間隔は、前記所定間隔より大きいことを特徴とする半導体回路装置。 - 請求項2に記載の半導体回路装置において、
前記他のグループは、複数の端子を含む第3グループをさらに含み、
前記第3グループに属する複数の端子の各々と、前記複数の第2グループに属する端子との間隔は、前記所定間隔より大きく、
前記第3グループに属する複数の端子同士の間隔は、前記所定間隔より大きいことを特徴とする半導体回路装置。 - 請求項1ないし請求項3のいずれか1項に記載の半導体回路装置において、
前記第1端子に隣接する端子は、前記他の第1グループまたは前記他のグループのいずれかに属することを特徴とする半導体回路装置。 - 請求項4に記載の半導体回路装置において、
前記第1端子に隣接する端子は、互いに異なるグループに属することを特徴とする半導体回路装置。 - 複数のチップと、前記複数のチップの所定の面に配置された複数の端子を相互に接続する接続部とを有し、前記複数のチップの各々の端子は、複数の第1グループまたは他のグループのいずれかに属し、前記複数の第1グループのうち、1つの第1グループに属する端子は、所定間隔より大きい間隔で配置され、前記1つの第1グループに属する複数の端子のうちの第1端子と、前記第1端子に隣接する端子であって、前記複数の第1グループのうちの他の第1グループまたは前記他のグループのいずれかに属する複数の端子のうちの第2端子との間隔が、前記所定間隔である半導体回路装置の試験方法において、
前記半導体回路装置をテストするテスト装置が、前記接続部により互いに接続された端子を含む信号経路をテストし、
前記テストの結果に基づいて、前記複数のチップの各々が有する選択部が、複数の端子のうち、信号を伝達する端子を第1グループ毎に選択することを特徴とする半導体回路装置の試験方法。 - 請求項6に記載の半導体回路装置の試験方法において、
前記テスト装置が、前記複数の第1グループから検査対象の第1グループを選択し、前記検査対象の第1グループに対応する信号経路および前記検査対象以外の第1グループに対応する信号経路に、第1レベルのデータおよび前記第1レベルと異なる第2レベルのデータをそれぞれ転送する第1テストと、前記検査対象の第1グループに対応する信号経路および前記検査対象以外の第1グループに対応する信号経路に、前記第2レベルのデータおよび前記第1レベルのデータをそれぞれ転送する第2テストとを第1グループ毎に実行し、
前記第1テストおよび前記第2テストの結果に基づいて、前記選択部が、複数の端子のうち、信号を伝達する端子を第1グループ毎に選択することを特徴とする半導体回路装置の試験方法。
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US14/810,831 US9823291B2 (en) | 2014-08-11 | 2015-07-28 | Semiconductor device and method of testing semiconductor device |
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JPH1174407A (ja) * | 1997-08-29 | 1999-03-16 | Mitsubishi Electric Corp | 半導体装置 |
JP2006019328A (ja) * | 2004-06-30 | 2006-01-19 | Nec Corp | 積層型半導体装置 |
JP2011226917A (ja) * | 2010-04-20 | 2011-11-10 | Mitsubishi Electric Corp | 自己診断装置、自己診断方法及び自己診断機能を備えた電子機器 |
US20150084689A1 (en) * | 2013-09-26 | 2015-03-26 | SK Hynix Inc. | Semiconductor chip including a spare bump and stacked package having the same |
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JP4708176B2 (ja) | 2005-12-08 | 2011-06-22 | エルピーダメモリ株式会社 | 半導体装置 |
JP5416200B2 (ja) | 2009-02-27 | 2014-02-12 | 株式会社日立製作所 | 半導体装置 |
US8659141B2 (en) * | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
JP2013131534A (ja) | 2011-12-20 | 2013-07-04 | Elpida Memory Inc | 半導体装置 |
US8895981B2 (en) | 2011-12-28 | 2014-11-25 | Altera Corporation | Multichip module with reroutable inter-die communication |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH1174407A (ja) * | 1997-08-29 | 1999-03-16 | Mitsubishi Electric Corp | 半導体装置 |
JP2006019328A (ja) * | 2004-06-30 | 2006-01-19 | Nec Corp | 積層型半導体装置 |
JP2011226917A (ja) * | 2010-04-20 | 2011-11-10 | Mitsubishi Electric Corp | 自己診断装置、自己診断方法及び自己診断機能を備えた電子機器 |
US20150084689A1 (en) * | 2013-09-26 | 2015-03-26 | SK Hynix Inc. | Semiconductor chip including a spare bump and stacked package having the same |
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US20160043029A1 (en) | 2016-02-11 |
US9823291B2 (en) | 2017-11-21 |
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