JP2016018569A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform error correction of a register by a relatively small circuit.SOLUTION: A semiconductor integrated circuit includes registers a0-a2, b0-b2, c0-c2 to which row addresses and column addresses are allocated, and which store 1-bit values of 0 or 1, respectively. Error detection circuits pa-pc provided in each row address output a first error detection signal when any value in a register group of the same row address changes. Error detection circuits p0-p2 provided in each column address output a second error detection signal when any value in a register group of the same column address changes. A normal value writing unit 2 specifies a register c1 in which an error has occurred on the basis of the first error detection signal and the second error detection signal, and inverts a stored value of the register c1 from 1 to 0 or from 0 to 1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit.

  A phenomenon called soft error is known in which the value of a bit stored in a memory is inverted by alpha rays and neutron rays from the universe. As a technique for correcting an error caused by a soft error, there has been a technique using ECC (Error Correcting Code).

  On the other hand, even in a large-scale logic circuit that is becoming finer, there is a concern about the influence of a soft error on a register group that stores setting values and the like.

JP-A-9-55077 JP 2007-248378 A

  If an attempt is made to apply ECC to counter a soft error in a register, the ECC is generated and stored at the time of data writing, so the circuit area increases due to the storage area and the like.

  According to one aspect of the invention, a row address and a column address are assigned, a plurality of registers each storing a 1-bit value of 0 or 1, and a first row of the same row address among the plurality of registers. A first error detection circuit provided for each row address, which outputs a first error detection signal when any of the values of the register group changes, and the first column of the same column address among the plurality of registers; A second error detection circuit provided for each of the column addresses, which outputs a second error detection signal when any one of the two register groups changes, the first error detection signal, and the first error detection signal A normal value writing unit that identifies the first register in which an error has occurred based on the error detection signal of 2 and inverts the first stored value of the first register from 1 to 0 or from 0 to 1; A semiconductor integrated circuit having .

  According to the disclosed semiconductor integrated circuit, register error correction can be performed with a relatively small circuit.

1 is a diagram illustrating an example of a semiconductor integrated circuit according to a first embodiment; It is a figure which shows an example of the semiconductor integrated circuit of 2nd Embodiment. It is a figure which shows an example of the register group and error detection part of 2nd Embodiment. It is a figure which shows an example of a register | resistor. It is a timing chart which shows the operation example at the time of the error correction of a register | resistor. It is a figure which shows an example of an error detection circuit. It is a figure which shows an example of a normal value holding | maintenance part. 7 is a timing chart illustrating an example of operations of an error detection circuit and a normal value holding unit when an error occurs in a register included in a register group. 6 is a timing chart illustrating an example of operations of an error detection circuit and a normal value holding circuit when an error occurs in a register of the error detection circuit. It is a flowchart which shows the flow of an example of operation | movement of the semiconductor integrated circuit at the time of error generation. It is a figure which shows an example of the semiconductor integrated circuit of 3rd Embodiment. 14 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the third embodiment (part 1); 12 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the third embodiment (part 2);

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a semiconductor integrated circuit according to the first embodiment.

The semiconductor integrated circuit 1 includes registers a0, a1, a2, b0, b1, b2, c0, c1, c2, error detection circuits pa, pb, pc, p0, p1, p2, and a normal value writing unit 2.
The registers a0 to a2, b0 to b2, and c0 to c2 each store a 1-bit value of 0 or 1. The stored value is a set value used for the operation of the semiconductor integrated circuit 1.

In addition, row addresses and column addresses are assigned to the registers a0 to a2, b0 to b2, and c0 to c2.
In the following description, the row addresses are a, b, and c, the same row address a is stored in the registers a0, a1, and a2, the same row address b is stored in the registers b0, b1, and b2, and the registers c0, c1, and c2. It is assumed that the same row address c is assigned to c2. The column addresses are 0, 1, and 2. The same column address 0 is stored in the registers a0, b0, and c0, the same column address 1 is stored in the registers a1, b1, and c1, and the registers a2, b2, and c2 are stored. It is assumed that the same column address 2 is assigned.

  One of the row address and the column address may indicate a bit position. For example, if the column addresses 0 to 2 indicate the bit positions, the register a0 is a register that stores the least significant bit of the data at the row address a, and the register a2 is a register that stores the most significant bit of the data at the row address a. .

  In the example of FIG. 1, the registers a0 to a2, b0 to b2, and c0 to c2 are arranged in a matrix. However, the registers a0 to a2, b0 to b2, and c0 to c2 may be arranged in any way. , B, c and column addresses 0, 1, 2 are assigned. For example, the registers a0 to a2, b0 to b2, and c0 to c2 may be arranged in one column. In FIG. 1, the clock signals supplied to the registers a0 to a2, b0 to b2, and c0 to c2 are not shown.

  The error detection circuits pa, pb, pc are provided corresponding to the respective row addresses a, b, c. The error detection circuit pa is an error detection signal indicating that an error has been detected when any one of the registers a0 to a2 of the row address a changes among the registers a0 to a2, b0 to b2, and c0 to c2. Is output. The error detection circuit pb outputs an error detection signal indicating that an error has been detected when any value of the registers b0 to b2 at the row address b changes. The error detection circuit pc outputs an error detection signal indicating that an error has been detected when any one of the registers c0 to c2 at the row address c changes.

  On the other hand, error detection circuits p0, p1, and p2 are provided corresponding to the column addresses 0, 1, and 2, respectively. The error detection circuit p0 is an error indicating that an error has been detected when any of the registers a0, b0, c0 at the column address 0 among the registers a0-a2, b0-b2, c0-c2 changes. A detection signal is output. The error detection circuit p1 outputs an error detection signal indicating that an error has been detected when any one of the registers a1, b1, and c1 at the column address 1 changes. The error detection circuit p2 outputs an error detection signal indicating that an error has been detected when any one of the registers a2, b2, and c2 at the column address 2 changes.

As a method for detecting a change in the value of a register group at each row address or each column address by the error detection circuits pa, pb, pc, p0, p1, and p2, for example, the following methods are available.
The error detection circuit pa will be described as an example. For example, the error detection circuit pa generates a parity bit by performing an XOR operation on the values of the registers a0, a1, and a2. Then, the error detection circuit pa detects whether the value of any of the registers a0, a1, and a2 has changed by comparing the generated parity bit with a normal parity bit stored in advance. it can. If the generated parity bit is different from the normal parity bit, the error detection circuit pa outputs an error detection signal indicating that an error has been detected.

  The normal value writing unit 2 stores a register in which an error has occurred (the value is inverted) based on the error detection signals from the error detection circuits pa, pb, and pc and the error detection signals from the error detection circuits p0, p1, and p2. Identify. Since the error detection circuits pa, pb, pc, p0, p1, and p2 correspond to the row addresses a, b, and c or the column addresses 0, 1, and 2, they are output from the error detection circuits pa, pb, and pc. The row address of the register in which the error has occurred is specified from the error detection signal. Further, the column address of the register in which the error has occurred is specified from the error detection signals output from the error detection circuits p0, p1, and p2. As a result, the register in which the error has occurred is specified.

Further, the normal value writing unit 2 inverts the value to be written to the specified register from 1 to 0 or from 0 to 1. As a result, error correction is performed.
The normal value writing unit 2 may be a processor (for example, a CPU (Central Processing Unit)). When the processor is used, an interrupt to the processor is asserted based on the error detection signals output from the error detection circuits pa to pc and p0 to p2, and the processor inverts the value of the register in which the error has occurred.

(Operation example of semiconductor integrated circuit)
Hereinafter, an operation example at the time of error detection / correction by the semiconductor integrated circuit 1 will be described. In the following description, an example in which an error (for example, a soft error) occurs in the register c1 and the value (bit) is inverted from 0 to 1 or from 1 to 0 will be described.

  When the value of the register c1 is inverted, the error detection circuit pc outputs an error detection signal indicating that an error has occurred in response to a change in the values of the registers c0 to c2. On the other hand, the error detection circuit p1 also outputs an error detection signal indicating that an error has occurred in response to changes in the values of the registers a1, b1, and c1.

  The normal value writing unit 2 receives an error detection signal from the error detection circuits pc and p1, and receives a register c1 in which an error has occurred from the row address c to which the error detection circuit pc belongs and the column address 1 to which the error detection circuit p1 belongs. Is identified. Then, the normal value writing unit 2 inverts the stored value of the register c1 and corrects the error occurring in the register c1.

  As described above, the semiconductor integrated circuit 1 assigns the row address and the column address to the register, detects a change in the value of the register group for each of the same row address and the same column address, and an error specified from the detection result occurs. The error is corrected by inverting the value stored in the register. As a result, for example, a read operation performed when ECC is used and an ECC storage area are not required, so that register error detection / correction can be performed with a relatively small circuit.

  One of the error detection circuits pa to pc or the error detection circuits p0 to p2 may be one. For example, when an address of 1 row n (n ≧ 2) column is assigned to each register, there is one error detection circuit corresponding to the row address.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor integrated circuit according to the second embodiment.
The semiconductor integrated circuit 3 according to the second embodiment includes a processor 4, a register group 5, an error detection unit 6, a normal value holding unit 7, an interrupt control unit 8, and a circuit unit 9.

  For example, the processor 4 outputs a clock signal CLK, an address signal ADD, a byte enable signal BE, and a write signal W to the register group 5 and the like. The processor 4 is connected to the register group 5 and the error detection unit 6 by, for example, a data bus. Further, when the interrupt signal Int output from the interrupt control unit 8 is asserted, the processor 4 specifies the register in which an error has occurred in the register group 5 based on the error detection signal from the error detection unit 6, and Error correction is performed by inverting the stored value of the register. That is, the processor 4 performs the function of the normal value writing unit 2 of the semiconductor integrated circuit 1 according to the first embodiment.

  The processor 4 is, for example, a CPU, a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The processor 4 may be a combination of two or more elements among CPU, MPU, DSP, ASIC, and PLD. The processor 4 may be a multiprocessor.

Each register included in the register group 5 is assigned a row address and a column address, and stores a 1-bit value of 0 or 1, respectively.
The error detection unit 6 has a plurality of error detection circuits provided for each row address and column address, and detects a change in the value of the register group for each row address or column address included in the register group 5 In addition, an error detection signal indicating that an error has been detected is output.

  The normal value holding unit 7 holds (maintains) the output state of the normal value (the stored value of the register before the occurrence of the error) for the circuit unit 9 even if an error is detected by the error detection unit 6. To do. Based on the error detection signal, the normal value holding unit 7 inverts the value of the register in which the error has occurred and outputs it to the circuit unit 9. For this reason, even if the value of a certain register is inverted due to an error, the value of the register supplied to the circuit unit 9 remains a normal value. The normal value holding unit 7 instructs the interrupt control unit 8 to generate the interrupt signal Int when the error detection unit 6 detects an error.

  When the generation of the interrupt signal Int is instructed from the normal value holding unit 7, the interrupt control unit 8 asserts the interrupt signal Int supplied to the processor 4. The interrupt control unit 8 negates the interrupt signal Int when there is no instruction to generate the interrupt signal Int from the normal value holding unit 7.

  The circuit unit 9 is a circuit unit that executes a specific function of the semiconductor integrated circuit 1. The circuit unit 9 executes a specific function based on the value held in the register group 5. The value supplied to the circuit unit 9 is maintained at a normal value by the function of the normal value holding unit 7 described above.

(Example of register group and error detection unit)
Hereinafter, an example of the register group 5 and the error detection unit 6 will be described.
FIG. 3 is a diagram illustrating an example of a register group and an error detection unit according to the second embodiment.

  The same elements as those shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is partially omitted. In the register group 5, the write signal W and the like input from the processor 4 are not shown.

  The register group 5 includes nine registers a0 to a2, b0 to b2, and c0 to c2 to which row addresses and column addresses are assigned. Note that the number of registers is not particularly limited to this number.

  As in the register group shown in the semiconductor integrated circuit 1 of the first embodiment, the row addresses are a, b, and c, and the same row address a is stored in the registers a0, a1, and a2, and the registers b0, Assume that the same row address b is assigned to b1 and b2, and the same row address c is assigned to registers c0, c1 and c2. The column addresses are 0, 1, and 2. The same column address 0 is stored in the registers a0, b0, and c0, the same column address 1 is stored in the registers a1, b1, and c1, and the registers a2, b2, and c2 are stored. It is assumed that the same column address 2 is assigned.

  In the following description, the row addresses a, b, and c are specified by the address signal ADD output from the processor 4 as shown in FIG. 2, the column addresses 0, 1, and 2 indicate the bit positions, and the processor 4 Is specified by the multi-bit data output by. Here, assuming that the column address 0 indicates the least significant bit and the column address 2 is the most significant bit, for example, when 3-bit data “010” is output from the processor 4, the column address 1 is designated.

  In the following description, the output signals of the registers a0 to a2 are the signals da0, da1, and da2, the output signals of the registers b0 to b2 are the signals db0, db1, and db2, and the output signals of the registers c0 to c2 are the signals dc0, dc1, and dc2. write.

  The error detection unit 6 includes error detection circuits pa to pc and p0 to p2 provided for each row address and column address. Each of the error detection circuits pa to pc and p0 to p2 detects a change in the values of the registers a0 to a2, b0 to b2, and c0 to c2 belonging to the row addresses a, b, c or the column addresses 0, 1, 2. . Hereinafter, the error detection signals output from the error detection circuits pa to pc are expressed as signals xap, xbp, and xcp, and the error detection signals output from the error detection circuits p0 to p2 are expressed as signals x0p, x1p, and x2p. The signals xap, xbp, xcp, x0p, x1p, and x2p represent, for example, that an error has occurred when the value is “1”.

(Example of register)
Hereinafter, an example of the registers a0 to a2, b0 to b2, and c0 to c2 will be described.
FIG. 4 is a diagram illustrating an example of a register.

In the following, an example of the register c1 is shown, but other registers can be realized with the same circuit configuration.
The register c1 has a function of further inverting the value inverted by an error, for example, under the control of the processor 4. The register c1 includes a flip-flop 10, a NOT circuit 11, and a selector 12.

  The flip-flop 10 holds the value output from the selector 12 in synchronization with the rise (or fall) of the clock signal CLK, and outputs the held value as the signal dc1. The flip-flop 10 also has an asynchronous set terminal 10a and an asynchronous reset terminal 10b that are used when setting the initial value of the flip-flop 10. For example, in an initial state such as when the power is turned on, a signal for setting an initial value is set to the asynchronous set terminal 10a when the initial value of the flip-flop 10 is 1, and to the asynchronous reset terminal 10b when the initial value is 0. Is supplied from the processor 4.

The NOT circuit 11 inverts the value of the signal dc1 and outputs it to the selector 12.
The selector 12 selects either the signal dc1 or the signal dc1 inverted by the NOT circuit 11 based on the selection signal, and outputs the selected signal to the flip-flop 10.

  The selection signal is generated based on the address signal ADD, the byte enable signal BE, the write signal W, and data (for example, the above-described 3-bit data). The selection signal input to the register c1 is when the row address c is designated by the address signal ADD, the byte enable signal BE is valid, the write signal W is “1”, and the column address 1 is designated by data. , “1”. At this time, the value stored in the flip-flop 10 is inverted from 0 to 1 or from 1 to 0.

Hereinafter, an operation example of the register c1 based on various signals output from the processor 4 will be described.
(Register operation example)
FIG. 5 is a timing chart showing an operation example at the time of register error correction.

  FIG. 5 shows an example of the clock signal CLK, the address signal ADD, the byte enable signal BE, the write signal W, and the data flowing through the data bus that are output from the processor 4 during the write-back process.

  Further, an example of a signal dc1 output from the register c1 and a selection signal input to the selector 12 of the register c1 is shown. In FIG. 5, an error occurs in the register c1 before the timing t0, and the value stored in the register c1 (flip-flop 10) is inverted to “1”, that is, the signal dc1 is “1”. It shall be.

  When an error occurs in the register c1, the interrupt control unit 8 asserts an interrupt signal Int to the processor 4. Then, the processor 4 identifies the register c1 in which an error has occurred based on the error detection signal output from the error detection unit 6. Then, the processor 4 designates the row address c to which the register c1 belongs by the address signal ADD at the timing t0, and designates the column address 1 by the 3-bit data “010”.

At timing t0, the processor 4 enables the byte enable signal BE so that the value of the register c1 can be rewritten.
At timing t1, the processor 4 causes the write signal W to rise to “1” in synchronization with the rise of the clock signal CLK, and the selection signal also becomes “1”. At this time, the selector 12 selects the signal dc1 inverted to “0” by the NOT circuit 11 and outputs it to the flip-flop 10.

  At timing t2, the signal dc1 falls to “0” in synchronization with the rise of the clock signal CLK. Thereby, the error generated in the register c1 is corrected. Further, in synchronization with the rising of the clock signal CLK, the write signal W falls and the selection signal also falls.

  When a normal value is output from the register c1, an interrupt signal Int to the processor 4 by the interrupt control unit 8 is negated. As a result, the designation of the row address c from the processor 4 and the data output for designating the column address 1 are stopped, and the byte enable signal BE is also invalidated.

  As described above, the processor 4 designates data having a plurality of bits (3 bits in the above example) with the column address to which the error occurrence register belongs as a bit position. Error correction is not performed in the register at the column address corresponding to the bit position having the value “0” among the plurality of bits, and error correction is performed in the register at the column address corresponding to the bit position having the value “1”. As a result, correction can be performed for each register (in units of 1 bit).

  In the above example, the processor 4 sets the write signal W to “1” only for one clock cycle (between timings t1 and t2). When the write signal W is “1” for an even number of clock cycles, for example, for two clock cycles, the selection signal is also “1” for two clock cycles. Then, the signal dc1 inverted from “1” to “0” at the first clock is further inverted from “0” to “1” at the second clock, and returns to the original state. In order to prevent this, as described above, the processor 4 sets the write signal W to “1” only for an odd clock period, for example, for one clock period.

For other registers, error correction is performed by the same operation.
(Example of error detection circuit)
Hereinafter, an example of the error detection circuits pa to pc and p0 to p2 will be described.

FIG. 6 is a diagram illustrating an example of an error detection circuit. Hereinafter, the error detection circuit pc will be described as an example, but other error detection circuits can be realized with the same circuit configuration.
The error detection circuit pc is a circuit that detects a change in the values of the registers c0, c1, and c2 at the row address c by an even parity method.

The error detection circuit pc includes XOR circuits 13 and 14, a register 15, and an XOR circuit 16.
The XOR circuit 13 performs an XOR operation on the signal dc1 output from the register c1 and the signal dc2 output from the register c2, and outputs the operation result to the XOR circuit 14. The XOR circuit 14 performs an XOR operation on the XOR operation result output from the XOR circuit 13 and the signal dc0 output from the register c0, and outputs the operation result to the register 15 and the XOR circuit 16. The XOR operation result output from the XOR circuit 14 becomes a parity bit generated by the even parity system of the signals dc0 to dc2.

  The register 15 holds the parity bit output from the XOR circuit 14 in synchronization with the rising edge (or falling edge) of the clock signal CLK, and outputs the held parity bit to the XOR circuit 16.

  The XOR circuit 16 performs an XOR operation on the parity bit output from the XOR circuit 14 and the parity bit held in the register 15 and outputs the operation result as a signal xpc to the normal value holding unit 7 shown in FIG. To do. In the example shown in FIG. 6, when the parity bit output from the XOR circuit 14 and the parity bit held in the register 15 do not match, the signal xpc becomes “1” indicating the occurrence of an error.

  The signal xpc may also be output to the processor 4. The processor 4 specifies that the register c1 is an error occurrence register when both the value of the signal xpc and the value of the signal xp1 output from the error detection circuit p1 are “1”.

  In the error detection circuit pc, there is a possibility that an error occurs in the register 15 and the value of the held parity bit is inverted. However, since the register 15 updates the parity bit in synchronization with the clock signal CLK, the parity bit is automatically normal if the signals dc0 to dc2 supplied from the registers c0, c1, and c2 are correct. Is written back to the correct value and the error is corrected.

(Example of normal value holding unit)
Hereinafter, an example of the normal value holding unit 7 will be described.
FIG. 7 is a diagram illustrating an example of a normal value holding unit. FIG. 7 shows a circuit portion that supplies a normal value to the circuit portion 9 when an error occurs and the signal dc1 output from the register c1 changes. Although the illustration regarding the other registers is omitted, the circuit is similar.

The normal value holding unit 7 includes an AND circuit 17, a register 18, a NOT circuit 19, and a selector 20.
The AND circuit 17 performs an AND operation on the signal xpc output from the error detection circuit pc shown in FIG. 3 and the signal xp1 output from the error detection circuit p1. The AND operation result is supplied to the clock input terminal of the register 18.

  The data input terminal of the register 18 is connected to an inverted output terminal that inverts and outputs the value held by the register 18. The register 18 inverts the held value in synchronization with the rise (or fall) of the AND operation result supplied from the AND circuit 17 and outputs it as a selection signal of the selector 20. The selection signal becomes “1” when an error occurs in the register c1, as will be described later.

The NOT circuit 19 inverts the value of the signal dc1 output from the register c1 shown in FIG.
When the selection signal supplied from the register 18 is “0”, the selector 20 selects the signal dc1 output from the register c1 and outputs it as the signal Dc1. When the selection signal is “1”, the selector 20 selects the signal dc1 inverted by the NOT circuit 19 and outputs it as the signal Dc1.

  In the semiconductor integrated circuit 3 of the second embodiment, the selection signal supplied from the register 18 to the selector 20 generates a signal that instructs the interrupt control unit 8 shown in FIG. 2 to generate the interrupt signal Int. Also used when. For example, the signal instructing the generation of the interrupt signal Int is an OR of selection signals generated for each register of the register group 5.

  Further, the selection signal becomes “1” when an error occurs in the register c1, as will be described later. Since this selection signal is generated for each register of the register group 5, the processor 4 may specify the error occurrence register from the selection signal that is “1” when the interrupt signal Int is generated. Good.

(Operation example 1 of error detection circuit and normal value holding unit)
Hereinafter, operation examples of the error detection circuit and the normal value holding unit will be described.
FIG. 8 is a timing chart illustrating an example of the operation of the error detection circuit and the normal value holding unit when an error occurs in a register included in the register group. FIG. 8 shows an example in the case where an error occurs in the register c1. The clock signal CLK, the signal dc1 output from the register c1, the signals of the error detection circuits pc and p1, and the normal value holding unit 7 are shown. The state of an example of the signal of each part of is shown.

Note that the error detection circuit p1 and the error detection circuit pc shown in FIG. 6 are similar circuits, and therefore, in FIG.
Also, the parity bit that is the output of the register 15 of the error detection circuit pc and the initial value of the output of the XOR circuit 14 are “0”, the parity bit that is the output of the register 15 of the error detection circuit p1 and the initial value of the output of the XOR circuit 14 The value is assumed to be “1”.

  In the example of FIG. 8, an error occurs in the register c1 at the timing t3, and the value of the signal dc1 output from the register c1 is inverted from “0” to “1”. As the value of the signal dc1 changes, the output of the XOR circuit 14 of the error detection circuit pc rises to “1”. At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc and the value of the output of the register 15 do not match, so that the signal xpc rises to “1”. As the value of the signal dc1 changes, the output of the XOR circuit 14 of the error detection circuit p1 falls to “0”. As a result, the value of the output of the XOR circuit 14 of the error detection circuit p1 does not match the value of the output of the register 15, so that the signal xp1 rises to “1”.

  Further, at timing t3, the signals xpc and xp1 rise to “1”, whereby the output of the AND circuit 17 of the normal value holding unit 7 rises to “1”. Further, in synchronization with the rise of the output of the AND circuit 17, the register 18 inverts the held value from “0” to “1”, so that the output of the register 18 rises to “1”. Further, when the signal dc1 rises to “1”, the output of the NOT circuit 19 of the normal value holding unit 7 falls to “0”.

  At timing t3, the output of the register 18 of the normal value holding unit 7 rises to “1”, so that the selector 20 selects the output from the NOT circuit 19 and outputs it as the signal Dc1. As a result, even if an error occurs in the register c1 at the timing t3 and the value of the signal dc1 is inverted to “1”, the normal value “0” of the signal dc1 is output to the circuit unit 9 as the signal Dc1. Continue to be.

  At timing t4, the register 15 of the error detection circuit pc holds “1” output from the XOR circuit 14 in synchronization with the rising edge of the clock signal CLK. Therefore, the output of the register 15 of the error detection circuit pc rises to “1”. At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc and the output of the register 15 coincide with “1”, so that the signal xpc falls to “0”.

  At timing t4, the register 15 of the error detection circuit p1 holds “0” output from the XOR circuit 14 in synchronization with the rising edge of the clock signal CLK. Therefore, the output of the register 15 of the error detection circuit p1 falls to “0”. At this time, since the value of the output of the XOR circuit 14 of the error detection circuit p1 and the output of the register 15 coincide with “0”, the signal xp1 falls to “0”.

At timing t4, the signals xpc and xp1 fall to “0”, so that the output of the AND circuit 17 of the normal value holding unit 7 falls to “0”.
At timing t5, a write back (normal value writing) process by the processor 4 is performed. The signal dc1 falls to “0” by the operation of the register c1 shown in FIG.

  As the value of the signal dc1 changes, the output of the XOR circuit 14 of the error detection circuit pc falls to “0”. At this time, since the XOR circuit 14 of the error detection circuit pc and the output value of the register 15 do not match, the signal xpc rises to “1”. As the value of the signal dc1 changes, the output of the XOR circuit 14 of the error detection circuit p1 falls to “1”. At this time, the value of the output of the XOR circuit 14 of the error detection circuit p1 does not match the value of the output of the register 15, so that the signal xp1 rises to “1”.

  At timing t5, the signals xpc and xp1 rise to “1”, whereby the output of the AND circuit 17 of the normal value holding unit 7 rises to “1”. In synchronization with the rise of the output of the AND circuit 17, the register 18 inverts “1” and holds “0”. Therefore, the output of the register 18 falls to “0”. Further, when the signal dc1 falls to “0”, the output of the NOT circuit 19 of the normal value holding unit 7 rises to “1”.

  Further, when the output of the register 18 of the normal value holding unit 7 falls to “0”, the selector 20 selects the signal dc1 and outputs it as the signal Dc1. As a result, at timing t5, “0” of the signal dc1 having a normal value by error correction is output as the signal Dc1.

  At timing t6, the register 15 of the error detection circuit pc holds “0” output from the XOR circuit 14 in synchronization with the rising edge of the clock signal CLK, so that the output of the register 15 of the error detection circuit pc is “0”. To fall. At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc coincides with the value of the output of the register 15, so that the signal xpc falls to “0”.

  At timing t6, the register 15 of the error detection circuit p1 holds “1” output from the XOR circuit 14 in synchronization with the rising edge of the clock signal CLK. Therefore, the output of the register 15 of the error detection circuit p1 is “ Get up to 1 ”. At this time, since the value of the output of the XOR circuit 14 of the error detection circuit p1 and the output of the register 15 coincide with “1”, the signal xp1 falls to “0”.

At timing t6, the signals xpc and xp1 fall to “0”, so that the output of the AND circuit 17 of the normal value holding unit 7 falls to “0”.
With the above operation, even if an error occurs in the register c1 and the value of the signal dc1 changes, the normal value can be continuously supplied to the circuit unit 9.

Hereinafter, an operation example when an error occurs in the register 15 of the error detection circuit pc will be described.
(Operation example 2 of error detection circuit and normal value holding circuit)
FIG. 9 is a timing chart showing an example of operations of the error detection circuit and the normal value holding circuit when an error occurs in the register of the error detection circuit.

FIG. 9 shows an example of the various signals shown in FIG. 8 when an error occurs in the register 15 of the error detection circuit pc.
In the initial state, it is assumed that “0” is held as a normal parity bit in the register 15 of the error detection circuit pc.

  In the example of FIG. 9, an error occurs in the register 15 of the error detection circuit pc at timing t7, and the output of the register 15 is inverted from “0” to “1”. At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc and the value of the output of the register 15 do not match, so that the signal xpc rises to “1”.

  At timing t7, even if the signal xpc rises to “1”, the signal xp1 maintains “0”, so that the output of the AND circuit 17 of the normal value holding unit 7 also maintains “0”. As a result, the output of the register 18 of the normal value holding unit 7 (selection signal of the selector 20) also maintains “0”, so that the signal instructing generation of the interrupt signal Int generated based on this selection signal is negated. No interrupt is generated.

  Further, since the output of the register 18 of the normal value holding unit 7 maintains “0”, the selector 20 continues to select the signal dc1 having the normal value, and thus the signal Dc1 also continues to maintain the signal dc1 having the normal value. .

  On the other hand, at the timing t8, the register 15 of the error detection circuit pc holds the output (normal parity bit) of the XOR circuit 14 in synchronization with the rising edge of the clock signal CLK. As a result, the output of the register 15 falls to “0”. At this time, since the output of the XOR circuit 14 of the error detection circuit pc and the output of the register 15 are “0” and coincide with each other, the signal xpc falls to “0”.

The operation of the semiconductor integrated circuit 1 when an error occurs will be summarized below.
FIG. 10 is a flowchart showing an example of the operation of the semiconductor integrated circuit when an error occurs.

  When an error occurs in a register included in the register group 5, the output to the circuit unit 9 is held at a normal value by the normal value holding unit 7 (step S1). For example, even if an error occurs in the register c1 and the value of the signal dc1 output from the register c1 is inverted, the selector 20 (FIG. 7) inverts the value of the signal dc1 in the NOT circuit 19 (FIG. 7). Since it outputs as Dc1, the output to the circuit part 9 is hold | maintained at a normal value.

On the other hand, when an error occurs, the interrupt signal Int to the processor 4 is asserted as described above (step S2).
Thereafter, the processor 4 identifies an error occurrence register and performs a normal value write-back (error correction) process to the register as shown in FIG. 5 (step S3).

When the register error is corrected by the above processing, the parity bit becomes a normal value (step S4).
Further, the normal value holding unit 7 selects a register value that has become a normal value and outputs the selected value to the circuit unit 9 (step S5).

Thereafter, the interrupt signal Int to the processor 4 is negated (step S6).
In the semiconductor integrated circuit 3 of the second embodiment as described above, the same effect as the semiconductor integrated circuit 1 of the first embodiment can be obtained.

  Further, in the semiconductor integrated circuit 3 of the second embodiment, the normal value holding unit 7 inverts the value of the signal output from the error occurrence register from 0 to 1 or 1 to 0 and outputs the inverted value to the circuit unit 9. Thus, the value supplied to the circuit unit 9 can be maintained at a normal value. As a result, it is possible to suppress a malfunction from occurring in the circuit unit 9 due to an error in the register group 5.

  Furthermore, in the semiconductor integrated circuit 3 according to the second embodiment, the plurality of registers included in the register group 5 have a function of inverting the held value when an error occurs under the control of the processor 4. As a result, it is not necessary to store a copy of the normal value in a memory or the like by mirroring or the like, so that it is possible to perform error correction of the register with a smaller circuit configuration.

(Third embodiment)
FIG. 11 is a diagram illustrating an example of a semiconductor integrated circuit according to the third embodiment. The same elements as those shown in FIGS. 3 and 4 are denoted by the same reference numerals, and the description thereof is partially omitted.

  The semiconductor integrated circuit 3 a according to the third embodiment has a normal value writing unit 7 a that inverts the stored value of the error occurrence register instead of the processor 4. The normal value writing unit 7a also has a function of the normal value holding unit 7 of the semiconductor integrated circuit 3 according to the second embodiment. In FIG. 11, the normal value writing unit 7a is a circuit unit that inverts the stored value of the register c1 when an error occurs in the register c1, and the stored value (normal value) before the error of the register c1. 9 shows the portion to be output. Although the illustration regarding the other registers is omitted, the circuit is similar.

The normal value writing unit 7a includes an AND circuit 21, a register 22, a NOT circuit 23, an AND circuit 24, a NOT circuit 25, and a selector 26.
The AND circuit 21 performs an AND operation on the signal xpc output from the error detection circuit pc and the signal xp1 output from the error detection circuit pc, and outputs the operation result to the register 22 and the AND circuit 24.

  The register 22 holds the operation result output from the AND circuit 21 in synchronization with the rising (or falling) of the input clock signal CLK, and outputs the held value to the NOT circuit 23.

The NOT circuit 23 inverts the value output from the register 22 and outputs the result to the AND circuit 24.
The AND circuit 24 performs an AND operation on the operation result output from the AND circuit 21 and the value output from the NOT circuit 23, and the operation result is selected as a selection signal for the selector 26 and the selector 12 included in the register c1. Output as. The selection signal becomes “1” when an error occurs in the register c1.

The NOT circuit 19 inverts the value of the signal dc1 output from the register c1 shown in FIG.
When the selection signal supplied from the register 18 is “0”, the selector 20 selects the signal dc1 output from the register c1 and outputs it as the signal Dc1. When the selection signal is “1”, the selector 20 selects the signal dc1 inverted by the NOT circuit 19 and outputs it as the signal Dc1.

The NOT circuit 25 inverts the value of the signal dc1 output from the register c1 and outputs it to the selector 26.
When the selection signal supplied from the AND circuit 24 is “0”, the selector 26 selects the signal dc1 output from the register c1 and outputs it as the signal Dc1. When the selection signal is “1”, the selector 26 selects the signal dc1 inverted by the NOT circuit 25 and outputs it as the signal Dc1.

Hereinafter, an operation example of the semiconductor integrated circuit 3a of the third embodiment will be described.
(Operation Example 1 of Semiconductor Integrated Circuit)
FIG. 12 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the third embodiment. FIG. 12 shows an example in the case where an error occurs in the register c1, and the clock signal CLK, the signal dc1 output from the register c1, the signals of the error detection circuits pc and p1, and the normal value writing unit 7a. The state of an example of the signal of each part of is shown.

Since the error detection circuit p1 and the error detection circuit pc shown in FIG. 6 are similar circuits, the same reference numerals are given to the corresponding elements in FIG. 12 for convenience.
Also, the parity bit that is the output of the register 15 of the error detection circuit pc and the initial value of the output of the XOR circuit 14 are “0”, the parity bit that is the output of the register 15 of the error detection circuit p1 and the initial value of the output of the XOR circuit 14 The value is assumed to be “1”.

  In the example of FIG. 12, at timing t9, an error occurs in the register c1, and the signal dc1 output from the register c1 is inverted from “0” to “1”. As the value of the signal dc1 changes, the output of the XOR circuit 14 of the error detection circuit pc rises to “1”. At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc and the value of the output of the register 15 do not match, so that the signal xpc rises to “1”. As the value of the signal dc1 changes, the output of the XOR circuit 14 of the error detection circuit p1 falls to “0”. As a result, the value of the output of the XOR circuit 14 of the error detection circuit p1 does not match the value of the output of the register 15, so that the signal xp1 rises to “1”.

  At timing t9, the signals xpc and xp1 rise to “1”, whereby the output of the AND circuit 21 of the normal value writing unit 7a rises to “1”. At this time, the output of the AND circuit 24 rises to “1”. Further, when the signal dc1 rises to “1”, the output of the NOT circuit 25 of the normal value writing unit 7a falls to “0”.

  At timing t9, when the output (selection signal) of the AND circuit 24 of the normal value writing unit 7a rises to “1”, the selector 26 selects the output from the NOT circuit 25 and outputs it as the signal Dc1. As a result, even if an error occurs in the register c1 at the timing t9 and the value of the signal dc1 is inverted to “1”, the normal value writing unit 7a continues to output “0” that is a normal value as the signal Dc1. .

  At timing t9, the output of the AND circuit 24 of the normal value writing unit 7a rises to “1”. Therefore, the selector 12 of the register c1 selects the signal dc1 that has been inverted to “0” by the NOT circuit 11, and the flip-flop Output to

  The signal dc1 falls to “0” in synchronization with the first rising timing (timing t10) of the clock signal CLK after the signal dc1 is inverted to “1”. This is because the flip-flop 10 holds the signal dc1 inverted to “0” by the NOT circuit 11 output from the selector 12 in synchronization with the rising edge of the clock signal CLK. As a result, the error occurring in the register c1 is corrected.

  At timing t10, the output of the XOR circuit 14 of the error detection circuit pc falls to “0” in accordance with the change in the value of the signal dc1. Further, since the register 15 of the error detection circuit pc holds the output of the XOR circuit 14 that has risen to “1” at the timing t9 at the timing t10, the output of the register 15 of the error detection circuit pc rises to “1”. . At timing t10, the value of the output of the XOR circuit 14 of the error detection circuit pc and the output of the register 15 do not match, so the signal xpc maintains “1”.

  Further, with the change of the value of the signal dc1 at the timing t10, the output of the XOR circuit 14 of the error detection circuit p1 rises to “1”. Further, since the register 15 of the error detection circuit p1 holds the output of the XOR circuit 14 that has fallen to “0” at the timing t9, the output of the register 15 of the error detection circuit p1 falls to “0”. Further, at timing t10, the value of the output of the XOR circuit 14 of the error detection circuit p1 and the output of the register 15 do not match, so the signal xp1 maintains “1”.

  As described above, since the signals xpc and xp1 maintain “1”, the output of the AND circuit 21 of the normal value writing unit 7a maintains “1”. At this time, the AND circuit 24 performs an AND operation on the output of the AND circuit 21 and the output of the NOT circuit 23. The output of the NOT circuit 23 becomes a value (“0”) obtained by inverting the value held in the register 22 at the timing t10. As a result, the output of the AND circuit 24 falls to “0”.

Further, when the signal dc1 falls to “0”, the output of the NOT circuit 25 of the normal value writing unit 7a rises to “1”.
At this time, since the output of the AND circuit 24 which is a selection signal supplied to the selector 26 is “0”, the selector 26 selects the signal dc1 and outputs it as the signal Dc1. As a result, the signal dc1 having a normal value by error correction is output as the signal Dc1.

  In synchronization with the next rising timing (timing t11) of the clock signal CLK, the register 15 of the error detection circuit pc holds the output of the XOR circuit 14, so that the output of the register 15 falls to "0". At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc coincides with the value of the output of the register 15, so that the signal xpc falls to “0”.

  On the other hand, the register 15 of the error detection circuit p1 holds the output of the XOR circuit 14 in synchronization with the rising edge of the clock signal CLK, so that the output of the register 15 rises to “1”. At this time, since the value of the output of the XOR circuit 14 of the error detection circuit p1 and the output of the register 15 coincide with “1”, the signal xp1 falls to “0”.

As described above, when the signals xpc and xp1 fall to “0”, the output of the AND circuit 21 of the normal value writing unit 7a falls to “0”.
With the above operation, even if an error occurs in the register c1 and the value of the signal dc1 changes, the normal value can be continuously supplied to the circuit unit 9. Further, the normal value writing unit 7a can correct an error occurring in the register c1 without asserting an interrupt to the processor 4.

Hereinafter, an operation example when an error occurs in the register 15 of the error detection circuit pc will be described.
(Operation example 2 of semiconductor integrated circuit)
FIG. 13 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the third embodiment. FIG. 13 shows an example of the various signals shown in FIG. 12 when an error occurs in the register 15 of the error detection circuit pc.

In the initial state, it is assumed that “0” is held as a normal parity bit in the register 15 of the error detection circuit pc.
In the example of FIG. 13, at timing t12, an error occurs in the register 15 of the error detection circuit pc, and the output of the register 15 of the error detection circuit pc is inverted from “0” to “1”. At this time, the value of the output of the XOR circuit 14 of the error detection circuit pc and the value of the output of the register 15 do not match, so that the signal xpc rises to “1”.

  However, even if the signal xpc rises to “1”, the signal xp1 maintains “0”, so the output of the AND circuit 21 of the normal value writing unit 7a also maintains “0”. As a result, the output of the AND circuit 24 of the normal value writing unit 7a also maintains “0”, so that the selector 12 of the register c1 also maintains the selection of the signal dc1 output from the flip-flop 10. Further, when the output of the AND circuit 24 of the normal value writing unit 7a is maintained at “0”, the selector 26 continues to output the signal dc1 as the signal Dc1.

  In synchronization with the first rise timing (timing t13) of the clock signal CLK after the occurrence of the error, the register 15 of the error detection circuit pc holds the normal parity bit value that is the output of the XOR circuit 14. As a result, the output of the register 15 of the error detection circuit pc falls to “0” and is written back to a normal value. At this time, since the value of the output of the XOR circuit 14 of the error detection circuit pc and the value of the output of the register 15 are “0” and coincide with each other, the signal xpc falls to “0”.

Other operations are the same as those of the semiconductor integrated circuit 3 of the second embodiment, and the same effects as those of the semiconductor integrated circuit 3 of the second embodiment are obtained.
As described above, one aspect of the semiconductor integrated circuit of the present invention has been described based on the embodiment, but these are only examples, and the present invention is not limited to the above description.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Normal value writing part a0-a2, b0-b2, c0-c2 register p0-p2, pa-pc Error detection circuit

Claims (5)

A row address and a column address are assigned, and a plurality of registers each storing a 1-bit value of 0 or 1,
A first error detection circuit provided for each row address that outputs a first error detection signal when any value of the first register group at the same row address among the plurality of registers changes. When,
A second error detection circuit provided for each column address that outputs a second error detection signal when any value of the second register group at the same column address among the plurality of registers changes. When,
Based on the first error detection signal and the second error detection signal, the first register in which an error has occurred is specified, and the first stored value of the first register is set to 1 to 0 or 0 to 1 A normal value writing part to be reversed,
A semiconductor integrated circuit comprising:   Based on the first error detection signal and the second error detection signal, the value output from the first register in which an error has occurred is inverted from 1 to 0 or from 0 to 1, and the error before the error occurs The semiconductor integrated circuit according to claim 1, further comprising a normal value holding unit that holds an output state of the second stored value of the first register.   3. Each of the plurality of registers has a circuit that inverts a value held by itself based on a selection signal supplied from the normal value writing unit. A semiconductor integrated circuit according to 1.   In the first error detection circuit or the second error detection circuit, the first register group or the second register group holds a parity bit in a normal state, and the parity bit is set to the first by an error. When the value of the first register group changes to the second value, the parity bit is set to the first value generated based on the value of the first register group or the second register group in synchronization with the clock signal. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is updated.   The normal value writing unit inverts the value output from the first register in which an error has occurred from 1 to 0 or from 0 to 1 based on the first error detection signal and the second error detection signal 5. The semiconductor integrated circuit according to claim 3, wherein an output state of a value stored in the first register before occurrence of an error is held.

Images