JPH02150000A - Semiconductor storage device with error self correction function - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device with an error self correction function which can reduce the number of cells to be required by providing parity check cells which omit a part of plural memory cells and stores check information of plural memory cells before the omission. CONSTITUTION:The parity check cells 11 and 12 which omit a part of plural memory cells 10 and which store check information of the memory cells are provided. Furthermore, operation means such as EOR gates 20-37 which obtain information on plural memory cells before omission and a correction means consisting of an EOR gate 38 detecting the error of information on plural memory cells before omission and correcting them, AND gates 80-114 OR gates 120-123 and input output control circuits 40-65 are provided. Consequently, the operation means have functions outputting information on omitted memory cells and the correction means corrects the error of all information including the output. Thus, the semiconductor storage device with the error self correction function which reduces the memory cells can be obtained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides an error self-correction function that automatically detects and corrects fixed defective bits and non-fixed bit errors caused by the incidence of alpha rays, etc. The present invention relates to a semiconductor memory device with an attached semiconductor memory device.

(Prior art) Conventionally, as a technology in this field,
The one described in Publication No. 5198 etc. was found. The configuration will be explained below using figures.

FIGS. 2(a) and 2(b) are diagrams explaining the principle of a conventional semiconductor memory device with an error self-correction function.

This semiconductor memory device with an error self-correction function makes the horizontal/vertical parity check method one-dimensional and applies it to each memory cell connected to one word line, thereby eliminating bit errors that occur within the semiconductor memory device. is self-correcting.

In Fig. 2, if 16 data bits are considered, the 16 data bits 1 are arranged on a 4 x 4 matrix, and the horizontal parity bit 2 is 4 bits, and the vertical parity bit 2 is 4 bits for inspection. direction parity bit 3 to 4
Provide a bit. Note that the even number parity check method is used for the parity check.

Here, 16 data bits 1.4 horizontal parity bits 2 and 4 vertical parity bits 3 are shown in FIG.
By moving as shown by the dashed arrow in a), the two-dimensional matrix can be converted into a one-dimensional matrix as shown in FIG. 2(b).

Therefore, 24 in the one-dimensional matrix in Figure 2(b)
If an error occurs in any one of the upper 16 bits, the error bit position can be detected by comparing the parity bits of the lower 8 bits for each group indicated by the solid arrows in the figure. Therefore, even if a fixed defect or a non-fixed defect occurs in any one of the upper 16 bits, the defective bit position is detected by an exclusive OR gate (hereinafter referred to as an EOR gate), and based on the detection result. Error correction of defective bits can be easily performed.

(Problems to be Solved by the Invention) However, in the device having the above configuration, the number of test bits added to data bits for data storage increases. For example, in the example shown in Figure 2, 8 bits of test bits 2 and 3 are required for 16 data bits 1, so in order to achieve the same storage capacity, the memory cells must be 1.5 times, leading to a corresponding increase in chip size (area), and it was difficult to reduce this increase.

The present invention provides a semiconductor memory device with an error self-correction function that solves the problem of the increase in chip size, which is a problem of the prior art.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a plurality of memory cells for storing information, and a horizontal pano cell for detecting and correcting errors in information in the memory cells. , an error self-correction U equipped with a plurality of test cells such as vertical parity cells and parity check cells, (in a semiconductor memory device with function, some of the plurality of memory cells are omitted, and the plurality of memory cells before the omission are A parity check cell is provided to store test information of the memory cell.Roughly, an EOR gate is provided to calculate the output of the other memory cell after the omission and the output of the test cell to obtain the information of the omitted memory cell. an EOR gate, an AND gate, an OR gate, and an input/output control circuit that detects and corrects errors in the information of the plurality of memory cells before omission based on the inspection information of the inspection cells and parity check cells; A correction means consisting of, etc. is provided.

(Function) According to the present invention, since a semiconductor memory device with an error self-correction function is configured as described above, omitting some of the plurality of memory cells serves to reduce the increase in chip area. , and the parity check cell serves to output information necessary to determine the location of the bit in which an error has occurred. The arithmetic means has a function of outputting information of the omitted memory cells, and errors in all information including that output are corrected by the correction means. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a block diagram of a semiconductor memory device with an error self-correction function showing an embodiment of the present invention.

This semiconductor memory device with an error self-correction function shows a configuration of 16 data bits as an example, including a memory cell section 10, a horizontal parity cell section 11, a vertical parity cell section 12, and a parity check cell section 13.14. It is equipped with

The memory cell unit 10 has 16 data bits arranged on a 4×4 matrix, and has a code aHj (however, i
, j=o ~3) indicate memory cells corresponding to 16 data bits. Of the 16 data bits,
6 memory cells a. 1゜a02= a03= a12
The memory cell portion having = a13 = a23 has the code 1.
0A is attached. In addition, four memory cells aoo, a11 . a22. The memory cell portion 10B having a33 is omitted and is not formed in the semiconductor memory device.

The horizontal parity cell section 11 has a horizontal parity bit of the memory cell section 10, that is, a horizontal parity cell (inspection cell) pxj (where j=O to 3) that stores each horizontal parity information. There is. Vertical parity cell section 1
2 is a vertical parity bit of the memory cell section 10;
That is, it has vertical parity cells (inspection cells) p (where i=O to 3) that store parity information in each vertical direction. The parity check cell section 13 has a parity check cell (check cell) px that stores parity information of four parity bits in the horizontal direction or four parity bits in the vertical direction, and further includes a parity check cell (cell for inspection) px. teeth,
Parity information of the memory cell unit 'IOA (i.e., information necessary to determine the position of the bit where an error has occurred)
It has a parity check cell p7 that stores .

Note that since the memory cell section 10B is not actually provided, when outputting information on the memory cell section 10B,
The memory cells aoo, a11. It is configured to output the result of an operation between the parity bits of the horizontal group or vertical group to which a22 and a33 belong and other bits belonging to the same group. For example, memory cell a. When outputting information of 0, the output of horizontal parity cell pxo (or vertical parity cell p, 0) and other memory cells a1o, a2
o and the output of a3o (or a.1.ao2.ao3) to calculate the memory cell a. Find the storage information of 0 and output that information. Therefore, the number of memory cells required for 16 data bits is 12 in the memory cell section 10.
It is sufficient to have a total of 22 pieces, including this one and the other 10 pieces.

In the above configuration, (1) an error detection method in the memory cell section 10, and (2) an error detection method in the horizontal parity cell section 11, vertical parity cell section 12, and parity check cell section 13, 14 will be explained.

(1) Error detection method for memory cell section 10 First, one bit (in actual case,
Consider the case where an error occurs in 1 bit out of 12 bits (excluding 4 bits) in the memory cell section 10B.

If an error occurs in the information of memory cell a13, the information of memory cell a11 will be changed to memory cells a1o, a1.
2. Since it is determined by calculating the outputs of a13 and the vertical parity cell I)yl, the information of the memory cell a11 will also be incorrect. In this state, 16 data hits (a
00” a 33 > each horizontal direction (ao.

〜a30・aO1〜a31・aO2〜a32・aO3〜
When performing the parity check of a33) and comparing each result with the information written in the horizontal parity cells pxo to pX3, it is found that the error occurred in the memory cell a13.
The result of the parity check of the horizontal group to which px3 belongs does not match the information in the horizontal parity cell px3. Similarly, the result of the parity check for the horizontal group containing the bit (aii) that has resulted in an error in the calculation does not match the information in the horizontal parity cell Px1.

However, even if an error occurs in memory cell a31 instead of memory cell a13, the same result as above can be obtained, so a parity check is performed on the six data bits of memory cell section 10A at the same time, and the result and parity check are By comparing the information with the information of the cell 14, it can be determined whether the error has occurred in the memory cell a13 or a31.

(2) Horizontal parity cell section 11, vertical parity cell section 1
2 and error detection method in parity check cell section 13.14 If an error occurs in vertical parity cell p, 1, the vertical parity cell py1 and memory cells a1o, a1
2. The data bit (al
The information in l) becomes incorrect information. Here, when performing a horizontal group parity check, only the horizontal parity cell px1 becomes inconsistent, and the other horizontal parity cells pxO9pX2''
x3 matches. This shows that the error occurs in the parity bit, but the horizontal parity cell p
Even if an error occurs in x1 itself, the same result will be obtained.

Therefore, at the same time, four horizontal parity cells pxO""
px3, and four vertical parity cells D v□”D
By performing a parity check on each of y3 and comparing it with the information stored in the parity check cell px9, it is possible to determine whether an error has occurred in the vertical parity cell py1 or whether the error has occurred in the horizontal parity cell p
It can be determined whether it is occurring in xl.

An error in the parity check cell px can be determined by comparing the parity check results of the four horizontal parity cells pxo to pX3 and the four vertical parity cells pyO to py3, which agree with each other.

The error in parity check cell p2 is 4 horizontal parity cells pxO" px3 and 4 vertical parity cells l)
When the results of the parity check of each of the yo"" p y3 and the parity check cell pxvo information match, the determination can be made by comparing the results of the parity check of the six data bits of the memory cell section 10A.

As described above, for 16 data bits, 4 bits of memory cell a on the diagonal line. . .

all, a22. a33 is omitted, and four horizontal parity cells p to p and four vertical parity cells Dy□xo
x3 to p, 3, and a parity check cell px bowl that stores parity check information of four horizontal parity cells pxo""x3 or four vertical parity cells lay□ to py3,
In a writing/practicing device consisting of a total of 22 cells including a parity check cell 14 that stores parity information of the 6-bit memory cell section 10A below the omitted memory cell section 10B,
No matter which one of the 22 cells has incorrect information,
The erroneous bit can be detected accurately. In addition, conventionally, an nxn bit memory required an increase of 2n bits due to the parity bit, but in the storage device shown in Figure 1, an increase of (n+2> bits is sufficient), which reduces the chip area. Can be reduced.

FIG. 3 is a circuit diagram of a semiconductor memory/old device with an error self-correction function showing a configuration example of FIG. 1, and elements common to those in FIG. 1 are given the same reference numerals.

This semiconductor memory device is a semiconductor memory device with an error self-correction function when the data bit width is 1 bit, and a plurality of word lines 15 and bit lines 16 have a memory cell section omitting the memory cell section 10B. 10. A horizontal parity cell section 11, a vertical parity cell section 12, and a parity check cell section 13 and 14 are connected.

EOR gates 20 to 37 are connected to the bit line 16. EOR gates 20 to 23 are connected to omitted memory cells aoo, a11 . a22. Each three memory cells aO1-a02 belonging to the same vertical group as a33 = "03-a1
0= a12= 813- a20 = a21= a2
3-a30=a31-a32 information and the vertical parity cell pyO-p v3 information of each group are input, and the omitted memory cells aoo, a11. a22゜a3
It has a function as a calculation means to obtain the information of 3. F
OR gates 24 to 27 are omitted in memory cell a. 0”
” Memory cells aOO to a30 in each horizontal group including a33
- This is a circuit that performs a parity check in the horizontal direction of data bits read from aO1 to a31, aO2 to a32, and aO3 to a33. The EOR gates 28 to 31 receive the results of the horizontal parity check of the read data bits (
That is, it has a function of comparing the outputs of the FOR gates 24 to 27) with the horizontal parity information stored in the horizontal parity cells pxO to px3. EOR gate 3
2 performs a parity check on the horizontal parity bit read from the horizontal parity cell pxo'' px3, and
The OR gate 33 is a vertical parity cell p. It has a function of performing a parity check on the vertical parity bits read from ~p, 3. EOR gate 34.35 is E
Each output of OR gate 32, 33 and parity check cell l)
Comparison is made with the information written in xV(7), and the EOR gate 36 selects the memory cell ao1.
ao2. ao3, a12. A 6-bit parity check of a13 and a23 is performed, and the EOR gate 37 performs an EO
It has a function of comparing the output of the R gate 36 and the information stored in the parity check cell p7.

All data hits of memory cell section 10 (a00 to a33)
is connected to the selection circuit 70 via each input/output control circuit 40 to 55, and is roughly connected to the horizontal parity cell pxO"" px3
are connected to the selection circuit 71 via the input/output control circuits 56-59, and the vertical parity cells lay□-py3 are connected to the selection circuit 72 via the input/output control circuits 60-63, respectively. Parity check cells pxy, p2 are connected to each input/output control circuit 64, 65. Selection circuits 70, 71
．． 72 is a circuit for extracting necessary information to the outside by inputting an address. Among them, the selection circuit 70 is connected to an input terminal 74 via a gate 73 and directly to an output terminal 75. In addition, the input terminal 74
and the output terminal 75 are connected to the input side of the FOR gate 38, and are connected to the output side of the EOR gate 38 or the update circuit 76.
．． 77 to the selection circuits 71, 72 and to the update circuit 7B.

79 to input/output control circuits 64 and 65. Here, the EOR gate 38 is PI? It has a function of comparing the corrected data bit information with data newly written to the same memory cell. Update circuit 76
．． 77.78.79 is E when writing new data.
The horizontal parity cell p is determined by the output result of the OR gate 38.
It has a function of updating the previous arrangement data of XO-pX3, vertical parity cells OyO to py3, and parity check cells pxy and p2.

The input/output control circuits 40 to 65 control the output angle of data, and have the function of correcting any error in the read data using the control signal υ11 "H".

This control 1 signal "to 1" is an AND gate (hereinafter referred to as AN
They are generated by D gates >80 to 114 and OR gates (hereinafter referred to as OR gates) 120 to 123.

AND gates 80 to 85 input the outputs of EOR gates 28 to 31, and select the horizontal parity check result or 2.
If the bits do not match, an output is obtained by the combination, and the AND gates 86 to 89 output the EOR gate 28.
It has a function of obtaining an output when the horizontal parity check results do not match by just one bit based on the outputs of the bits 31 to 31. AND gates 90 to 101 are AN
Memory cells ao1 to aO3 and a that require correction according to the outputs of the D gates 80 to 85 and the output results of the AND gate 37
lo・a12・a13・a20・a21・first total a3F”
A AND gates 102 to 105, which are circuits that provide control signals for correcting the output information of a32 to input/output control circuits 41 to 44, 46 to 49, and 51 to 54, connect the outputs of AND gates 86 to 89 and the AND gates. A1\D gates 106 to 109 are circuits that provide input/output control circuits 56 to 59 with control signals for correcting the outputs of horizontal parity cells pxO to pX3 that require correction based on the output of A1\D gates 106 to 109.
The input/output control circuit 60 receives a control signal 1311 for correcting the outputs of the vertical parity cells 0-p, 3 that require correction using the outputs of the gates 86-89 and the output of the AND gate 112.
63.

The AND gate 110 inputs the outputs of the EOR gates 34 and 35, and determines that neither the parity check of the parity bit in the horizontal direction nor the parity check of the parity bit in the vertical direction that is read out matches the information in the parity check cell px. In this case, the input/output control circuit 64 sends a control signal for correcting the output information of the parity check cell px.
This is a circuit that gives AND gate 111 obtains an output when only the parity check of horizontal parity cells pxo to px3 does not match the parity check cell pxy (D information, and AND gate 112 outputs vertical parity cell 1) y
Q"'-p Get output if only the parity check of y3 does not match the information of the parity check hill pxy,
AND game 1-113 performs a parity check of horizontal parity cells p8 to p3 and vertical parity cell 1) v(
)""-D This circuit outputs when any of the parity checks of y3 matches the information of the parity check cell pxy. AND gate 114 is AND gate 1
13 and the output of the FOR gate 37, a control signal is given to the input/output control circuit 65 for correcting the output information of the parity check cell p2 when it is necessary to correct the contents of the parity check cell p7. It is a circuit.

OR gates 120-123 are AND gates 90-92
．． The omitted memory cell a is obtained by inputting the outputs of 93-95.96-98.99-101 and using FOR gates 20-23. When it is necessary to correct the output information of 0 to a33, the control signal is sent to the input/output control circuits 40, 45, 50 .
55.

FIG. 4 is a circuit diagram showing a one-channel configuration of the input/output control circuits 40 to 65 in FIG. 3.

The input/output control circuits 40 to 65 have a terminal 130 connected to the output side of the memory cell, etc., an input/output terminal 131, and a control signal ji for correcting output information of the memory cell, etc.
A control terminal 132 for inputting H11 is provided, and an EOR gate 133, a read gate 134, inverters 135 and 136, and write gates 137 and 138 are connected between these terminals 130 to 132. When reading data, the gate 134 listens, and if the output information of the memory cell etc. needs to be corrected, the EOR gate 133
If the correction is made and no correction is necessary, the inverter 13
5. Temporarily latched at 136. When rewriting a memory cell or the like, the gate 138 listens, and correct information is written to the cell in which the error occurred through the terminal 130. Furthermore, when new data is written from the outside through the input/output terminal 131, the gate 137 is opened and the new data is written through the terminal 130.

FIG. 5 is a circuit diagram showing an example of the configuration of update circuits 76 to 79 in FIG. 3.

The update circuits 76 to 79 are connected to the FOR gate 38 in FIG.
Terminal 140 connected to the output side of , and selection circuit 71.7
2, etc., and has a terminal 141 connected to the terminal 1
EOR gate 142 and gate 143 between 40 and 141
is connected.

When occupying new data, the gate 143 opens and the first
According to the output result of the FOR gate 38 in the figure, the FOR142
and updates previous data such as horizontal parity cells through gate 143.

The semiconductor story in Figure 1, which is constructed as described above, and the hypothetical stomach (
A> Write operation and (B) read operation will be explained. It is assumed that the parity check takes, for example, an even parity check method.

First, all memory cells a. 0-a33, horizontal parity cell pxo"" px3, vertical parity cell pyo-p
and parity check cells pxy, p2 to logic “011”.
Clear to.

(A) Operation when writing When data is written or output, input information is written to a desired address, and at the same time, an exclusive OR is performed between the input information and the inspected information before that address, and the input information is Associated horizontal parity cells pxO to px3, vertical parity cells D, O to py3, and parity check cells 13.14
Update information.

That is, memory cell a is omitted during writing. . .

all, a22. FOR gates 20-2 for information on a33
3, and the EOR gates 24 to 27 select the horizontal memory cells a00 to a3o, ao1 to a31, ao2 to a32.
．． A parity check is performed on ao3 to a33, and the results are compared with the written/l information of horizontal parity cells pxo to pX3 using FOR gates 28 to 31.

The comparison result of EOR gates 28 to 31 is AND gate 8
It is determined from 0 to 85 and from 86 to 89.

When the results of the horizontal parity check do not match by two bits, the outputs of AND gates 80-85 become valid. At this time, memory cell a01 of memory cell section 10A
~ao3. a12. a13. The parity check of a23 is performed by the EOR gate 36, and the result is compared with the record information of the parity check cell p7 by the FOR gate 37, so the comparison result of the EOR gate 37 and the
The output of OR gates 80-85, AND gates 90-
101. Among the outputs of the AND gates 90 to 101, the output of the AND gate corresponding to the location where the information of the input/output memory cell is incorrect becomes "Hll", which is corrected to the correct value by the input/output control circuits 40 to 55, and then the selection circuit The write input information is output from the output terminal 75 through the input terminal 74, the gate 73, the selection circuit 70,
and input/output control circuits 41-44.46-49.51-5
The data is written to the corresponding memory cell using route 4.

At the same time, the exclusive OR of the write input information and the output information of the output terminal 75 is taken at 38 to the FOR game 1. This E
The output information of the OR gate 38 and the outputs of the selection circuits 71 and 72 and the input/output control circuits 64 and 65 are respectively exclusive ORed by the update circuits 77 to 79, and the results are sent to the selection circuits 71 and 72. and the horizontal parity cell section 11 and the vertical parity cell section 12 in the paths of the input/output control circuits 56 to 63.
The information of the horizontal validation cells pxo to px3 and the vertical parity cells p, op to p, 3 to which the occupied address relates is updated, and the information of the parity check cell pxo to px3 is updated via the input/output control circuits 64 and 65. .

The information on p7 will be updated.

On the other hand, when the comparison results of EOR gates 28 to 31 are judged by AND gates 80 to 85 and 86 to 89, if the horizontal parity check results do not match by one hit, the outputs of AND gates 86 to 89 are determined to be valid. Become. At this time, F
The output of the EOR gate 32.33 and the information stored in the parity check cell pxy are
Compare with OR gates 34 and 35, and if only horizontal parity check or pxy does not match, AND gate 11
1 output is “H”, and when only the vertical parity check is inconsistent with pxy, the output of the AND gate 112 is “H”.
The outputs of these AND gates 1-111 and 112 and the outputs of AND gates 86-89 are given to AND gates 102-105 and 106-109.

Among the outputs of AND gates 102 to 109, the output of the AND gate corresponding to the error part of the parity time signal is "T1".
This is corrected to the correct value by the input/output 1''1] control circuits 56 to 63, and returned to the horizontal parity cell section 11 and vertical parity cell section 12.

During comparison by the FOR gates 34 and 35, if both the horizontal parity check and the vertical parity check do not match pxy, the output of the AND gate 110 becomes 'l-1' and the content of the parity check cell pxy It is corrected to the correct value by the input/output control circuit 64 and returned to the parity check cell unit 13. Both the horizontal parity check and the vertical parity check are performed p, .
=-, the output of the AND gate 113 becomes “H”
', which is compared with the output of the EOR gate 37 by the AND gate 114, and if the content of the parity check cell p2 is incorrect, it is corrected by the input/output control circuit 65 and returned to the parity check cell unit 14.

(B) Operation during reading When data is continuously output, by activating one word line 15 connected to the read memory cell, all memory cells a01 to a01 connected to that word line 15 are activated. a
03・alo・a12・a13・a20・a2
1. a23. a3o to a32, horizontal parity cells px.

~px3, vertical parity cells p, o~py3, and parity check cells pxy, information of p7 is read.

By EOR gates 20 to 23, the omitted memory cell a
oo, a11. a22. After asking for information on a33, FO
A horizontal parity check is performed by R gates 24 to 27, and the results and horizontal parity cells pxo to px3 are
The EOR gates 28 to 31 compare the recorded practice information.

If there is an error in the read information by comparing the EOR gates 28 to 31, AND gates 80 to 85, 90 to 101,
The information is corrected by the input/output control circuits 40 to 55 via the OR gates 120 to 123, and the corrected information is re-recorded in the memory cell section 10 and outputted from the output terminal 75 through the selection circuit 70.

Roughly speaking, as in writing, the horizontal parity cell section 11,
Vertical parity cell section 12 and parity check cell section 13.
14 is checked, and if there is an error, the input/output control circuit 5
6-59.60-63°64.65 and then returned to the horizontal parity cell section 11, vertical parity cell section 12, and parity check cell section 13.14.

By the above-described operations, it is possible to inspect and correct write/continue memory cell information, and at the same time, inspect and correct horizontal and vertical parity information and parity check information that stores the inspection information. Moreover, the parity check cell pxy,
l:) While adding z, some of the memory cells aoo,
a11. a22. By omitting a33, the number of cells required for conventional error self-correction can be reduced compared to a semiconductor memory device with capability, so the increase in chip area can be reduced and the yield can be improved.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

■ In FIG. 1, the parity check cell p2 consists of the six memory cells a10 and above the omitted memory cell section 10B.
It may be configured to record the parity information of a20, a21, a30-a31, and a32.

(2) In FIG. 3, the arithmetic means for obtaining the information of the omitted memory cells is composed of EOR gates 20 to 23, but it may be composed of other circuits.

Correction means for detecting and correcting errors in omitted memory cell information include EOR gates 28-31°37, AND gates 80-85, 90-101, and OR gates 120-12.
3, input/output control circuits 40.45, 50.55, etc., but other circuits may be used.

(2) In FIG. 3, the explanation has been given using a multiple word x 1 bit configuration as an example, but FIG. 1 can also be applied to a multiple word x multi bit configuration.

(Effects of the Invention) As described in detail above, according to the present invention, compared to the C1 conventional recorder/recipient device, which has a configuration in which a part of the memory cell is omitted without adding a parity check cell. Therefore, it is possible to reduce the number of cells required in the process, thereby reducing the increase in chip area, and realizing a semiconductor storage device with high yield.

[Brief explanation of the drawing]

FIG. 1 is a conjunctive diagram of a half-and-half recorder device with an error self-correction function showing an embodiment of the present invention, and FIG. 2(a). (b) (Explanatory diagram of the principle of a conventional semiconductor memory device with an error self-correction function, Figure 3 is the circuit diagram of Figure 1, and Figure 4 is the circuit diagram of Figure 3.
The circuit diagram of the input/output cull control circuit in the figure is shown, and FIG. 5 is the circuit diagram of the update circuit in FIG. 3. 10.10A, 10B...Mericell part, ao
. ~a33...Memory building, 11...Horizontal parity cell section, p0~px3...Horizontal parity cell, 12...Vertical parity cell section, p
Wow. ~py3...Vertical parity cell, 13.1
4...Parity check hill section, pxy, p2...
...Parity check cell, 15...Word line, 16...Bit line, 20-38...
EOR gate, 40-65... Input/output control circuit, 70-72... Selection circuit, 76-79...
...Update circuit, 80-114...AND gate, 120-123...OR gate.

Claims (1)

[Scope of Claims] A semiconductor memory device with an error self-correction function comprising a plurality of memory cells for storing information and a plurality of test cells for detecting and correcting errors in the information in the memory cells, comprising: A part of the plurality of memory cells is omitted, and a parity test cell is provided that stores test information of the plurality of memory cells before the omission, and the output of the other memory cell after the omission and the test cell are provided. an arithmetic means for calculating information on the omitted memory cells by calculating the output, and detecting errors in the information on the plurality of memory cells before omitted based on the inspection information of the inspection cells and parity inspection cells, and correcting the errors. What is claimed is: 1. A semiconductor memory device with an error self-correction function, characterized in that it is provided with a correction means for performing error self-correction.