JP2016015413A - Semiconductor light emitting element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element and a manufacturing method of the same, which can achieve a high optical output even though an operating voltage is decreased more than ever before.SOLUTION: A semiconductor light emitting element manufacturing method according to the present embodiment comprises: a process (a) of preparing a substrate; a process (b) of forming an n-type first semiconductor layer composed of n-AlGaInN(0≤x1≤1, 0≤y1≤1) on the substrate; a process (c) of forming an active layer in an upper layer of the first semiconductor layer; a process (d) of forming a p-type second semiconductor layer composed of p-AlGaInN(0<x2≤1, 0≤y2<1) in the upper layer of the active layer at a temperature inside a furnace of equal to or higher than 800°C; a process (e) of forming a p-type third semiconductor layer composed of p-GaN in an upper layer of the second semiconductor layer at a temperature inside the furnace of equal to or higher than 800°C; and a process (f) of decreasing the temperature inside the furnace after the process (e).

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  As a light-emitting element using a nitride semiconductor, the structure of Patent Document 1 below is known. FIG. 6 is a cross-sectional view schematically showing the structure of the semiconductor light emitting device disclosed in the document.

  A conventional semiconductor light emitting device 100 shown in FIG. 6 includes a substrate 101, a buffer layer 102, an n-type contact layer 103, an n-type cladding layer 104, an active layer 105, a p-type cladding layer 106, a first p-type contact layer 107, A second p-type contact layer 108 is provided. In addition, the semiconductor light emitting device 100 includes an n-side electrode 109 on the upper surface of the n-type contact layer 103 and a p-side electrode 110 on the upper surface of the second p-type contact layer 108.

  According to Patent Document 1, the second p-type contact layer 108 in contact with the p-side electrode 110 is composed of a semiconductor layer having a high p-type impurity concentration and a low Al composition ratio, and the first p-type contact layer 107 is the first p-type contact layer 107. It is described that it is composed of a semiconductor layer having a low p-type impurity concentration and a high Al composition ratio as compared with the second p-type contact layer 108. According to the document, ohmic contact with the p-side electrode 110 is realized by forming the p-type contact layer (107, 108) with two types of layers having different p-type impurity concentration and Al composition ratio. However, it is described that the thickness of the contact layer can be secured to such an extent that the element characteristics can be maintained while preventing self-absorption.

Japanese Patent No. 3614070

  According to Patent Document 1, the conventional semiconductor light emitting device 100 shown in FIG. 6 is manufactured by the following procedure.

After the buffer layer 102 made of GaN is grown on the substrate 101 at 510 ° C., the n-type contact layer 103 made of n-type Al _0.04 Ga _0.96 N is grown at 1050 ° C. Next, an n-type cladding layer 104 made of n-type Al _0.18 Ga _0.82 N is grown on the n-type contact layer 103 at 1050 ° C., and then an active layer 105 made of undoped InGaN is grown at 700 ° C. Let Note that in this specification, the description of InGaN means In _a1 Ga _1-a1 N (0 <a1 <1), and does not indicate that the composition ratio of In and Ga is 1: 1. . The description of AlGaN has the same purpose.

Next, the p-type cladding layer 106 made of Al _0.2 Ga _0.8 N is grown at 1050 ° C. Next, a first p-type contact layer 107 made of Al _0.04 Ga _0.96 N doped with 1 × 10 ¹⁹ / cm ³ of Mg is grown to a thickness of 0.1 μm on the p-type cladding layer 106. After that, the second p-type contact layer 108 made of Al _0.01 Ga _0.99 N doped with 2 × 10 ²¹ / cm ^{3 of} Mg by adjusting the gas flow rate is grown to a thickness of 0.02 μm. .

  Thereafter, the wafer is annealed at 700 ° C. in the reaction container to reduce the resistance of the p-type semiconductor layer, and then the wafer is taken out from the reaction container. Then, a mask having a predetermined shape is formed on the surface of the second p-type contact layer 108 positioned at the uppermost layer, and the semiconductor layer is etched from the second p-type contact layer 108 side by an RIE (reactive ion etching) apparatus. Then, the surface of the n-type contact layer 103 is exposed as shown in FIG. Then, an n-side electrode 109 is formed on the exposed upper surface of the n-type contact layer 103, and a p-side electrode 110 is formed on the upper surface of the second p-type contact layer 108.

  Here, as described above, the p-type cladding layer 106, the first p-type contact layer 107, and the second p-type contact layer 108 are all epitaxially grown at a high temperature of 1000 ° C. or higher. It is formed. Thereafter, the temperature in the furnace is lowered. In the above method, after the temperature is lowered to about 700 ° C. and annealing is performed, the wafer is taken out of the furnace.

  However, according to the diligent research of the present inventors, it has been found that the semiconductor light emitting device manufactured by the above-described method has a high operating voltage.

  In view of the above-described problems, an object of the present invention is to realize a semiconductor light-emitting element capable of obtaining a high light output while lowering the operating voltage than the conventional one and a manufacturing method thereof.

  The present inventor considers the reason why the operating voltage of the semiconductor light emitting device described in Patent Document 1 is high as a result of diligent research as follows.

Of the semiconductor layers of the semiconductor light emitting device 100 described in Patent Document 1, the semiconductor layer located on the uppermost surface, that is, the semiconductor layer in contact with the p-side electrode 110 (second p-type contact layer 108) is Al _0.01. It is composed of Ga _0.99 N. This layer is a layer formed by epitaxial growth in a state where the temperature in the furnace is as high as 1050 ° C.

  By the way, AlGaN is a mixed crystal of GaN and AlN, and the formation temperature of AlN is higher than the formation temperature of GaN. That is, the second p-type contact layer 108 made of AlGaN is grown while supplying a source gas such as TMG (trimethylgallium), TMA (trimethylaluminum), or ammonia at a high temperature of 1050 ° C., and then the gas is supplied. Even if it stops, the furnace is exposed to extremely high temperatures for a while. At this time, GaN of AlGaN constituting the second p-type contact layer 108 is selectively evaporated, and the Al composition ratio of AlGaN increases.

That is, as a growth condition, even if the flow rate ratio of each source gas is set so that Al _0.01 Ga _0.99 N is formed, the extent that GaN does not evaporate after the gas supply is stopped. In particular, GaN evaporates from the upper surface of the second p-type contact layer 108 until the temperature in the furnace becomes low. For this reason, an Al-rich layer is formed on the upper surface of the second p-type contact layer 108.

Thus, when an Al-rich layer is present on the upper surface of the second p-type contact layer 108, the band gap of the layer is expanded and the carrier concentration is decreased. In addition, the Al-rich layer may be oxidized to form a high resistance layer such as Al ₂ O _{3 on the} surface. For these reasons, the contact resistance between the p-side electrode 110 and the second p-type contact layer 108 increases, and the operating voltage of the semiconductor light emitting device 100 increases.

Under such consideration, a method for manufacturing a semiconductor light emitting device according to the present invention includes:
Preparing a substrate (a),
A step (b) of forming an n-type first semiconductor layer made of n-Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1) on the substrate;
Forming an active layer on the first semiconductor layer (c);
An upper layer of the active _{layer, p-Al x2 Ga y2 In} 1-x2-y2 N p -type second semiconductor made of (0 <x2 ≦ 1,0 ≦ y2 <1) the temperature in the furnace as 800 ° C. or higher Forming a layer (d),
A step (e) of forming a p-type third semiconductor layer made of p-GaN at a temperature in the furnace of 800 ° C. or higher on the second semiconductor layer;
And it has the process (f) which lowers | hangs the furnace temperature after the said process (e), It is characterized by the above-mentioned.

By the above method, immediately before the temperature in the furnace is lowered state, i.e., immediately before the state of step _{(f), p-Al x2} Ga y2 In 1-x2-y2 N (0 <x2 ≦ 1, A p-type third semiconductor layer made of p-GaN is formed on the upper surface of the p-type second semiconductor layer made of 0 ≦ y2 <1). In other words, even if the gas supply is stopped when the temperature in the furnace is high, the second semiconductor layer composed of a mixed crystal containing Al is not located on the uppermost surface. Does not evaporate and the upper surface of the second semiconductor layer becomes Al-rich. In addition, since the third semiconductor layer located on the uppermost surface at the time when the supply of gas is stopped is composed of p-GaN, the GaN is removed from the third semiconductor layer during the process of lowering the temperature in the furnace. Even if evaporates, an Al-rich layer is not formed on the uppermost surface of the third semiconductor layer.

  Therefore, unlike the prior art, since an Al-rich layer is not formed on the upper surface of the p-type semiconductor layer that contacts the p-side electrode, the upper surface of the third semiconductor layer is formed after the step (f) of reducing the furnace temperature. Even if the p-side electrode is formed, the contact resistance between the p-side electrode and the third semiconductor layer does not increase. Therefore, a semiconductor light emitting element having a lower operating voltage than the conventional one is realized. This result will be described later with reference to the examples in the section “DETAILED DESCRIPTION”.

The third semiconductor layer may be a layer having a high doped p-type impurity concentration (for example, 1 × 10 ¹⁹ / cm ³ or more).

The second semiconductor layer may also be a layer having a high doped p-type impurity concentration (for example, 1 × 10 ¹⁹ / cm ³ or more). In this case, all of the third semiconductor layer may be evaporated in the process (f). At this time, the third semiconductor layer functions only as a protective layer for preventing evaporation of GaN from a mixed crystal containing Al constituting the second semiconductor layer. Then, after the step (f), a p-side electrode is formed on the upper surface of the second semiconductor layer. In this case, the semiconductor layer in contact with the p-side electrode _is a second semiconductor layer made of _{p-Al x2 Ga y2 In 1} -x2-y2 N. When the second semiconductor layer is an AlGaN layer, the p-side electrode is formed on the p-AlGaN layer, which is the same as the conventional structure described above with reference to FIG. However, as described above, since the second semiconductor layer has a third semiconductor layer as a protective layer formed on the upper surface thereof after the step (f), particularly in the initial stage where the furnace temperature is high, Unlike _{configurations, p-Al x2 Ga y2 in} 1-x2-y2 on the upper surface of the second semiconductor layer made of N is not formed Al rich layer. Therefore, a semiconductor light emitting device having a lower operating voltage than the conventional configuration is realized.

The step (d) _is may as forming with _{p-Al x2 Ga y2 In 1} -x2-y2 N temperature above that can be grown (0 <x2 ≦ 1,0 ≦ y2 <1) Absent. Similarly, the step (e) may be formed at a temperature higher than the temperature at which p-GaN can be grown.

  Moreover, the manufacturing method of the semiconductor light-emitting device of the present invention may further include a step (g) of forming an electrode on the third semiconductor layer after the step (f).

  Moreover, the said process (e) can also be made into the process performed by changing only the flow volume of the source gas supplied in the said furnace compared with the said process (d). That is, the growth temperature may be substantially the same in step (d) and step (e).

At this time, since the step (e) is a step for growing the semiconductor layer at a high temperature in the furnace following the step (d), the p-Al _x2 Ga _y2 In _1-x2-y2 formed by the step (d) is used. GaN does not evaporate from the upper surface of the second semiconductor layer made of N (0 <x2 ≦ 1, 0 ≦ y2 <1), and an Al-rich layer is not formed on the upper surface. A third semiconductor layer is formed.

  In addition, after the step (f) is performed, the film thickness of the third semiconductor layer may be 5 nm or less.

  In particular, when the semiconductor light emitting device is realized as a device that emits ultraviolet light having a peak wavelength of 400 nm or less, it is preferable to make the semiconductor layer made of GaN whose absorption edge is located on the longer wavelength side than AlN as thin as possible. As described above, since the third semiconductor layer is provided for the purpose of functioning as a protective layer for preventing the formation of an Al-rich layer on the upper surface of the second semiconductor layer, after the execution of the step (e) The upper surface of the second semiconductor layer may be covered under a state where the temperature in the furnace is still high.

  And after execution of a process (e), in the initial stage which starts a process (f), since the temperature in a furnace is high in the state where gas supply was stopped, the third semiconductor layer comprised of p-GaN Some evaporate. For this reason, the film thickness of the third semiconductor layer after the execution of the step (f) is made thinner than the film thickness formed in the step (e). In step (e), by setting the growth thickness of the third semiconductor layer so that the thickness of the third semiconductor layer made of p-GaN is 5 nm or less after the execution of step (f), the light output High ultraviolet light emitting element can be realized.

After the step (c), the temperature in the furnace is set to 800 ° C. or higher on the active layer, and p-Al _x3 Ga _y3 In _1-x3-y3 N (0 <x3 ≦ 1, 0 ≦ y3 < 1) having a step (h) of forming a p-type fourth semiconductor layer comprising:
The step (d) may be performed after the step (h) and is a step of forming the second semiconductor layer having a higher p-type impurity concentration than the fourth semiconductor layer.

  In this case, the fourth semiconductor layer can constitute a p-type cladding layer, and the second semiconductor layer can constitute a p-type contact layer. In addition, when the third semiconductor layer remains after the execution of the step (f), the second semiconductor layer and the third semiconductor layer can constitute a p-type contact layer.

The present invention includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer on a substrate, and a peak wavelength of 400 nm or less. A semiconductor light emitting device that emits ultraviolet light,
The p-type semiconductor layer includes a p-type second semiconductor layer made of p-Al _x2 Ga _y2 In _1-x2-y2 N (0 <x2 ≦ 1, 0 ≦ y2 <1), and a p-thickness of 5 nm or less. A p-type third semiconductor layer made of GaN,
The third semiconductor layer is an uppermost layer on the surface of the p-type semiconductor layer opposite to the active layer.

  Although the third semiconductor layer is composed of p-GaN, since the film thickness is 5 nm or less, the light absorbed in the third semiconductor layer even when realized as an ultraviolet light-emitting element having a peak wavelength of 400 nm or less. Can be very small.

  When it is intended to realize an ultraviolet light emitting device having a peak wavelength of 400 nm or less using a nitride semiconductor, it is preferable that GaN whose absorption edge is located on the longer wavelength side than AlN is not used as much as possible. It is generally considered that all the semiconductor layers are composed of nitride semiconductor layers including

  However, the semiconductor light emitting device according to the above configuration includes a third semiconductor layer made of p-GaN on the layer located on the uppermost surface of the p-type semiconductor layer. More specifically, it means that the layer formed at a position in contact with the p-side electrode can be a third semiconductor layer made of p-GaN.

  As described above, when a semiconductor layer formed at a position in contact with the p-side electrode, for example, a p-type contact layer is composed of a semiconductor layer containing Al such as AlGaN or AlInGaN, each semiconductor layer is formed in the furnace. Therefore, after the epitaxial growth process is completed and the supply of the source gas is stopped, GaN evaporates during the process of lowering the furnace temperature, and an Al-rich layer is formed on the upper surface. As a result, the contact resistance between the layer and the p-side electrode increases. According to the above configuration, since the uppermost surface of the p-type semiconductor layer is the third semiconductor layer made of p-GaN, an Al-rich layer is not formed on the upper surface of the layer, and the contact resistance with the p-side electrode Can be reduced in resistance. Thereby, the operating voltage can be lowered as compared with the conventional semiconductor light emitting device.

  The semiconductor light emitting device of the present invention may have an electrode on the third semiconductor layer. In more detail, it can be set as the structure which has an electrode on the surface on the opposite side to the said active layer among the surfaces of the said 3rd semiconductor layer.

The p-type semiconductor layer includes a p-type fourth semiconductor layer made of p-Al _x3 Ga _y3 In _1-x3-y3 N (0 <x3 ≦ 1, 0 ≦ y3 <1), and the fourth semiconductor The second semiconductor layer formed above the layer and the third semiconductor layer formed above the second semiconductor layer may be included.

  In the above configuration, the second semiconductor layer and the third semiconductor layer may have a higher p-type impurity concentration than the fourth semiconductor layer. In this case, the fourth semiconductor layer can constitute a p-type cladding layer, and the second semiconductor layer can constitute a p-type contact layer.

The n-type semiconductor layer is composed of an n-type first semiconductor layer made of n-Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1). It does not matter.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device which can obtain a high light output, reducing an operating voltage conventionally is realizable.

It is sectional drawing which shows typically the structure of one Embodiment of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. 6 is a cross-sectional view schematically showing the structure of a light emitting device of Comparative Example 1. FIG. FIG. 6 is a cross-sectional view schematically showing the structure of a light emitting device of Comparative Example 2. It is sectional drawing which shows the structure of the light emitting element of the comparative example 3 typically. 4 is a table comparing input voltage and light output values when the same amount of current is injected into each light emitting element of Example 1, Comparative Example 1, and Comparative Example 2. FIG. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows typically a part of manufacturing process of the semiconductor light-emitting device of this invention. It is sectional drawing which shows the structure of the conventional semiconductor light-emitting device typically.

  A semiconductor light emitting device and a method for manufacturing the same according to the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio.

  First, after describing the structure of the semiconductor light emitting device of the present invention, the manufacturing method thereof will be described. Then, with reference to an Example, the performance of the semiconductor light emitting element of this invention and the conventional semiconductor light emitting element is compared.

[Construction]
FIG. 1 is a cross-sectional view schematically showing a configuration of one embodiment of a semiconductor light emitting device of the present invention. The semiconductor light emitting device 1 includes an n-type semiconductor layer 13, a p-type semiconductor layer 20, and an active layer 15 sandwiched between the n-type semiconductor layer 13 and the p-type semiconductor layer 20 on a growth substrate 11. A more detailed configuration of the semiconductor light emitting device 1 will be described below.

  The semiconductor light emitting device 1 shown in FIG. 1 has an undoped layer 12 on a growth substrate 11 and an n-type semiconductor layer 13 on the undoped layer. The semiconductor light emitting device 1 has an active layer 15 above the n-type semiconductor layer 13 and a p-type semiconductor layer 20 above the active layer 15. In the semiconductor light emitting device 1 shown in FIG. 1, the p-type semiconductor layer 20 includes a p-type semiconductor layer 21, a p-type semiconductor layer 22, and a p-type semiconductor layer 23.

  The n-type semiconductor layer 13 corresponds to a “first semiconductor layer”, the p-type semiconductor layer 21 corresponds to a “fourth semiconductor layer”, the p-type semiconductor layer 22 corresponds to a “second semiconductor layer”, The p-type semiconductor layer 23 corresponds to a “third semiconductor layer”. Hereinafter, the n-type semiconductor layer 13 is referred to as “first semiconductor layer 13”, the p-type semiconductor layer 21 is referred to as “fourth semiconductor layer 21”, and the p-type semiconductor layer 22 is referred to as “second semiconductor layer 22”. The p-type semiconductor layer 23 is referred to as a “third semiconductor layer 23”.

  That is, in the semiconductor light emitting device 1, the third semiconductor layer 23 constitutes the uppermost layer on the surface opposite to the active layer 15 among the surfaces of the p-type semiconductor layer 20.

(Growth substrate 11)
The growth substrate 11 is composed of a sapphire substrate as an example. The growth substrate 11 may be made of Si, SiC, AlN, AlGaN, GaN, YAG or the like in addition to sapphire.

(Undoped layer 12)
The undoped layer 12 is formed of GaN. More specifically, it is formed of a low-temperature buffer layer made of GaN and an underlying layer made of GaN on the upper layer. The undoped layer 12 is provided on the growth substrate 11 made of, for example, sapphire, for epitaxial growth of the first semiconductor layer 13 and the like in a good state.

(First semiconductor layer 13)
The first semiconductor layer 13 is composed of n-Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1). The first semiconductor layer 13 is doped with n-type impurities such as Si, Ge, S, Se, Sn, and Te, and is preferably doped with Si. In the present embodiment, as an example, the first semiconductor layer 13 is formed of n-Al _0.06 Ga _0.94 N.

(Active layer 15)
The active layer 15 is configured, for example, by periodically repeating a light emitting layer made of InGaN and a barrier layer made of AlGaN. These layers may be undoped or p-type or n-type doped.

  The active layer 15 is not limited to the above materials, and includes a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer. It is only necessary that one nitride semiconductor layer is sandwiched between two second nitride semiconductor layers. In this case, the first nitride semiconductor layer constitutes a light emitting layer, and the second nitride semiconductor layer constitutes a barrier layer. Each material constituting the active layer 15 is appropriately selected according to the peak wavelength of light to be extracted.

(Fourth semiconductor layer 21)
The fourth semiconductor layer 21 is constituted by _{p-Al x3 Ga y3 In 1} -x3-y3 N (0 <x3 ≦ 1,0 ≦ y3 <1). The fourth semiconductor layer 21 is doped with a p-type impurity such as Mg, Be, Zn, or C, and is particularly preferably doped with Mg. In the present embodiment, as an example, the fourth semiconductor layer 21 is formed with a stacked structure of p-Al _0.3 Ga _0.7 N and p-Al _0.13 Ga _0.87 N.

(Second semiconductor layer 22)
The second semiconductor layer 22 is constituted by _{p-Al x2 Ga y2 In 1} -x2-y2 N (0 <x2 ≦ 1,0 ≦ y2 <1). The second semiconductor layer 22 is doped with a p-type impurity such as Mg, Be, Zn, or C, and is particularly preferably doped with Mg. In the present embodiment, as an example, the second semiconductor layer 22 is formed of p-Al _0.13 Ga _0.87 N. In the present embodiment, the p-type impurity concentration of the second semiconductor layer 22 is higher than the p-type impurity concentration of the fourth semiconductor layer 21.

(Third semiconductor layer 23)
The third semiconductor layer 23 is composed of p-GaN having a thickness of 5 nm or less. The third semiconductor layer 23 is doped with a p-type impurity such as Mg, Be, Zn, or C, and is particularly preferably doped with Mg.

In the present embodiment, the p-type impurity concentration of the third semiconductor layer 23 is higher than the p-type impurity concentration of the fourth semiconductor layer 21. As an example, the p-type impurity concentration of the fourth semiconductor layer 21 is about 3 × 10 ¹⁹ / cm ³ , and the p-type impurity concentrations of the second semiconductor layer 22 and the third semiconductor layer 23 are about 1 × 10 ²⁰ / cm ^3. It is.

  In addition, as described later in the section of the manufacturing method, after forming the third semiconductor layer 23 by a predetermined film thickness in the process according to Step S7, the cooling process according to Step S8 is performed, so that the third semiconductor layer 23 is formed. Part of the film evaporates and the film thickness decreases. In FIG. 1, the upper layer of the third semiconductor layer 23 is indicated by a broken line in order to indicate that the film thickness has decreased after the third semiconductor layer 23 is formed. That is, FIG. 1 shows that the third semiconductor layer 23 corresponding to the broken line portion has evaporated in the step S8.

  In the above-described embodiment, the case where the semiconductor light emitting element 1 has the structure shown in FIG. 1 has been described. However, the semiconductor light emitting element 1 does not necessarily include the fourth semiconductor layer 21. That is, the semiconductor light emitting device 1 may be configured to include the second semiconductor layer 22 on the upper surface of the active layer 15.

  Further, when the semiconductor light emitting device 1 includes the fourth semiconductor layer 21, the p-type impurity concentration of the second semiconductor layer 22 does not necessarily have to be higher than the p-type impurity concentration of the fourth semiconductor layer 21.

[Production method]
Next, a method for manufacturing the semiconductor light emitting device 1 will be described. The dimensions such as manufacturing conditions and film thickness described below are merely examples, and are not limited to these numerical values.

(Step S1)
A growth substrate 11 is prepared. More specifically, a c-plane sapphire substrate is prepared as the growth substrate 11 and is cleaned. More specifically, for this cleaning, for example, a growth substrate 11 (c-plane sapphire substrate) is disposed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and a flow rate is set in the processing furnace. Is performed by raising the furnace temperature to, for example, 1150 ° C. while flowing 10 slm of hydrogen gas.

  This step S1 corresponds to the step (a).

(Step S2)
A low-temperature buffer layer made of GaN is formed on the surface of the growth substrate 11, and a base layer made of GaN is further formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 12.

  A specific method for forming the undoped layer 12 is, for example, as follows. First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, nitrogen gas and hydrogen gas having a flow rate of 5 slm are supplied as carrier gases into the processing furnace, while TMG having a flow rate of 50 μmol / min and ammonia having a flow rate of 250,000 μmol / min are supplied to the processing furnace for 68 seconds. To do. Thereby, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the growth substrate 11.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.

  By this step S2, an undoped layer 12 is formed on the growth substrate 11 as shown in FIG. 2A.

(Step S3)
Next, as shown in FIG. 2B, the n-type first semiconductor layer 13 is formed on the undoped layer 12. A specific method for forming the first semiconductor layer 13 is, for example, as follows.

First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, TMA having a flow rate of 6 μmol / min, and a flow rate of 250,000 μmol / min. Ammonia of min and tetraethylsilane having a flow rate of 0.013 μmol / min are supplied into the processing furnace for 60 minutes. Thereby, for example, a first semiconductor layer 13 having a composition of n-Al _0.06 Ga _0.94 N, a Si concentration of 5 × 10 ¹⁹ / cm ³ , and a thickness of 2 μm is formed on the undoped layer 12. Is done.

  Although the case where Si is used as the n-type impurity doped in the first semiconductor layer 13 has been described here, Ge, S, Se, Sn, Te, or the like can be used in addition to Si.

  Thereafter, the supply of TMA may be stopped and other source gases may be supplied for 6 seconds to form n-GaN having a thickness of about 5 nm on the first semiconductor layer 13.

  This step S3 corresponds to the step (b).

(Step S4)
Next, as shown in FIG. 2C, an active layer in which a light emitting layer made of, for example, InGaN and a barrier layer made of n-AlGaN are periodically repeated above the n-type first semiconductor layer 13. 15 is formed.

  Specifically, first, the furnace pressure of the MOCVD apparatus is set to 100 kPa, and the furnace temperature is set to 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, the active layer 15 in which the light-emitting layer made of InGaN having a thickness of 2 nm and the barrier layer made of n-AlGaN having a thickness of 7 nm are repeated 15 cycles becomes the first semiconductor layer 13. It is formed in the upper layer.

  This step S4 corresponds to the step (c).

(Step S5)
Next, as shown in FIG. 2D, a p-type fourth semiconductor layer 21 is formed on the active layer 15. A specific method for forming the fourth semiconductor layer 21 is, for example, as follows.

The furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are allowed to flow into the processing furnace. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (Cp ₂ Mg) is fed into the processing furnace for 60 seconds. Thus, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 15. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. The fourth semiconductor layer 21 is formed by these hole supply layers. The p-type impurity concentration of the fourth semiconductor layer 21 is, for example, about 3 × 10 ¹⁹ / cm ³ .

  Here, the temperature in the furnace is set to 1025 ° C., and the fourth semiconductor layer 21 is formed. However, if the temperature is equal to or higher than the lower limit temperature (for example, 800 ° C. or higher) at which AlGaN can be grown while doping the p-type impurity, It is not limited. However, the growth temperature is preferably 900 ° C. or higher, and more preferably 1000 ° C. or higher.

  This step S5 corresponds to the step (h).

(Step S6)
Next, as shown in FIG. 2E, the p-type second semiconductor layer 22 is formed on the p-type fourth semiconductor layer 21. A specific method for forming the second semiconductor layer 22 is, for example, as follows.

From step S5, while maintaining the furnace temperature and the carrier gas flow rate, the raw material gas was TMG with a flow rate of 20 μmol / min, TMA with a flow rate of 4 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and p-type impurities. Cp ₂ Mg having a flow rate for doping of 0.2 μmol / min is supplied into the processing furnace for 40 seconds. Thereby, the second semiconductor layer 22 having a composition of p-Al _0.13 Ga _0.87 N having a thickness of 10 nm is formed on the fourth semiconductor layer 21. The p-type impurity concentration of the second semiconductor layer 22 is, for example, about 1 × 10 ²⁰ / cm ³ .

  This step S6 corresponds to the step (d).

(Step S7)
Next, as shown in FIG. 2F, a p-type third semiconductor layer 23 is formed on the p-type second semiconductor layer 22. A specific method for forming the third semiconductor layer 23 is, for example, as follows.

While maintaining the temperature in the furnace from step S6, the supply of TMA is stopped and the flow rate of Cp ₂ Mg is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds. As a result, the third semiconductor layer 23 made of p-GaN having a thickness of about 5 nm is formed on the second semiconductor layer 22. The p-type impurity concentration of the third semiconductor layer 23 is, for example, about 1 × 10 ²⁰ / cm ³ .

  This step S7 corresponds to the step (e).

(Step S8)
Next, the supply of a predetermined source gas is stopped to lower the temperature in the furnace. This step S8 corresponds to the step (f).

  In the state immediately before the start of step S8 for lowering the temperature in the furnace, the p-type third semiconductor layer 23 made of p-GaN is formed on the upper surface of the second semiconductor layer 22 made of p-AlGaN. Yes. That is, even if the supply of gas is stopped in a state where the temperature in the furnace is high, the second semiconductor layer 22 made of a mixed crystal containing Al is not positioned on the uppermost surface. Thus, GaN does not evaporate and the upper surface of the second semiconductor layer 22 does not become Al-rich.

  In addition, since the third semiconductor layer 23 located on the uppermost surface of the p-type semiconductor layer 20 is made of p-GaN when the supply of the source gas is stopped, the temperature of the furnace is lowered. Even if GaN evaporates from the third semiconductor layer 23, no Al-rich layer is formed on the uppermost surface of the third semiconductor layer 23.

  After the completion of step S7, in the process of stopping the supply of the source gas and lowering the furnace temperature, at least a part of the p-GaN constituting the third semiconductor layer 23 evaporates, and the film thickness of the third semiconductor layer 23 Becomes thinner. In one example, when the step S8 is completed, the film thickness of the third semiconductor layer 23 is 1 nm or less. As described above, the film thickness of the third semiconductor layer 23 is thinner at the completion of step S8 than at the completion of step S7, and this is indicated by a broken line in FIG.

  In step S8, ammonia is allowed to flow until the temperature in the furnace decreases to about 700 ° C., and after the temperature decreases to about 700 ° C., nitrogen gas is used until the temperature in the furnace decreases to about room temperature. It is possible to supply only to the furnace. By doing in this way, the activation process of a wafer can be performed in the cooling process in a furnace.

(Subsequent processes)
After step S8, the wafer is taken out from the processing furnace, and a step of forming an electrode for energization (corresponding to step (g)) is performed. Specifically, the following method is used.

(Step S9)
As shown in FIG. 2G, a partial region of the p-type semiconductor layer 20 (the third semiconductor layer 23, the second semiconductor layer 22, and the fourth semiconductor layer 21) until a partial upper surface of the first semiconductor layer 13 is exposed. The active layer 15 is removed by dry etching using an ICP device. In step S9, the first semiconductor layer 13 may also be partially removed by etching.

(Step S10)
As shown in FIG. 2H, an n-side electrode 31 is formed on the upper surface of the first semiconductor layer 13, and a p-side electrode 32 is formed on the upper surface of the p-type semiconductor layer 20, more specifically on the upper surface of the third semiconductor layer 23. . A specific forming method is, for example, as follows.

  After depositing, for example, Cr having a thickness of 100 nm and Au having a thickness of 0.5 to 3 μm on at least a part of the upper surface of the first semiconductor layer 13, annealing is performed at 250 ° C. for about 1 minute in a nitrogen atmosphere. Do. Thereby, the n-side electrode 31 is formed on the upper surface of the first semiconductor layer 13.

  Further, a material film made of a conductive material is formed on at least a part of the upper surface of the third semiconductor layer 23. For example, Ag having a thickness of 150 nm and Ni having a thickness of 30 nm are formed in a predetermined region on the upper surface of the third semiconductor layer 23 by a sputtering apparatus. As this material film, in order to improve the adhesion with the third semiconductor layer 23, Ni having a film thickness of about 1.5 nm may be formed under the Ag layer. Thereafter, a contact annealing process is performed at 400 ° C. to 550 ° C. for 60 seconds to 300 seconds in a dry air or inert gas atmosphere using an RTA apparatus or the like. Thereby, the p-side electrode 32 is formed on the upper surface of the third semiconductor layer 23.

[Verification]
Hereinafter, verification is performed using Examples and Comparative Examples.

    (Example 1) The semiconductor light-emitting device 1 manufactured through the above steps S1 to S10 was used as the light-emitting device of Example 1. In Example 1, the second semiconductor layer 22 having a thickness of 10 nm was formed in Step S6, and the third semiconductor layer 23 having a thickness of 5 nm was formed in Step S7. In addition, after completion | finish of step S7, the film thickness of the 3rd semiconductor layer 23 fell to 1 nm or less through step S8.

  As described above, after the completion of step S7, the film thickness is reduced because part of the p-GaN constituting the third semiconductor layer 23 is evaporated in the furnace exposed to high temperature. It is considered a thing.

    (Comparative example 1) The semiconductor light-emitting device manufactured through steps S1 to S6 and S8 to S10 was used as the light-emitting device of Comparative Example 1. The comparative example 1 is different from the first example in that the third semiconductor layer 23 is not provided. In Comparative Example 1, after the second semiconductor layer 22 made of p-AlGaN having a thickness of 10 nm was formed in Step S6, the cooling process according to Step S8 was performed without forming the third semiconductor layer 23.

  That is, the uppermost surface of the p-type semiconductor layer in the state immediately before performing the cooling step is the second semiconductor layer 22 made of p-AlGaN. In addition, through step S8, the film thickness of the second semiconductor layer 22 has decreased to 6 nm or less, and an Al-rich layer 35 having a film thickness of about 2 nm was formed on the uppermost surface of the second semiconductor layer 22 ( (See FIG. 3A).

    (Comparative example 2) The semiconductor light-emitting device manufactured through steps S1 to S5 and S7 to S10 was used as the light-emitting device of Comparative Example 2. The comparative example 2 is different from the first example in that the second semiconductor layer 22 is not provided. In Comparative Example 2, after step S5 is completed, the second semiconductor layer 22 is not formed. In step S7, the third semiconductor layer 23 made of p-GaN having a thickness of 10 nm is formed, and then the cooling process according to step S8 is performed. Executed.

  That is, in the element of Comparative Example 2, the uppermost surface of the p-type semiconductor layer in the state immediately before performing the cooling step is the third semiconductor layer 23 made of p-GaN as in Example 1, but in the lower layer thereof Does not include the second semiconductor layer 22 made of p-AlGaN. In addition, through step S8, the film thickness of the third semiconductor layer 23 was reduced to about 6 nm (see FIG. 3B). The point that the film thickness of the third semiconductor layer 23 becomes thinner at the time of completion of step S8 than at the time of completion of step S7 is the same as in Example 1, and this is also indicated by a broken line in FIG. 3B as in FIG. Represents that.

    (Comparative Example 3) The semiconductor light emitting device manufactured through the steps S1 to S10, in which the third semiconductor layer 23 made of p-GaN having a film thickness of 10 nm was grown in step S7, the light emission of the comparative example 3. It was set as the element. That is, Comparative Example 3 differs from Example 1 in that the growth thickness of the third semiconductor layer 23 in Step S7 is increased.

  In Comparative Example 3, the third semiconductor layer 23 made of p-GaN is formed on the uppermost surface of the p-type semiconductor layer just before the cooling process according to Step S8, as in Example 1. A second semiconductor layer 22 made of p-AlGaN is formed below the third semiconductor layer 23. And in the comparative example 3, the film thickness of the 3rd semiconductor layer 23 fell to about 6 nm through the cooling process which concerns on step S8 (refer FIG. 3C). The point that the film thickness of the third semiconductor layer 23 becomes thinner at the time of completion of step S8 than at the time of completion of step S7 is the same as in Example 1, and this is indicated by the broken line in FIG. 3C as in FIG. Represents.

    (Results) When 20 mA was injected by applying a voltage between the n-side electrode 31 and the p-side electrode 32 to each of the light-emitting elements of Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3. The input voltage and optical output are shown in FIG. According to FIG. 4, compared with Comparative Example 1, Example 1 has the same optical output, but the input voltage is reduced. Moreover, compared with Comparative Example 2 and Comparative Example 3, Example 1 has the same input voltage but high optical output.

  As described above, in the light emitting device of Comparative Example 1, the Al-rich layer 35 having a thickness of about 2 nm is formed on the uppermost surface of the second semiconductor layer 22 located at the uppermost layer of the p-type semiconductor layer 20 through Step S8. Was formed. Compared to Example 1, the operating voltage of Comparative Example 1 is higher, suggesting that the contact resistance between the Al-rich layer 35 and the p-side electrode 32 is higher in Comparative Example 1. ing.

  Conversely, according to the light emitting device of Example 1, the third semiconductor layer 23 is located at the uppermost layer of the p-type semiconductor layer, and no Al-rich layer is formed on the uppermost surface. It can be seen that the contact resistance between the p-side electrode 32 and the light emitting element of Comparative Example 1 can be reduced. This is because the light emitting device of Comparative Example 2 in which the uppermost layer of the p-type semiconductor layer is the third semiconductor layer 23 made of p-GaN at the time immediately before the start of the cooling process according to Step S8 is the same as that of Example 1. It can be understood from the fact that the input voltage is lower than that of the light-emitting element of Comparative Example 1 as in the case of the light-emitting element.

  In the light emitting device of Comparative Example 2, even though a part of the third semiconductor layer 23 evaporates through the cooling process according to Step S8, the third semiconductor layer 23 made of p-GaN having a thickness of about 6 nm still remains. It will be.

  That is, the light-emitting element of Comparative Example 2 includes a GaN layer that is thicker than the GaN layer included in the light-emitting element of Example 1. As a result, since the absorption edge of GaN has a longer wavelength side than that of AlGaN, the proportion of light emitted from the active layer 15 that is absorbed by GaN is higher in the device of Comparative Example 2 than in Example 1. Thus, it is considered that the light output is lower than that in the first embodiment.

  This point also appears in the result of Comparative Example 3. As described above, in Comparative Example 3, unlike Comparative Example 2, the second semiconductor layer 22 made of p-AlGaN is formed below the third semiconductor layer 23. However, the element of Comparative Example 3 has the third semiconductor layer 23 with a thickness of about 6 nm after the cooling process according to Step S8. This result is similar to Comparative Example 2 because Comparative Example 3 includes a GaN layer having a thickness larger than that of the GaN layer included in Example 1, so that GaN out of the light emitted from the active layer 15 is GaN. It is considered that the light output is lower than that of Example 1 because the absorbed ratio is higher than that of Example 1.

  When realizing a semiconductor light emitting device that emits ultraviolet light having a peak wavelength of 400 nm or less, it is preferable to make GaN whose absorption edge is located on the longer wavelength side than AlGaN as thin as possible. This can be understood from the comparison results of Example 1 and Comparative Example 2, and Example 1 and Comparative Example 3. The third semiconductor layer 23 made of p-GaN is formed immediately after the start of the cooling process according to step S8, that is, immediately after the supply of the source gas is stopped, at the time when the temperature in the furnace is still at a high temperature. It is provided for the purpose of preventing the second semiconductor layer 22 made of AlGaN from being exposed to the upper surface. For this reason, the third semiconductor layer 23 is made as thin as possible within a range in which the second semiconductor layer 22 is not exposed on the upper surface until the temperature in the furnace is lowered to such an extent that GaN does not evaporate. Is more preferable.

  In view of the above, after the upper surface of the second semiconductor layer 22 made of p-AlGaN is covered with the third semiconductor layer 23 made of p-GaN, a cooling process is performed, so that a high light output is ensured while the operating voltage is maintained. It can be seen that a low semiconductor light emitting device can be realized.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> In embodiment mentioned above, it demonstrated as what forms the n side electrode 31 and the p side electrode 32 through steps S9-S10. In this case, the growth substrate 11 is used as it is as an element substrate, and a semiconductor light emitting device in which the n-side electrode 31 and the p-side electrode 32 are formed on the same surface side of the two surfaces of the growth substrate 11 is manufactured. An example of this will be described. Such a semiconductor light emitting device is sometimes referred to as a “lateral structure”. However, the present invention is not limited to the semiconductor light emitting device having such a lateral structure.

  Hereinafter, an example of a method for manufacturing a semiconductor light emitting device manufactured through another step after step S8 will be described. In addition, about S1-S8, since it is the same as the manufacturing method mentioned above, description is omitted.

(Step S11)
As shown in FIG. 5A, a reflective electrode 49 is formed at a predetermined location on the upper surface of the third semiconductor layer 23. Here, a case is shown in which the reflective electrode 49 is formed in almost the entire region of the third semiconductor layer 23 inside the region where the third semiconductor layer 23 is formed.

  For example, the reflective electrode 49 is formed by depositing 0.7 nm-thickness Ni and 150 nm-thick Ag on the upper surface of the third semiconductor layer 23 by a sputtering apparatus, and then using an RTA apparatus in a dry air atmosphere at 400 ° C. It is formed by performing contact annealing for 2 minutes. Here, an alloy of Ni and Ag is adopted as the material of the reflective electrode 49, but the reflective electrode 49 can also be formed of Al or Rh.

(Step S12)
Next, as shown in FIG. 5B, an insulating layer 51 is formed at a predetermined position on the upper layer of the reflective electrode 49. At this time, as shown in FIG. 5B, a part of the insulating layer 51 can be formed so as to cover the side surface of the reflective electrode 49.

More specifically, the upper layer of the reflective electrode 49 in the region where the insulating layer 51 is not formed is masked, and, for example, SiO _{2 is formed} to a thickness of about 200 nm by sputtering. Note that the material for forming the film may be an insulating material, such as SiN or Al ₂ O ₃ .

(Step S13)
As shown in FIG. 5C, the solder diffusion preventing layer 47 and the solder layer 45 are formed so as to cover the upper surfaces of the reflective electrode 49 and the insulating layer 51.

  More specifically, solder is formed by depositing three periods of Ti having a thickness of 100 nm and Pt having a thickness of 200 nm so as to cover the upper surfaces of the reflective electrode 49 and the insulating layer 51 with an electron beam evaporation apparatus (EB apparatus). A diffusion prevention layer 47 is formed. Furthermore, after depositing Ti with a film thickness of 10 nm on the upper surface (Pt surface) of the solder diffusion preventing layer 47, Au-Sn solder composed of Au 80% Sn 20% is vapor-deposited with a thickness of 3 μm. 45 is formed.

  In the step of forming the solder layer 45, the solder layer 43 may be formed on the upper surface of the support substrate 9 prepared separately from the growth substrate 11 (see FIG. 5D). This solder layer 43 may be made of the same material as that of the solder layer 45, and the growth substrate 11 and the support substrate 9 are bonded together by bonding to the solder layer 43 in the next step. For example, CuW is used as the support substrate 9 as described in the section of the structure.

  5D, the solder diffusion preventing layer 47 may be formed on the support substrate 9 and the solder layer 43 may be formed on the solder diffusion preventing layer 47.

(Step S14)
Next, as shown in FIG. 5E, the growth substrate 11 and the support substrate 9 are bonded together. More specifically, the solder layer 47 formed on the upper layer of the growth substrate 11 and the solder layer 43 formed on the upper layer of the support substrate 9 are bonded together at a temperature of 280 ° C. and a pressure of 0.2 MPa.

(Step S15)
Next, as shown in FIG. 5F, the growth substrate 11 is peeled off. More specifically, with the growth substrate 11 facing up and the support substrate 9 facing down, irradiation with a KrF excimer laser is performed from the growth substrate 11 side, and the interface between the growth substrate 11 and the semiconductor layer (undoped layer 12). Then, the growth substrate 11 is peeled off. While the growth substrate 11 passes through the laser, the underlying GaN (undoped layer 12) absorbs the laser, so that the temperature of the interface is increased and GaN is decomposed. As a result, the growth substrate 11 is peeled off.

  Thereafter, as shown in FIG. 5G, GaN (undoped layer 12) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the first semiconductor layer 13 is removed. Expose.

(Step S16)
Next, as shown in FIG. 5H, adjacent elements are separated. Specifically, the semiconductor layer (the first semiconductor layer 13, the active layer 15, the fourth semiconductor layer 21, the second semiconductor is used until the upper surface of the insulating layer 51 is exposed to the boundary region with the adjacent element using an ICP device. Layer 22 and third semiconductor layer 23) are etched. At this time, the insulating layer 51 also functions as a stopper during etching.

(Step S17)
Next, as shown in FIG. 5I, n-side electrodes (72, 73) are formed on the upper surface of the first semiconductor layer 13 at positions facing the insulating layer 51 in the direction orthogonal to the surface of the support substrate 9. To do. Specifically, after forming an electrode made of Cr having a thickness of 100 nm and Au having a thickness of 3 μm, sintering is performed at 250 ° C. for 1 minute in a nitrogen atmosphere.

  Then, the elements are separated from each other by, for example, a laser dicing apparatus, the back surface of the support substrate 9 is joined to the package by, for example, Ag paste, and wire bonding is performed on the n-side electrode 73 as a power supply terminal. For example, wire bonding is performed by connecting a wire 45 made of Au to a bonding region of Φ100 μm with a load of 50 g.

  Even in such a configuration, since the third semiconductor layer 23 made of p-GaN is provided, an Al-rich layer is not formed on the upper surface (the surface on the reflective electrode 49 side) of the second semiconductor layer 22 made of p-AlGaN. Therefore, the contact resistance does not increase due to the contact between the Al-rich layer and the reflective electrode 49. In addition, since the third semiconductor layer 23 made of p-GaN can be formed of an extremely thin film, even when realizing a semiconductor light emitting device that emits ultraviolet light having a peak wavelength of 400 nm or less, it is absorbed by the third semiconductor layer 23. It is possible to suppress the amount of light to be minimized, and a high light output is realized.

  The method of steps S11 to S17 is an example of a method for manufacturing a semiconductor light emitting device having a so-called “vertical structure”, and the present invention is limited to a semiconductor light emitting device manufactured by applying this method. is not.

<2> In the embodiment described above, the first semiconductor layer 13 is composed of n-AlGaN, but is n-Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1). You may comprise.

In the above-described embodiment, the second semiconductor layer 22 is composed of p-AlGaN. However, the second semiconductor layer 22 is composed of p-Al _x2 Ga _y2 In _1-x2-y2 N (0 <x2 ≦ 1, 0 ≦ y2 <1). It doesn't matter. Similarly, in the above-described embodiment, the fourth semiconductor layer 21 is composed of p-AlGaN, but is composed of p-Al _x3 Ga _y3 In _1-x3-y3 N (0 <x3 ≦ 1, 0 ≦ y3 <1). You may comprise.

<3> After the third semiconductor layer 23 made of p-GaN is formed in Step S7, the third semiconductor layer 23 may be completely evaporated through the cooling process in Step S8. In this case, the second semiconductor layer 22 made of p-Al _x2 Ga _y2 In _1-x2-y2 N (0 <x2 ≦ 1, 0 ≦ y2 <1) is exposed during the cooling process according to step S8. However, as compared with the conventional light emitting device, the timing at which the second semiconductor layer 22 is exposed can be delayed by the time required for the third semiconductor layer 23 to completely evaporate. The amount of evaporation of GaN can be suppressed.

  Therefore, since the Al-rich layer formed on the upper surface of the second semiconductor layer 22 can be made extremely smaller than the conventional light emitting element, an operating voltage lower than that of the conventional light emitting element can be realized.

  <4> In the above embodiment, the temperature in the furnace is maintained over steps S5 to S7. However, this method is merely an example, and each p-type semiconductor layer is changed slightly while changing the temperature in the furnace between the steps. It is not intended to exclude the method of forming (21, 22, 23) from the scope of the present invention.

1: Semiconductor light-emitting device of the present invention
9: Support substrate
11: Growth substrate
12: Undoped layer
13: First semiconductor layer (n-type semiconductor layer)
15: Active layer
20: p-type semiconductor layer
21: Fourth semiconductor layer (p-type semiconductor layer)
22: Second semiconductor layer (p-type semiconductor layer)
23: Third semiconductor layer (p-type semiconductor layer)
31: n-side electrode
32: p-side electrode
35: Al-rich layer
43, 45: Solder layer
47: Solder diffusion prevention layer
49: Reflective electrode
51: Insulating layer
72, 73: n-side electrode 100: conventional semiconductor light emitting device 101: substrate 102: buffer layer 103: n-type contact layer 104: n-type cladding layer 105: active layer 106: p-type cladding layer 107: first p-type Contact layer 108: second p-type contact layer 109: n-side electrode 110: p-side electrode

Claims (9)

Preparing a substrate (a),
A step (b) of forming an n-type first semiconductor layer made of n-Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1) on the substrate;
Forming an active layer on the first semiconductor layer (c);
An upper layer of the active _{layer, p-Al x2 Ga y2 In} 1-x2-y2 N p -type second semiconductor made of (0 <x2 ≦ 1,0 ≦ y2 <1) the temperature in the furnace as 800 ° C. or higher Forming a layer (d),
A step (e) of forming a p-type third semiconductor layer made of p-GaN at a temperature in the furnace of 800 ° C. or higher on the second semiconductor layer;
And the manufacturing method of the semiconductor light-emitting device characterized by having the process (f) which lowers | hangs the furnace temperature after the said process (e).   2. The method of manufacturing a semiconductor light emitting element according to claim 1, further comprising a step (g) of forming an electrode on the third semiconductor layer after the step (f). 3.   The step (e) is a step that is executed by changing only the flow rate of the source gas supplied into the furnace as compared with the step (d). Manufacturing method of the semiconductor light-emitting device.   4. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein after the step (f) is performed, the film thickness of the third semiconductor layer is 5 nm or less. 5. After the step (c), the upper layer of the active layer, _p-Al the temperature in the furnace as 800 ° C. or higher _{x3 Ga y3 In 1-x3-} y3 N (0 <x3 ≦ 1,0 ≦ y3 <1) A step (h) of forming a p-type fourth semiconductor layer comprising:
The step (d) is performed after the step (h), and is a step of forming the second semiconductor layer having a higher p-type impurity concentration than the fourth semiconductor layer. Item 5. The method for producing a semiconductor light-emitting device according to any one of Items 1 to 4. The substrate has an n-type semiconductor layer, a p-type semiconductor layer, and an active layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer, and emits ultraviolet light having a peak wavelength of 400 nm or less. A semiconductor light emitting device,
The p-type semiconductor layer includes a p-type second semiconductor layer made of p-Al _x2 Ga _y2 In _1-x2-y2 N (0 <x2 ≦ 1, 0 ≦ y2 <1), and a p-thickness of 5 nm or less. A p-type third semiconductor layer made of GaN,
The third semiconductor layer is the uppermost layer on the surface opposite to the active layer among the surfaces of the p-type semiconductor layer.   The semiconductor light emitting element according to claim 6, further comprising an electrode on an upper layer of the third semiconductor layer. The p-type semiconductor layer includes a p-type fourth semiconductor layer made of p-Al _x3 Ga _y3 In _1-x3-y3 N (0 <x3 ≦ 1, 0 ≦ y3 <1), and the fourth semiconductor layer The semiconductor light emitting device according to claim 6, comprising the second semiconductor layer formed in an upper layer and the third semiconductor layer formed in an upper layer of the second semiconductor layer. The n-type semiconductor layer is composed of an n-type first semiconductor layer made of n-Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1). The semiconductor light-emitting device according to claim 6.

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