JP2016004916A - Solar battery and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solar battery that can prevent degradation of characteristics caused by wraparound of anti-reflection coating without increasing the number of manufacturing steps, and enhance the photoelectric conversion efficiency.SOLUTION: A method of manufacturing a solar battery uses a p-type monocrystal silicon substrate 1 as an example of a crystalline semiconductor substrate having a first conduction type having a first principal surface as a photodetection face 1A and a back face 1B as a second principal surface confronting the first principal surface. Second conduction type impurities are diffused in the p-type monocrystal silicon substrate 1 to form an n-type diffusion layer 2. The n-type diffusion layer 2 of the side surface 1C located between the photodetection face 1A and the back surface 1B is removed to separate the area into first and second conduction type areas. A silicon nitride film is formed in the range from 55 to 60 nm in thickness by the CVD method so that the silicon nitride film extends from the photodetection face 1A to the side surface 1C, thereby forming an anti-reflection coating 3.

Description

  The present invention relates to a solar cell manufacturing method and a solar cell, and more particularly to pn separation of a solar cell.

  One method of forming a pn junction in a general single crystal silicon solar cell or polycrystalline silicon solar cell is to form an n-type layer by diffusing an n-type impurity in a p-type silicon substrate by thermal diffusion. There is a method of forming. During thermal diffusion, a PSG layer (Phosphorus Silicon Glass), which is a glass layer having n-type conductivity, is deposited at the same time on the edge of the substrate. Therefore, if the PSG layer at the edge of the substrate is left, electrical leakage occurs and cell characteristics are degraded. Therefore, the PSG layer at the edge of the substrate is etched to separate the pn junction. In order to remove the PSG layer, a conventionally used method is dry etching using a RIE (Reactive Ion Etching) method.

In order to efficiently absorb the incident light in the process after removing the PSG layer, a thin film called an antireflection film is usually deposited or grown on the light receiving surface. The antireflection film is made of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), titanium oxide, magnesium fluoride, aluminum oxide, tantalum oxide, zinc sulfide or the like having a thickness of about several tens to hundreds of nanometers. Used in combination. Among them, the silicon nitride film has a composition of Si ₃ N ₄ stoichiometrically, but the ratio of silicon (Si) and nitrogen (N) in the film can be controlled by the generation conditions. Sometimes referred to as _x . A silicon nitride film has a wider range of application than other materials because it is relatively easy to change the refractive index depending on the generation conditions. In recent years, for example, a plasma CVD apparatus capable of forming a large amount of SiN _x film at a high speed has been developed and attracts attention.

  On the other hand, when this antireflection film is formed by a plasma CVD apparatus, there is a problem that the characteristics are deteriorated by wrapping around the side surface or the other surface of the semiconductor substrate. For this reason, Patent Document 1 discloses a film forming method for preventing an antireflection film formed on one surface from wrapping around a side surface or another surface of a semiconductor substrate. In Patent Document 1, the substrate holder frame in the plasma CVD apparatus suppresses the semiconductor substrate from entering the side surface or the other surface.

  In addition, a method of physically removing the PSG layer and the antireflection film simultaneously by laser or blasting after the formation of the antireflection film, or a method of wet etching the PSG layer has been proposed. In patent document 2, it cut | disconnects physically using a laser after antireflection film formation.

JP 2007-197745 A JP 2012-209316 A

  However, when the above conventional technique is used to prevent the characteristic deterioration due to the wraparound as described above, there are the following problems. For example, in Patent Document 1, wraparound is suppressed by providing a frame on a substrate holder installed in a plasma CVD apparatus. Although the method of Patent Document 1 can prevent the plasma CVD film from wrapping around, the effective area is reduced in the region where the antireflection film is not formed because the antireflection effect and the substrate termination effect, that is, the passivation effect are not present.

  In Patent Document 2, when the separation groove is formed using a laser, there is a problem that the substrate is damaged and the characteristics are deteriorated. Further, in both cases of Patent Documents 1 and 2, the manufacturing cost increases.

  This invention is made | formed in view of the above, Comprising: It aims at obtaining the manufacturing method of the solar cell which can suppress the characteristic fall by wraparound, without increasing a manufacturing man-hour.

  In order to solve the above-described problems and achieve the object, the present invention provides a crystal having a first conductivity type having a first main surface that is a light-receiving surface and a second main surface that faces the first main surface. A step of diffusing a second conductivity type impurity to form a second conductivity type semiconductor layer in a semiconductor substrate, and a second conductivity type of a side surface located between the first main surface and the second main surface A silicon nitride film is formed so as to reach from the first main surface to the side surface of the semiconductor substrate by a pn separation process step of removing the semiconductor layer and performing region separation into first and second conductivity types and a CVD method And the step of forming the silicon nitride film is a step of forming a film with a thickness in the range of 55 to 60 nm.

  According to the present invention, there is an effect that it is possible to suppress deterioration of characteristics due to wraparound without increasing the number of manufacturing steps only by controlling the film thickness of the silicon nitride film to 55 to 60 nm.

1A and 1B are diagrams illustrating a solar cell according to a first embodiment, in which FIG. 1A is a plan view schematically showing a main part configuration on the light receiving surface side, and FIG. (C) is AA sectional drawing of (a), BB sectional drawing of (b). FIG. 2 is a flowchart showing the manufacturing process of the solar cell. 3A to 3G are process cross-sectional views illustrating the manufacturing process of the solar cell. FIG. 4 is a diagram showing the correlation of cell conversion efficiency with respect to the thickness of the silicon nitride film which is an antireflection film. FIG. 5 is a diagram showing the correlation of Id (dark current) with respect to the film thickness of silicon nitride which is an antireflection film. 6A and 6B are process cross-sectional schematic diagrams illustrating a pn separation process step in the manufacturing process of the solar cell according to the second embodiment.

  Below, the manufacturing method of the solar cell concerning this invention and embodiment of a solar cell are described in detail based on drawing. In addition, this invention is not limited by this embodiment, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings.

Embodiment 1 FIG.
FIG. 1 shows a solar cell according to Embodiment 1, FIG. 1 (a) is a plan view showing the external appearance of the solar cell on the light-receiving surface side, and FIG. FIG. 1C is a cross-sectional view corresponding to the AA cross section of FIG. 1A and the BB cross section of FIG. 1B. The solar cell 10 according to the first embodiment is opposed to the light receiving surface 1A and the first main surface, which are the first main surface of the p-type single crystal silicon substrate 1 that functions as a crystalline semiconductor substrate having the first conductivity type. On the back surface 1B which is the second main surface, a surface uneven portion called texture 1T for confining light is formed with a depth of about 10 μm. An n-type diffusion layer 2 which is a second conductivity type semiconductor layer having a thickness of 0.2 μm is formed on the surface of the texture 1T on the light-receiving surface 1A side of the p-type single crystal silicon substrate 1 to form a pn junction. An antireflection film 3 made of a silicon nitride film is formed on the n-type diffusion layer 2 to reduce reflection and improve the light utilization rate. On the surface on the light receiving surface 1 </ b> A side, a light receiving surface electrode composed of a large number of thin finger electrodes 4 and several thick bus electrodes 5 orthogonal to the finger electrodes 4 is formed in the opening of the antireflection film 3. In this embodiment, the antireflection film 3 is a silicon nitride film having a film thickness of 55 nm to 60 nm formed by a CVD method. Here, the texture 1T is formed on the surface of the p-type single crystal silicon substrate 1, but the unevenness is exaggerated to enhance the visibility.

  The p-type single crystal silicon substrate 1 is positioned between the light receiving surface 1A on which light is incident, the back surface 1B facing the light receiving surface 1A, and the light receiving surface 1A and the back surface 1B. And 1C of side surfaces which connect. The back surface 1B is a surface located on the back side of the light receiving surface 1A, and has the same shape as the light receiving surface 1A. In the present embodiment, the planar shapes of the light receiving surface 1A and the back surface 1B are square-processed wafers (pseudo-square wafers) processed to remove the corners as shown in FIG. 1, but squares can also be used. It is. The first conductivity type semiconductor substrate is not limited to p-type but may be n-type, and may be polycrystalline without being limited to single crystal.

On the other hand, on the back surface 1 </ b> B of the solar cell, a back electrode composed of a current collecting back surface collecting electrode 7 and an external extraction electrode 8 is disposed on the p-type single crystal silicon substrate 1. An aluminum and silicon alloy layer (not shown) is formed under the back surface collecting electrode 7, and a back surface electric field layer comprising a P ⁺ layer by aluminum diffusion is formed under the aluminum and silicon alloy layer. A BSF layer 6 is formed. The BSF layer 6 is formed on the back surface 1B of the p-type single crystal silicon substrate 1, but the n-type diffusion layer 2 remains slightly on the outer periphery, that is, the edge of the back surface 1B.

  The p-type single crystal silicon substrate 1 is a rectangular flat plate that is square-processed, for example, having a side of about 150 mm to 160 mm and a thickness of about 150 μm to 250 μm. A pn junction region where p-type silicon and n-type silicon are joined is formed on the outer peripheral surface of the p-type single crystal silicon substrate 1. That is, the pn junction is provided along the outer peripheral surface of the p-type single crystal silicon substrate 1 which is a semiconductor substrate, and is provided from the light receiving surface 1A to the outer peripheral edges of the side surface 1C and the back surface 1B. More specifically, the pn junction may be provided on the entire outer surface of the light receiving surface 1A, the entire surface of the side surface 1C, and the outer surface of the back surface 1B where the current collecting back electrode 7 is not provided. Details will be described later.

  As shown in FIG. 1A, the electrode on the light receiving surface 1A side has a bus electrode 5 and a finger electrode 4 connected thereto as an n-type electrode. The bus electrode 5 has a wide width of about 1 mm to 3 mm and is provided on the light receiving surface 1A in parallel with about 2 to 4 wires. A large number of finger electrodes 4 are provided at a pitch of about 1 mm to 5 mm on the light receiving surface 1 </ b> A so as to intersect perpendicularly to the bus electrode 5. The width of the finger electrode 4 is about 20 μm to 200 μm. The thicknesses of the bus electrode 5 and the finger electrode 4 are about 10 μm to 20 μm. An antireflection film 3 for improving light absorption is formed on the entire surface of the light receiving surface 1A. Actually, as shown in FIG. 1C, the antireflection film 3 is formed so as to reach the outer peripheral edge of the back surface 1B from the light receiving surface 1A through the side surface 1C.

  As shown in FIG. 1B, the electrode on the back surface 1B side has a back surface collecting electrode 7 for collecting current and an output extracting electrode 8 for taking out the current collected by the back surface collecting electrode 7. . The back surface collecting electrode 7 is formed on the entire surface of the back surface 1B of the p-type single crystal silicon substrate 1 except for the outer peripheral portion. The output extraction electrode 8 has a width of about 2 mm to 5 mm, and is provided on the back surface 1 </ b> B in the same direction as the bus electrode 5 extends so as to have about 2 to 4 wires. At least a part of the output extraction electrode 8 is in electrical contact with the back collector electrode 7. The thickness of the output extraction electrode 8 is about 10 μm to 20 μm, and the thickness of the back collecting electrode 7 is about 15 μm to 50 μm.

  Here, the finger electrode 4 and the back surface collecting electrode 7 have a role of collecting carriers generated by photoelectric conversion. The bus electrode 5 and the output extraction electrode 8 have a role of collecting the carriers collected by the finger electrode 4 and the back surface collecting electrode 7 and outputting them to the outside.

  As described above, the pn junction is provided in the outer peripheral portion of the back surface 1B where the back surface collecting electrode 7 is not provided. Therefore, in the back surface 1B, the back surface collecting electrode 7 is provided adjacent to the pn junction region.

  In the present embodiment, the edges of the outer peripheral edges of the light receiving surface 1A and the back surface 1B of the p-type single crystal silicon substrate 1, that is, the edges, are subjected to an etching process by a dry etching apparatus to perform pn separation. The n-type diffusion layer 2 is removed. That is, the n-type diffusion layer 2 is formed on the entire surface of the p-type single crystal silicon substrate 1, and the side n-type diffusion layer 2 is removed by end face etching for pn separation. Further, the n-type diffusion layer 2 on the back surface side is inverted by the back surface diffusion to become the BSF layer 6. However, when the end surface etching is performed by dry etching, the texture valley portion may become a shadow and remain without being etched. The n-type diffusion layer 2 is not shown because it is slight even if it remains. However, when the n-type diffusion layer 2 remains even slightly, a pn junction may be formed from the light receiving surface 1A to the outer peripheral edges of the side surface 1C and the back surface 1B as described above. Furthermore, since the BSF layer 6 is formed on the back surface 1B after the formation of the silicon nitride film 3 as an antireflection film, the n-type diffusion layer 2 may remain slightly on the outer periphery, that is, the edge of the back surface 1B. .

  According to the solar cell of the present embodiment, it is desirable that the n-type diffusion layer 2 does not remain on the edge or side surface on the back surface side, and the end surface etching is performed reliably, but as described above. Even when the n-type diffusion layer 2 remains on the edge or side surface on the back surface side, the leakage current can be reduced by controlling the film thickness of the silicon nitride film, and the n-type diffusion can be achieved. It is possible to suppress deterioration of characteristics due to the wraparound of the layer 2.

In the solar cell configured as described above, the sunlight is from the light receiving surface 1A side of the solar cell to the pn junction surface of the p-type single crystal silicon substrate 1 (the junction surface between the p-type single crystal silicon substrate 1 and the n-type diffusion layer 2). ), Holes and electrons are generated. The generated electrons move toward the n-type diffusion layer 2, and the holes move toward the p-type single crystal silicon substrate 1, which is a p ⁺ layer, by the electric field at the pn junction. As a result, electrons are excessive in the n-type diffusion layer 2 and holes are excessive in the p ⁺ layer. As a result, a photovoltaic force is generated. This photovoltaic force is generated in the direction in which the pn junction is forward-biased, and the finger electrode 4 and the bus electrode 5 connected to the n-type diffusion layer 2 become negative poles, and the back surface collector connected to the BSF layer 6 which is a p ⁺ layer. The electric electrode 7 and the output extraction electrode 8 become positive poles, and current flows in the external circuit. Thereby, carriers are collected on both electrodes, and a potential difference is generated between both electrodes.

  Next, the manufacturing method of this solar cell is demonstrated. FIG. 2 is a flowchart showing the method for manufacturing the solar cell according to Embodiment 1, and FIGS. 3A to 3G are process cross-sectional views. First, as shown in FIG. 3A, a flat p-type single crystal silicon substrate 1 obtained by slicing a silicon ingot is prepared. The n-type single crystal silicon substrate 1 is, for example, a p-type having a specific resistance of about 0.2 Ω · cm to 2.0 Ω · cm, which exhibits a p-type conductivity by adding a small amount of boron (B) impurities to silicon. A single crystal silicon substrate 1 can be used. The impurity added here is not limited to boron, but can be applied to other group III elements.

  More specifically, when a single crystal semiconductor substrate is used, the semiconductor substrate is manufactured by, for example, a pulling method such as the Czochralski method, and is manufactured by slicing using a cutting apparatus such as a wire saw. In the case of using a polycrystalline semiconductor substrate, for example, a silicon ingot produced by a polycrystal formation method such as a casting method is sliced to a thickness of 350 μm or less, more preferably about 150 μm to 250 μm using a wire saw. .

  The shape of the semiconductor substrate may be a circle, a square, or a rectangle, and the size of the semiconductor substrate may be a diameter of about 100 mm to 200 mm for a circle, and a side of a square or a rectangle may be about 100 mm to 200 mm. The semiconductor substrate having any shape has a light receiving surface, a back surface, and a side surface as described above.

  First, a p-type single crystal silicon substrate 1 having a thickness of, for example, several hundred μm is prepared as a semiconductor substrate, and substrate cleaning is performed (substrate cleaning step S10). Since the p-type single crystal silicon substrate 1 is manufactured by slicing an ingot formed by cooling and solidifying molten silicon with a wire saw, damage at the time of slicing remains on the surface. Therefore, the p-type single crystal silicon substrate 1 is generated when the p-type single crystal silicon substrate 1 is cut out by immersing the p-type single crystal silicon substrate 1 in an acid such as hydrofluoric acid or a heated alkaline solution, for example, in an aqueous sodium hydroxide solution and etching the surface. Thus, the damaged region existing near the surface of the p-type single crystal silicon substrate 1 is removed. Then, it wash | cleans with a pure water (Fig.3 (a)).

  Following the damage removal, the p-type single crystal silicon substrate 1 is immersed in a mixed solution of, for example, sodium hydroxide and isopropyl alcohol (IPA), and anisotropic etching is performed on the p-type single crystal silicon substrate 1 to obtain a p-type. A texture 1T composed of minute irregularities is formed at a depth of about 10 μm on the light receiving surface 1A side and the back surface 1B side of the single crystal silicon substrate 1 (FIG. 3B: texture forming step S20). Alternatively, an uneven shape of 1 μm to 3 μm may be formed on the surface by a dry etching process such as RIE.

  By providing such a texture structure on the light receiving surface 1A side and the back surface 1B side of the p-type single crystal silicon substrate 1, multiple reflection of light occurs on the light receiving surface 1A side of the solar cell element, and the light enters the solar cell element. Light can be efficiently absorbed inside the p-type single crystal silicon substrate 1, and the reflectance can be effectively reduced to improve the conversion efficiency. When the damaged layer is removed and the texture structure is formed with an alkaline solution, the concentration of the alkaline solution may be adjusted to a concentration according to each purpose, and continuous treatment may be performed. Further, a texture 1T having a depth of about 1 μm to 3 μm may be formed on the surface of the p-type single crystal silicon substrate 1 by a dry etching process such as RIE.

Next, diffusion treatment is performed to form a pn junction in the p-type single crystal silicon substrate 1. That is, a group V element such as phosphorus (P) is diffused into the p-type single crystal silicon substrate 1 to form the n-type diffusion layer 2 (FIG. 3C: diffusion processing step S30). Here, a pn junction is formed on a p-type single crystal silicon substrate 1 having a textured structure on its surface by diffusing phosphorus by thermal diffusion at a high temperature in a phosphorus oxychloride (POCl ₃ ) gas by a vapor phase diffusion method. To do. That is, the n-type diffusion layer 2 is formed from the light receiving surface 1A to the side surface 1C and the back surface 1B of the p-type single crystal silicon substrate 1. P (phosphorus) can be used as the n-type doping element. The n-type diffusion layer 2 can be an n-type layer having a sheet resistance of about 30Ω / □ to 150Ω / □. As a result, a pn junction is formed between the p-type single crystal silicon substrate 1 and the n-type diffusion layer 2 which are the above-described p-type bulk regions. By using such a method, the n-type diffusion layer 2 is formed on the surface of the p-type single crystal silicon substrate 2 with a depth of about 0.2 μm to 0.7 μm.

  Thereafter, as shown in FIGS. 6A and 6B, only the substrate end is exposed (preferably a plurality of substrate front and back surfaces are overlapped, and only the substrate end is exposed (hereinafter referred to as “stack”). Then, only the substrate edge is etched by a dry etching apparatus (FIG. 3D: pn separation step S40). The edge is etched on the entire surface of the substrate (light receiving surface, back surface, This is for separating the light-receiving surface and the back surface into p-type and n-type, respectively (pn separation), from the state where the n-type layer as the diffusion layer is formed in the end portion. In performing pn separation, in addition to a method using a dry etching apparatus, a chemical removal method such as a wet etching method, a physical removal method such as a method using a laser as in Patent Document 2, and There is a removal method and the combination method of the physical removal method.

After pn separation by dry etching, an antireflection film 3 is formed on the light receiving surface 1A (FIG. 3E: antireflection film formation step S50). The antireflection film 3 is formed so as to reach the outer peripheral edge of the back surface 1B from the light receiving surface 1A through the side surface 1C. As the material of the antireflection film 3, the most common silicon nitride film (SiN _x film: stoichiometric state, that is, the ratio (composition) of the number of atoms constituting the SiN compound exists according to the chemical formula. A silicon nitride film having a composition ratio (x) having a width around Si ₃ N ₄ is used. Here, the film thickness of the antireflection film 3 is formed in a plasma CVD apparatus in the range of 55 μm to 60 μm. FIG. 4 is a diagram showing the results of measuring the relationship between the film thickness and the cell conversion efficiency when the film thickness of the SiN _x film as the antireflection film is changed. The horizontal axis represents the film thickness (nm), and the vertical axis represents the cell conversion efficiency (unit is the standard value). As a result, it can be seen that the cell conversion efficiency is the highest when the thickness of the antireflection film 3 is in the range of 55 μm to 60 μm. Here, there is a point that the cell conversion efficiency is high when the film thickness of the antireflection film 3 is about 62 μm, but since there is a steeply lowered portion immediately after that, the safe range is 55 μm to 60 μm. It is. The optimum range of the film thickness of the antireflection film 3 may slightly shift depending on the ambient conditions, but there is no significant difference, and the FF (fill factor) can be improved by selecting the above range. For example, in the case of silicon, the antireflective film 3 has a refractive index of about 1.8 to 2.3, and in the first embodiment, for example, about 2.1 is used.

The characteristic that decreases due to the wraparound of the SiN _x layer is mainly FF accompanying the increase in the dark current Id. Incidentally, the increase in the dark current Id means that the separation of the pn junction is not sufficient. A CVD (SiN _x ) film formed by a plasma CVD apparatus usually used for forming an antireflection film of a solar cell has a certain degree of conductivity. For this reason, it is considered that the dark current Id increases when the SiN _x layer wraps around from the light receiving surface (first conductivity type, for example, n-type region) side to the back surface (second conductivity type, for example, p-type region) side. It is done.

As shown in FIG. 5, the inventors of the present invention have a linear relationship between the dark current Id and the film thickness of the SiN _x film as the antireflection film, and are suitable for the film thickness and the conversion efficiency of the solar battery cell Found that there is a range. In FIG. 5, the horizontal axis represents the film thickness (nm) of the silicon nitride film SiN _x , and the vertical axis represents one film thickness and conversion efficiency when only one film thickness of SiN is changed (unit is a standard value). The result of having measured the relationship with is shown. Therefore, it is not necessary to physically separate the antireflective film by controlling the film thickness of the antireflective film within a range where conversion efficiency suitable for use as a device can be obtained, and the number of manufacturing steps of the solar battery cell is increased. The effect that the characteristic fall by wraparound can be suppressed is produced.

Next, the back surface collecting electrode 7 and the output extraction electrode 8 are formed on the back surface 1B of the p-type single crystal silicon substrate 1 (FIG. 3F: back electrode forming step S60). The back surface collecting electrode 7 is formed by applying a paste mainly composed of aluminum over the entire back surface 1B. After applying the paste, aluminum is baked onto the p-type single crystal silicon substrate 1 by heat treatment (baking) at a temperature of about 700 ° C. to 900 ° C. By printing and baking the applied aluminum paste in this way, aluminum as a p-type impurity can be diffused at a high concentration in the applied portion of the p-type single crystal silicon substrate 1, and is also formed on the back surface 1B. The n-type diffusion layer 2 can be inverted and replaced with the BSF layer 6 which is a p-type heavily doped layer (p ⁺ layer). The p-type heavily doped layer on the back surface 1 </ b> B thus formed serves as a contact layer for the back surface collecting electrode 7.

  Next, electrodes located on the light receiving surface 1A, that is, bus electrodes 5 and finger electrodes 4 (not shown) are formed (FIG. 3G: light receiving surface electrode forming step S70). Here, the bus electrode 5 and the finger electrode 4 are obtained by baking for several tens of seconds to several tens of minutes at a maximum temperature of 500 ° C. to 650 ° C. in a baking furnace.

  The output extraction electrode 8 on the back surface 1B and the bus electrode 5 and the finger electrode 4 which are light receiving surface electrodes are formed by applying a conductive paste mainly composed of silver. In the conductive paste mainly composed of silver, for example, an organic vehicle and glass frit are mixed and kneaded in an amount of 5 to 30 parts by weight and 0.1 to 15 parts by weight, respectively, with 100 parts by weight of silver filler. A solvent adjusted to a viscosity of about 50 Pa · S to 200 Pa · S can be used.

  As a method for applying the conductive paste, a printing method such as a screen printing method can be used, and after application, the solvent may be evaporated and dried at a constant temperature. Further, the output extraction electrode 8 on the back surface 1B side may be dried after printing, and fired at the same time as the bus electrode 5 and the finger electrode 4 on the light receiving surface 1A side. Thereby, the heat treatment process used as a high temperature process can be carried out once, and productivity can be improved.

  Next, electrodes (bus electrodes 5 and finger electrodes 4) on the light receiving surface 1A of the p-type single crystal silicon substrate 1 are formed. Also in the formation of the bus electrode 5 and the finger electrode 4, as described above, the conductive paste mainly composed of silver can be formed by applying, drying, and baking using a printing method such as a screen printing method. . The solar cell 10 can be manufactured through the above steps.

  Thus, the solar cell with favorable FF characteristic can be obtained by using the antireflection film 3 as a silicon nitride film having a film thickness of 55 nm to 60 nm formed by the CVD method. In addition, it can be formed very easily with good workability.

Embodiment 2. FIG.
In the first embodiment, dry etching is used in the pn separation step. In the second embodiment, a method for improving the productivity of the dry etching process will be described. 6A and 6B are process cross-sectional schematic diagrams showing a pn separation process step in the manufacturing process of the solar cell according to the second embodiment. In the present embodiment, a plurality of p-type single crystal silicon substrates 1 each having an n-type diffusion layer 2 that functions as a solar cell substrate are stacked, not one by one, to form a stack structure, Dry etching is performed on the structure.

  That is, the p-type single crystal silicon substrate 1 in which the diffusion processing step S30 for forming the n-type diffusion layer 2 in Embodiment 1 is performed is arranged so that the light receiving surface side is inward as shown in FIG. Then, the stack structure is formed by stacking so as not to be exposed to the outside of the stack structure. The steps up to the pn separation processing step are the same as those in the first embodiment shown in steps S10 to S30 in FIG. 2 and FIGS.

  As shown in FIG. 6A, dry etching is performed in a state of a stack structure, and the n-type diffusion layer 2 on the side surface is removed by etching. As described above, pn isolation is performed by removing the n-type diffusion layer 2 on the side surface by dry etching (pn isolation processing step). In the dry etching process, the outermost p-type single crystal silicon substrate 1 is supported and protected by a substrate holder (not shown), so that only the n-type diffusion layer 2 on the side surface is provided as shown in FIG. Can be removed by etching. At this time, by using the RIE method which is an anisotropic etching method, only the exposed side surface is selectively removed by etching, and the etching wraparound inside is suppressed, so that the n-type diffusion layer 2 on the light receiving surface side is suppressed. Can be prevented from being etched. In addition, even if etching gas may flow from the gap between the substrate holders, the stack structure is laminated so that the outermost surface of the stack structure is on the back surface 1B side of the p-type single crystal silicon substrate 1. Etching of the n-type diffusion layer 2 on the light receiving surface side can be suppressed.

  According to the present embodiment, by stacking a plurality of p-type single crystal silicon substrates 1 on which the n-type diffusion layer 2 is formed, forming a stack structure, and performing dry etching as the stack structure, It becomes extremely easy and easy to work, and a plurality of pn separations can be realized collectively.

  Further, the method of this embodiment does not require a mask for etching, and a relatively inexpensive apparatus can be selected as compared with a wet etching process using a chemical solution. Further, there is an effect that the surface is less rough than the pn separation step by a blasting method or a physical method using a laser.

Embodiment 3 FIG.
In the first embodiment, dry etching is used for the pn separation step, but wet etching may be used. In the third embodiment, the n-type diffusion layer 2 on the side surface 1C of the p-type single crystal silicon substrate 1 is removed by wet etching. Also in this case, all the steps other than the pn separation step S40 may be performed in the same manner as in the first embodiment.

  When wet etching is used, the n-type diffusion layer 2 from the side surface to the peripheral edge of the back surface is efficiently etched and removed by the wraparound of the etching, and the n-type diffusion layer 2 at the peripheral portion on the back surface 1B side is easily removed. For this reason, the increase in the dark current Id is not large as in the case where the pn separation is performed by dry etching as in the first embodiment. However, also in the case of the third embodiment, if the antireflection film formed on the upper layer of the n-type diffusion layer 2 is conductive, the increase in the dark current Id increases the thickness of the silicon nitride film constituting the antireflection film. By setting the thickness to 55 nm to 60 nm, an increase in dark current can be suppressed and a solar cell with a high FF can be obtained.

Embodiment 4 FIG.
The fourth embodiment is characterized in that RIE (reactive ion etching) is used for the pn separation step S40. Also in this case, all the steps other than the pn separation step S40 may be performed in the same manner as in the first embodiment.

  When RIE is used, the n-type diffusion layer 2 on the side surface 1C is efficiently removed by etching, but the etching hardly wraps around to the back surface, so that the n-type diffusion layer 2 on the back surface 1B side reliably remains to the edge of the substrate. doing. Thereby, if the antireflection film 3 formed on the upper layer of the n-type diffusion layer 2 is conductive, the increase in the dark current Id cannot be avoided, but the thickness of the silicon nitride film constituting the antireflection film 3 is 55 nm. By setting the thickness to ˜60 nm, an increase in dark current can be suppressed and a solar cell with a high FF can be obtained.

  Note that the semiconductor substrate constituting the solar cell is not limited to the p-type single crystal silicon substrate used in Embodiments 1 to 4, but may be n-type, or a crystal system such as single crystal silicon or polycrystalline silicon. A crystalline semiconductor substrate such as a silicon substrate can be used. In many cases, the semiconductor substrate used here is a rectangular flat plate that has been subjected to corner processing with, for example, a side of about 150 mm to 160 mm and a thickness of about 150 μm to 250 μm. On the outer peripheral surface of the semiconductor substrate, p-type silicon and n-type silicon are joined to form a pn junction region. That is, the pn junction is provided along the outer peripheral surface of the p-type single crystal silicon substrate 1 which is a semiconductor substrate, and is provided from the light receiving surface 1A to the outer peripheral portions of the side surface 1C and the back surface 1B. In the embodiment, the light-receiving surface electrode formed on the light-receiving surface side of the p-type single crystal silicon substrate is composed of finger electrodes 4 arranged in parallel and bus electrodes 5 orthogonal to the finger electrodes 4. However, the finger electrode is sometimes called a grid electrode, and the shape can be changed as appropriate. Also, the number and position of the bus electrodes can be changed as appropriate, and the bus electrodes may not be formed. Also, the configuration or structure of the electrodes can be changed as appropriate.

  Furthermore, in the embodiment, the case where the n-type diffusion layer is formed on the entire surface of the p-type single crystal silicon substrate 1 has been described. However, in the diffusion process, diffusion to the back surface or the side surface is performed with a shielding jig such as a substrate holder. Even when the n-type diffusion layer is formed while suppressing, impurity diffusion slightly occurs, and the formation of the n-type diffusion layer on the back surface or side surface may be unavoidable. Even when the n-type diffusion layer is formed on the back surface or side surface unintentionally in this way, the deterioration of characteristics can be suppressed by setting the thickness of the silicon nitride film in the range of 55 nm to 60 nm. Is possible.

  Further, the CVD method for forming the silicon nitride film is not limited to the plasma CVD method, and can be applied to general CVD methods such as an atmospheric pressure CVD method and a low pressure CVD method. However, in the case of the sputtering method, the occurrence of leak is not so much, and the present invention is considered to be a useful method in the case of film formation by the CVD method.

  Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments or modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 p-type single crystal silicon substrate, 1T texture, 1A light-receiving surface, 1B back surface, 1C side surface, 2 n-type diffusion layer, 3 antireflection film, 4 finger electrode, 5 bus electrode, 6 BSF layer, 7 back surface collecting electrode, 8 Output extraction electrode, 10 solar cell.

Claims (5)

A second conductivity type impurity is diffused into a crystalline semiconductor substrate having a first conductivity type having a first main surface as a light receiving surface and a second main surface opposite to the first main surface. Forming a two-conductivity-type semiconductor layer;
A pn isolation treatment step of removing the second conductivity type semiconductor layer on a side surface located between the first main surface and the second main surface and separating the regions into first and second conductivity types;
Forming a silicon nitride film so as to reach the side surface from the first main surface of the semiconductor substrate by a CVD method,
The step of forming the silicon nitride film is a method of manufacturing a solar cell, which is a step of forming a film with a film thickness in the range of 55 nm to 60 nm.   The method for manufacturing a solar cell according to claim 1, wherein the pn separation treatment step is a dry etching step.   The method for manufacturing a solar cell according to claim 1, wherein the step of forming the silicon nitride film is a plasma CVD step. The pn separation process step includes
A step of forming a stack structure by laminating a plurality of the crystalline semiconductor substrates, the first main surface being the inside, and
The method for manufacturing a solar cell according to claim 1, further comprising: a step of etching a silicon nitride film on a side surface of the stack structure by dry etching. A crystalline semiconductor substrate having a first conductivity type having a first main surface which is a light-receiving surface and a second main surface opposite to the first main surface;
A second conductivity type semiconductor layer formed on a part of the first main surface and the second main surface excluding the side surface of the semiconductor substrate;
A solar cell including a silicon nitride film having a film thickness of 55 nm to 60 nm formed so as to reach the side surface from the first main surface of the semiconductor substrate.

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