WO2011048656A1 - Method for roughening substrate surface, and method for manufacturing photovoltaic device - Google Patents

Method for roughening substrate surface, and method for manufacturing photovoltaic device Download PDF

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WO2011048656A1
WO2011048656A1 PCT/JP2009/068028 JP2009068028W WO2011048656A1 WO 2011048656 A1 WO2011048656 A1 WO 2011048656A1 JP 2009068028 W JP2009068028 W JP 2009068028W WO 2011048656 A1 WO2011048656 A1 WO 2011048656A1
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substrate
roughening
etching
silicon
silicon substrate
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PCT/JP2009/068028
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French (fr)
Japanese (ja)
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濱本　哲
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三菱電機株式会社
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Publication of WO2011048656A1 publication Critical patent/WO2011048656A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

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  • the present invention relates to a substrate roughening method and a photovoltaic device manufacturing method, and more particularly to a substrate roughening method and a photovoltaic device capable of efficiently forming an uneven shape on the surface of a silicon substrate.
  • an antireflection film is formed on the light receiving surface side of the solar cell substrate to reduce the reflectance itself, and (3) the solar cell substrate A combination of two methods of forming a concavo-convex shape as a textured structure on the surface and effectively reducing the reflectivity by allowing the light once reflected to strike another surface again.
  • Etching to form a concavo-convex shape on the surface of a crystalline silicon substrate is performed by adding an additive such as isopropyl alcohol (hereinafter abbreviated as IPA) to an aqueous alkali hydroxide solution to increase the etching rate anisotropy with respect to the silicon surface orientation.
  • IPA isopropyl alcohol
  • This is performed by a mechanism in which a plane orientation with a relatively low etching rate is revealed as etching progresses (for example, see Patent Document 1).
  • azimuth planes having a low etching rate do not begin to appear at the same time from the beginning of the dissolution reaction. That is, at the initial stage of etching, uniform “isotropic high melting” proceeds, and small “nuclei” surrounded by azimuth planes with a stochastic slow etching rate are formed. As the etching progresses, the etching of the azimuth plane having a low etching rate progresses to grow the “nucleus”, and the “nucleus” overlaps with each other in a complex manner to finally form the uneven shape.
  • the azimuth plane with a slow etching rate is the (111) plane which is the most dense surface.
  • the “nucleus” portion shows a quadrangular pyramid shape like a pyramid. For this reason, there exists a tendency for the favorable uneven
  • an increase in the total etching amount leads to a decrease in the thickness of the silicon substrate and an increase in work materials and costs.
  • the present invention has been made in view of the above, and a substrate roughening method capable of efficiently forming a good uneven shape on the surface of the silicon substrate without damaging the silicon substrate, and The object is to obtain a photovoltaic device.
  • a method for roughening a substrate according to the present invention is a method for forming a texture structure on the surface of a silicon substrate by subjecting the silicon substrate to a surface treatment.
  • a mixed solution of an alkali hydroxide aqueous solution and an alcohol is used as an etching solution in an environment where the saturated vapor pressure of the alcohol is 200 mmHg or more and 600 mmHg or less with respect to the surface of the silicon-based substrate. It includes an unevenness forming step of forming fine unevenness on the surface of the silicon-based substrate by performing etching under a condition where the temperature of the etching solution is 55 ° C. or higher and 75 ° C. or lower.
  • the present invention it is possible to efficiently form a good concavo-convex shape on the surface of the silicon substrate without damaging the silicon substrate, with low environmental load and at low cost.
  • FIG. 1-1 is a cross-sectional view illustrating a schematic configuration of the solar battery cell according to the first embodiment of the present invention.
  • FIGS. 1-2 is principal part sectional drawing explaining the texture structure by the side of the light-receiving surface of the photovoltaic cell concerning Embodiment 1 of this invention.
  • FIGS. FIG. 1-3 is a top view showing a schematic configuration of the solar battery cell according to the first embodiment of the present invention.
  • 1-4 is a bottom view showing a schematic configuration of the solar battery cell according to the first embodiment of the present invention.
  • FIG. FIGS. 2-1 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • FIGS. FIGS. 2-5 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • FIGS. FIGS. 2-6 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • FIGS. FIGS. 2-5 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • FIGS. FIGS. 2-6 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention.
  • FIGS. FIG. 3 is a characteristic diagram showing the temperature dependence of the saturated vapor pressure of IPA.
  • FIG. 4 is a characteristic diagram showing the temperature dependence of the nucleation density in a certain area by etching.
  • FIG. 5 is a characteristic diagram showing the temperature dependence of the etching rate in the etching of a silicon substrate using an alkaline aqueous solution.
  • FIG. 6A is a schematic diagram for explaining the uneven shape forming step according to the embodiment of the present invention.
  • FIG. 6B is a schematic diagram for explaining the uneven shape forming step in the embodiment of the present invention.
  • FIG. 6C is a schematic diagram for explaining the uneven shape forming step in the embodiment of the present invention.
  • FIG. 7A is a schematic diagram for explaining a conventional uneven shape forming process.
  • FIG. 7B is a schematic diagram for explaining a conventional uneven shape forming process.
  • FIG. 7C is a schematic diagram for explaining a conventional uneven shape forming process.
  • FIG. 7D is a schematic diagram for explaining a conventional uneven shape forming process.
  • FIGS. 1-1 to 1-4 are diagrams showing a schematic configuration of a solar battery cell 1 manufactured by a method of manufacturing a photovoltaic device according to the present embodiment
  • FIG. 1 is a cross-sectional view of the battery cell 1
  • FIG. 1-2 is a cross-sectional view of a main part for explaining the texture structure on the light receiving surface side of the solar cell 1
  • FIG. 1-3 is a top view of the solar cell 1 viewed from the light receiving surface side.
  • 1-4 are bottom views of the solar battery cell 1 as viewed from the side opposite to the light receiving surface.
  • FIG. 1-1 is a cross-sectional view in the AA direction of FIG. 1-3.
  • the solar cell 1 is a solar cell substrate having a photoelectric conversion function and having a pn junction, and a light receiving surface side surface of the semiconductor substrate 11
  • An antireflection film 17 formed on the (front surface) to prevent reflection of incident light on the light receiving surface; and a back surface side electrode 19 formed on a surface (back surface) opposite to the light receiving surface of the semiconductor substrate 11;
  • a light receiving surface side electrode 21 formed so as to penetrate the antireflection film 17 and contact the n-type impurity diffusion layer 15 on the light receiving surface side (front surface) of the semiconductor substrate 11.
  • the semiconductor substrate 11 includes a p-type (first conductivity type) polycrystalline silicon layer 13 and an n-type (second conductivity type) impurity diffusion layer 15 in which the conductivity type of the surface of the p-type polycrystalline silicon layer 13 is inverted. These constitute a pn junction.
  • fine irregularities are formed at a high density as a texture structure on the light receiving surface side surface of the semiconductor substrate 11 (n-type impurity diffusion layer 15).
  • the micro unevenness increases the area for absorbing light from the outside on the light receiving surface, suppresses the reflectance on the light receiving surface, and has a structure for confining light.
  • the back surface side electrode 19 is formed on the entire back surface of the semiconductor substrate 11.
  • the light receiving surface side electrode 21 includes a front silver grid electrode 23 and a front silver bus electrode 25 of the solar battery cell.
  • the front silver grid electrode 23 is locally provided on the light receiving surface in order to collect electricity generated by the semiconductor substrate 11.
  • the front silver bus electrode 25 is provided substantially orthogonal to the front silver grid electrode 23 in order to take out the electricity collected by the front silver grid electrode 23.
  • the solar cell 1 configured as described above, sunlight is irradiated from the light receiving surface side of the solar cell 1 to the pn junction surface of the semiconductor substrate 11 (the junction surface between the p-type polycrystalline silicon layer 13 and the n-type impurity diffusion layer 15). ), Holes and electrons are generated. Due to the electric field at the pn junction, the generated electrons move toward the n-type impurity diffusion layer 15 and the holes move toward the p-type polycrystalline silicon layer 13. As a result, electrons are excessive in the n-type impurity diffusion layer 15 and holes are excessive in the p-type polycrystalline silicon layer 13. As a result, photovoltaic power is generated.
  • This photovoltaic power is generated in the direction of biasing the pn junction in the forward direction, the light receiving surface side electrode 21 connected to the n-type impurity diffusion layer 15 becomes a negative electrode, and the back surface side electrode 19 connected to the p-type polycrystalline silicon layer 13. Becomes a positive pole, and current flows in an external circuit (not shown).
  • fine irregularities are formed at a high density as a texture structure on the surface of the semiconductor substrate 11 (n-type impurity diffusion layer 15) on the light receiving surface side. ing. Thereby, since the light reflected once hits another surface again, the reflectance at the light receiving surface can be suppressed, and the effect of confining the light in the solar battery cell 1 can be obtained more effectively. The amount of current generated is increased to improve the output characteristics.
  • a solar cell excellent in photoelectric conversion efficiency is realized by further improving the effect of confining light in the solar cell 1.
  • FIGS. 2-1 to 2-7 are cross-sectional views for explaining the manufacturing process of the solar battery cell 1 according to the present embodiment.
  • a p-type polycrystalline silicon substrate that is most frequently used for consumer solar cells is prepared (hereinafter referred to as p-type polycrystalline silicon substrate 11a) (FIG. 2-1).
  • the thickness and dimensions of the p-type polycrystalline silicon substrate 11a are not particularly limited, but in the present embodiment, as an example, the thickness of the p-type polycrystalline silicon substrate 11a is 200 ⁇ m and the dimensions are 150 mm ⁇ 150 mm.
  • the p-type polycrystalline silicon substrate 11a is manufactured by slicing an ingot formed by cooling and solidifying molten silicon with a wire saw, damage at the time of slicing remains on the surface (damage layer).
  • the damaged layer on the surface layer has extremely poor crystallinity and needs to be removed in order to sufficiently function as a semiconductor element. Therefore, the p-type polycrystalline silicon substrate 11a is first removed by immersing the surface of the p-type polycrystalline silicon substrate 11a in an acid or heated alkaline solution, for example, in an aqueous solution of sodium hydroxide, to etch the silicon substrate. Then, the damaged region existing near the surface of the p-type polycrystalline silicon substrate 11a is removed.
  • an alkali hydroxide aqueous solution such as an aqueous sodium hydroxide solution is used as the etching solution. More preferred.
  • the remaining damage layer appears mainly as a decrease in open circuit voltage (Voc) and fill factor (FF) in terms of the performance of the solar cell as a product.
  • the etching amount of the damaged layer is preferably 5 ⁇ m or more.
  • fine irregularities are formed as a texture structure on the light receiving surface side surface of the p-type polycrystalline silicon substrate 11a.
  • the formation of the texture structure is performed, for example, by etching the p-type polycrystalline silicon substrate 11a with an alkali hydroxide aqueous solution containing IPA.
  • the IPA temporarily adheres to the surface of the p-type polycrystalline silicon substrate 11a, inhibits the etching reaction, suppresses the etching rate, and promotes the appearance of the aforementioned nucleus 110.
  • An IPA concentration of a certain level or more is required for the role of promoting the appearance of the nucleus 110 to function effectively.
  • Table 1 shows changes in the short circuit current (Isc), which is one of the solar cell characteristics, with respect to the IPA concentration (wt%).
  • the IPA concentration (wt%) is an IPA concentration in an aqueous alkali hydroxide solution containing IPA which is an etching solution used in forming the texture structure.
  • the short-circuit current (Isc) is low because the formation of fine irregularities is not sufficient in the treatment with the IPA concentration of 1.8 wt% or less.
  • the lower limit of the IPA concentration is preferably 2.0 wt% or more, and more preferably 2.4 wt% or more.
  • the upper limit of the IPA concentration is practically 5 wt% or less from the viewpoint of preventing unnecessary consumption. However, it does not necessarily deny higher concentrations.
  • FIG. 3 is a characteristic diagram showing the temperature dependence of the saturated vapor pressure of IPA. As shown in FIG. 3, the vapor pressure increases as the temperature increases. For this reason, when the etching solution is high in temperature, the IPA in the etching solution is easily detached, and a large amount of IPA needs to be replenished in order to maintain an environment suitable for the formation of the nucleus 110, which is very difficult to control.
  • the temperature of the etching solution is low in terms of both cost and environmental load.
  • FIG. 4 is a characteristic diagram showing the temperature dependence of the nucleation density in a certain area by etching.
  • FIG. 4 shows the temperature of the etching solution and the nucleation density when an alkali hydroxide aqueous solution containing IPA is used as the etching solution when the etching time is 3 minutes and 10 minutes.
  • the density of the nuclei increases as the temperature of the etching solution decreases, and it tends to be generally stable when the temperature of the etching solution is 75 ° C. or lower.
  • the temperature of the etching solution is 75 ° C. or lower.
  • the size of the minute irregularities is preferably in the range of 1 to 5 ⁇ m.
  • the size of the micro unevenness is, for example, a crystal grain close to the (100) plane, and the size and height of each pyramid-shaped shape surrounded by the (111) plane which is the most dense surface. Is shown.
  • the required amount of etching can be performed within 10 minutes at the most, preferably within 5 minutes. .
  • an etching rate of at least 0.1 ⁇ m / min or more, preferably 0.2 ⁇ m / min or more is desired.
  • FIG. 5 is a characteristic diagram showing the temperature dependence of the etching rate in etching a silicon substrate using an alkaline aqueous solution.
  • FIG. 5 shows the relationship between the etching solution temperature and the etching rate when an alkaline aqueous solution having an IPA concentration of 3 wt% and a sodium hydroxide concentration of 3.2 wt% is used.
  • a liquid temperature of at least 55 ° C. or higher, preferably 65 ° C. or higher is preferable.
  • concentration of sodium hydroxide 1.5 wt% or more and 10 wt% or less is appropriate from the standpoint of maintaining the reaction rate-limiting concentration and practical consumption. However, other concentrations are not necessarily denied.
  • FIGS. 6-1 to 6-3 are schematic diagrams for explaining the uneven shape forming step in the present embodiment.
  • the p-type polycrystalline silicon substrate 11a (FIG. 6-1) from which the damaged layer has been removed has an IPA concentration of 3 wt% with respect to an aqueous sodium hydroxide solution having a concentration of 3.2 wt% and a temperature of 70 ° C.
  • Subsequent etching treatment is performed using an aqueous alkali solution added at%.
  • small nuclei 110 surrounded by azimuth planes with a low etching rate are stochastically developed while uniform silicon with high isotropy is initially dissolved.
  • FIGS. 7A to 7D are schematic views for explaining a conventional process for forming an uneven shape.
  • the p-type polycrystalline silicon substrate 31a from which the damaged layer has been removed is etched using an alkaline aqueous solution in which IPA is added at a concentration of 3 wt% to a sodium hydroxide aqueous solution at a concentration of 3.2 wt% and a temperature of 90 ° C.
  • IPA alkaline aqueous solution in which IPA is added at a concentration of 3 wt% to a sodium hydroxide aqueous solution at a concentration of 3.2 wt% and a temperature of 90 ° C.
  • uniform melting with high isotropic progresses, and small nuclei 110 surrounded by azimuth planes with a stochastically slow etching rate are formed (FIG. 7-1).
  • conditions for efficiently forming a good concavo-convex shape as in the case of the present embodiment are not set, so the nuclei 110 are formed at a high density as in the case of the present embodiment.
  • the nuclei 110 are formed at a
  • the etching of the azimuth plane having a low etching rate proceeds (FIG. 7-2), and the azimuth planes overlap at various places to finally form a concavo-convex shape (FIG. 7). 7-3).
  • the nuclei 110 are not formed at a high density at the initial stage of etching as in the case of the present embodiment, the density of the unevenness finally formed is also lower than that in the case of the present embodiment. Therefore, in the case of the texture structure formed by the conventional method, the effect of reducing the reflectance by the texture structure in the solar battery cell is less than that in the case of forming by the method of the present embodiment.
  • a larger amount of etching is required. As a result, the substrate thickness is further reduced and the risk of breakage is increased.
  • the p-type polycrystalline silicon substrate 11a having a textured surface with minute irregularities formed thereon is put into a thermal oxidation furnace and heated in an atmosphere of phosphorus (P) which is an n-type impurity. To do.
  • phosphorus (P) is diffused on the surface of the p-type polycrystalline silicon substrate 11a to form an n-type impurity diffusion layer 15 to form a semiconductor pn junction (FIG. 2-2).
  • FIG. 2-2 to FIG. 2-7 the description of minute irregularities is omitted.
  • the n-type impurity diffusion layer 15 is formed by heating the p-type polycrystalline silicon substrate 11a in a phosphorus oxychloride (POCl 3 ) gas atmosphere at a temperature of, for example, 800 ° C. to 850 ° C. Further, the diffusion of phosphorus (P) is controlled so that the sheet resistance of the n-type impurity diffusion layer 15 is 30 ⁇ / ⁇ to 80 ⁇ / ⁇ , preferably 40 ⁇ / ⁇ to 60 ⁇ / ⁇ .
  • a phosphorus oxychloride (POCl 3 ) gas atmosphere at a temperature of, for example, 800 ° C. to 850 ° C.
  • P phosphorus oxychloride
  • the phosphor glass layer mainly composed of glass is formed on the surface immediately after the formation of the n-type impurity diffusion layer 15, the phosphor glass layer is removed using a hydrofluoric acid solution or the like.
  • a silicon nitride film (SiN film) is formed as an antireflection film 17 on the light receiving surface side of the p-type polycrystalline silicon substrate 11a on which the n-type impurity diffusion layer 15 is formed in order to improve the photoelectric conversion efficiency ( Fig. 2-3).
  • a plasma CVD method is used, and a silicon nitride film is formed as the antireflection film 17 using a mixed gas of silane and ammonia.
  • the film thickness and refractive index of the antireflection film 17 are set to values that most suppress light reflection.
  • two or more films having different refractive indexes may be laminated.
  • a different film forming method such as a sputtering method may be used for forming the antireflection film 17.
  • a silicon oxide film may be formed as the antireflection film 17.
  • the removal of the n-type impurity diffusion layer 15 formed on the back surface of the p-type polycrystalline silicon substrate 11a is performed using, for example, a single-sided etching apparatus.
  • a method of using the antireflection film 17 as a mask material and immersing the entire p-type polycrystalline silicon substrate 11a in an etching solution may be used.
  • an alkaline aqueous solution such as sodium hydroxide or potassium hydroxide heated to room temperature to 95 ° C., preferably 50 ° C. to 70 ° C. is used.
  • a mixed aqueous solution of nitric acid and hydrofluoric acid may be used as the etching solution.
  • electrodes are formed by screen printing.
  • the back surface side electrode 19 is produced (before baking). That is, an aluminum paste 19a, which is an electrode material paste, is applied to the shape of the back surface side electrode 19 by screen printing on the back surface side of the semiconductor substrate 11 and dried (FIG. 2-5).
  • the light-receiving surface side electrode 21 is produced (before firing). That is, after applying the silver paste 21a, which is the light receiving surface side electrode material paste, to the shape of the front silver grid electrode 23 and the front silver bus electrode 25 on the antireflection film 17 that is the light receiving surface of the semiconductor substrate 11 by screen printing. The silver paste is dried (FIGS. 2-6).
  • the paste is baked to obtain the back surface side electrode 19, and the front silver grid electrode 23 and the front silver bus electrode 25 as the light receiving surface side electrode 21 (FIG. 2-7).
  • Firing is performed by selecting in the air atmosphere, for example, in the range of 750 to 850 ° C. The firing temperature is selected in consideration of the cell structure and paste type.
  • silver in the light receiving surface side electrode 21 penetrates the antireflection film 17, and the n-type impurity diffusion layer 15 and the light receiving surface side electrode 21 are electrically connected. Thereby, the n-type impurity diffusion layer 15 can obtain a good resistive junction with the light receiving surface side electrode 21.
  • the solar cell 1 according to the present embodiment shown in FIGS. 1-1 to 1-4 can be manufactured.
  • the order of arrangement of the paste, which is an electrode material, on the semiconductor substrate 11 may be switched between the light receiving surface side and the back surface side.
  • minute irregularities are formed at a high density as a texture structure on the surface of the semiconductor substrate 11 (n-type impurity diffusion layer 15) on the light receiving surface side.
  • the area which absorbs the light from the outside on the light receiving surface can be increased, the reflectance on the light receiving surface can be suppressed, and the effect of confining the light in the solar battery cell 1 can be obtained more effectively.
  • the output characteristics can be improved by increasing the amount of current obtained from the above.
  • a mixture of an alkali hydroxide aqueous solution and isopropyl alcohol as an etchant is used. Etching is performed under the condition that the solution temperature is 55 ° C. or higher and 75 ° C. or lower.
  • minute irregularities can be efficiently and densely formed on the light receiving surface side of the p-type polycrystalline silicon substrate 11a.
  • consumption of materials and power required for forming irregularities can be suppressed, and manufacturing costs and environmental loads can be reduced.
  • the effect of confining light in the solar cell 1 can be further improved, and a solar cell excellent in photoelectric conversion efficiency can be produced.
  • a mixed solution of an alkali hydroxide aqueous solution and isopropyl alcohol is used in order to efficiently form a favorable uneven shape on the surface of the silicon substrate without damaging the silicon substrate.
  • the present invention is applicable when a mixed solution of an alkali hydroxide aqueous solution and an alcohol is used as the mixed solution in an environment where the saturated vapor pressure of the alcohol is 200 mmHg or more and 600 mmHg or less. Can be obtained.
  • examples of such alcohol include ethanol and 1-propanol in addition to isopropyl alcohol.
  • the rate of alcohol removal from the mixture is high, and the silicon etching reaction is not stable.
  • the saturated vapor pressure of alcohol is less than 200 mmHg, there is no problem with the rate of alcohol release, but the reaction rate of the aqueous alkali hydroxide solution that is the mixing partner is too low.
  • the case where a p-type silicon substrate is used as the semiconductor substrate has been described.
  • the reverse conductivity type in which a p-type diffusion layer is formed using an n-type silicon substrate as the semiconductor substrate can also be obtained in solar cells.
  • the polycrystalline silicon substrate is used as the semiconductor substrate.
  • the above-described effects of the present invention can be obtained even when a single crystal silicon substrate is used as the semiconductor substrate.
  • the substrate thickness of the semiconductor substrate is 200 ⁇ m
  • a substrate thinned to about 50 ⁇ m can be used as long as the substrate can be self-held.
  • the size of the semiconductor substrate is 150 mm ⁇ 150 mm.
  • the above-described effect of the present invention is achieved. Needless to say, you can get it.
  • the method for roughening a substrate according to the present invention is useful for efficiently and densely forming minute irregularities on the surface of the substrate, and is particularly suitable for roughening a solar cell substrate. ing.

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Abstract

Disclosed is a method for roughening a substrate surface, wherein a texture structure is formed in the surface of a silicon substrate (11a) by subjecting the silicon substrate (11a) to a surface treatment. The method for roughening a substrate surface comprises a recesses/projections forming step wherein fine recesses and projections are formed in the surface of the silicon substrate (11a) by etching the surface of the silicon substrate (11a) using, as an etching liquid, a mixed solution of an aqueous alkali hydroxide solution and an alcohol in an environment where the saturated vapor pressure of the alcohol is not les than 200 mmHg but not more than 600 mmHg under a condition such that the temperature of the etching liquid is not less than 55˚C but not more than 75˚C.

Description

基板の粗面化方法、光起電力装置の製造方法Substrate roughening method and photovoltaic device manufacturing method
　本発明は、基板の粗面化方法および光起電力装置の製造方法に関し、シリコン系基板の表面に凹凸形状を効率良く形成することが可能な基板の粗面化方法および光起電力装置に関する。 The present invention relates to a substrate roughening method and a photovoltaic device manufacturing method, and more particularly to a substrate roughening method and a photovoltaic device capable of efficiently forming an uneven shape on the surface of a silicon substrate.
　例えば太陽電池においては、入射光を効率良く内部に取り込む為に、（１）太陽電池基板の受光面側に反射防止膜を形成して反射率自体を低減すること、（３）太陽電池基板の表面にテクスチャー構造として凹凸形状を形成し、一度反射した光が再度他の表面に当たるようにすることで反射率を実効的に低減すること、の２つの手法を組み合わせて実施している。 For example, in a solar cell, in order to capture incident light efficiently inside, (1) an antireflection film is formed on the light receiving surface side of the solar cell substrate to reduce the reflectance itself, and (3) the solar cell substrate A combination of two methods of forming a concavo-convex shape as a textured structure on the surface and effectively reducing the reflectivity by allowing the light once reflected to strike another surface again.
　このうち太陽電池基板の表面に凹凸形状を形成する方法としては、物理的研削や化学溶解反応などが用いられる。特に、太陽電池基板が結晶シリコン基板である場合は、水酸化アルカリ水溶液によるエッチング処理を用いることが多い。 Among these methods, physical grinding, chemical dissolution reaction, and the like are used as a method for forming an uneven shape on the surface of the solar cell substrate. In particular, when the solar cell substrate is a crystalline silicon substrate, etching with an aqueous alkali hydroxide solution is often used.
　結晶シリコン基板の表面に凹凸形状を形成するエッチングは、水酸化アルカリ水溶液にイソプロピルアルコール（以下、略称のＩＰＡで示す）等の添加剤を加えて、シリコンの面方位に対するエッチング速度の異方性を持たせ、エッチングの進行に伴って相対的にエッチング速度の遅い面方位を現出させる、というメカニズムにより行われる（たとえば、特許文献１参照）。 Etching to form a concavo-convex shape on the surface of a crystalline silicon substrate is performed by adding an additive such as isopropyl alcohol (hereinafter abbreviated as IPA) to an aqueous alkali hydroxide solution to increase the etching rate anisotropy with respect to the silicon surface orientation. This is performed by a mechanism in which a plane orientation with a relatively low etching rate is revealed as etching progresses (for example, see Patent Document 1).
特開２００９－８１４７０号公報JP 2009-81470 A
　しかしながら、上述したエッチングにおいては、実際には溶解反応の当初から一斉にエッチング速度の遅い方位面が現出し始めるのではない。すなわち、エッチングの初期においては、等方性の高い一様な溶解が進みながら、確率論的にエッチング速度の遅い方位面に囲まれた小さな「核」ができる。そして、エッチングの進行に従って、そのエッチング速度の遅い方位面のエッチングが進行して「核」が成長し、この「核」が各所で複合的に重なって、最終的に凹凸形状が形成される。 However, in the etching described above, in fact, azimuth planes having a low etching rate do not begin to appear at the same time from the beginning of the dissolution reaction. That is, at the initial stage of etching, uniform “isotropic high melting” proceeds, and small “nuclei” surrounded by azimuth planes with a stochastic slow etching rate are formed. As the etching progresses, the etching of the azimuth plane having a low etching rate progresses to grow the “nucleus”, and the “nucleus” overlaps with each other in a complex manner to finally form the uneven shape.
　シリコンの場合、エッチング速度の遅い方位面とは、最稠密面である（１１１）面である。そして、シリコンの結晶方位として典型的な（１００）面のシリコンの場合、「核」部分はピラミッドの様な４角錐の形状を現す。この為、エッチング総量を増やした方が、良好な凹凸形状が形成できる傾向がある。 In the case of silicon, the azimuth plane with a slow etching rate is the (111) plane which is the most dense surface. In the case of silicon having a typical (100) plane as the crystal orientation of silicon, the “nucleus” portion shows a quadrangular pyramid shape like a pyramid. For this reason, there exists a tendency for the favorable uneven | corrugated shape to be formed when the total etching amount is increased.
　その一方で、エッチング総量が増えることは、シリコン基板の板厚の減少、作業資材およびコストの増加に繋がる。特に近年は、シリコンウェハの薄板化が進んでいるため、シリコンウェハの破損等を防ぐ観点からは、エッチング総量を少なくすることが望ましい。したがって、現実的には、良好な凹凸形状の形成と、シリコンウェハの破損等の防止と、の両者のバランスを取ったエッチング量を設定することになる。 On the other hand, an increase in the total etching amount leads to a decrease in the thickness of the silicon substrate and an increase in work materials and costs. Particularly in recent years, since the thinning of the silicon wafer has progressed, it is desirable to reduce the total etching amount from the viewpoint of preventing the silicon wafer from being damaged. Therefore, in practice, an etching amount that balances both the formation of a good uneven shape and the prevention of breakage or the like of the silicon wafer is set.
　この際、「核」の形成能力が高くないと、エッチング総量を多く取らなければ十分な凹凸形状を形成できない。このため、十分な凹凸形状を得る為にウェハ破損のリスクを高めるか、凹凸形状が十分でないうちにエッチングを終えるかのバランスを取りづらくなり、効率的に良好な凹凸形状を形成することが難しいという問題が生じていた。 At this time, if the “nucleus” formation capability is not high, a sufficient uneven shape cannot be formed unless a large amount of etching is taken. For this reason, it is difficult to increase the risk of wafer breakage in order to obtain a sufficient uneven shape, or it is difficult to balance whether etching is completed before the uneven shape is sufficient, and it is difficult to efficiently form a good uneven shape. There was a problem.
　本発明は、上記に鑑みてなされたものであって、シリコン系基板を破損させることなく該シリコン系基板の表面に良好な凹凸形状を効率良く形成することが可能な基板の粗面化方法および光起電力装置を得ることを目的とする。 The present invention has been made in view of the above, and a substrate roughening method capable of efficiently forming a good uneven shape on the surface of the silicon substrate without damaging the silicon substrate, and The object is to obtain a photovoltaic device.
　上述した課題を解決し、目的を達成するために、本発明にかかる基板の粗面化方法は、シリコン系基板に表面処理を施すことにより前記シリコン系基板の表面にテクスチャー構造を形成する基板の粗面化方法であって、前記シリコン系基板の表面に対して、水酸化アルカリ水溶液とアルコールとの混合溶液を前記アルコールの飽和蒸気圧が２００ｍｍＨｇ以上６００ｍｍＨｇ以下の環境下でエッチング液として用いて、前記エッチング液の液温が５５℃以上７５℃以下の条件でエッチングを施すことにより、前記シリコン系基板の表面に微細凹凸を形成する凹凸形成工程を含むこと、を特徴とする。 In order to solve the above-described problems and achieve the object, a method for roughening a substrate according to the present invention is a method for forming a texture structure on the surface of a silicon substrate by subjecting the silicon substrate to a surface treatment. In the roughening method, a mixed solution of an alkali hydroxide aqueous solution and an alcohol is used as an etching solution in an environment where the saturated vapor pressure of the alcohol is 200 mmHg or more and 600 mmHg or less with respect to the surface of the silicon-based substrate. It includes an unevenness forming step of forming fine unevenness on the surface of the silicon-based substrate by performing etching under a condition where the temperature of the etching solution is 55 ° C. or higher and 75 ° C. or lower.
　本発明によれば、シリコン系基板を破損させることなく該シリコン系基板の表面に良好な凹凸形状を効率良く、低環境負荷かつ低コストで形成することが可能である、という効果を奏する。 According to the present invention, it is possible to efficiently form a good concavo-convex shape on the surface of the silicon substrate without damaging the silicon substrate, with low environmental load and at low cost.
図１－１は、本発明の実施の形態１にかかる太陽電池セルの概略構成を示す断面図である。FIG. 1-1 is a cross-sectional view illustrating a schematic configuration of the solar battery cell according to the first embodiment of the present invention. 図１－２は、本発明の実施の形態１にかかる太陽電池セルの受光面側のテクスチャー構造を説明する要部断面図である。FIGS. 1-2 is principal part sectional drawing explaining the texture structure by the side of the light-receiving surface of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図１－３は、本発明の実施の形態１にかかる太陽電池セルの概略構成を示す上面図である。FIG. 1-3 is a top view showing a schematic configuration of the solar battery cell according to the first embodiment of the present invention. 図１－４は、本発明の実施の形態１にかかる太陽電池セルの概略構成を示す下面図である。1-4 is a bottom view showing a schematic configuration of the solar battery cell according to the first embodiment of the present invention. FIG. 図２－１は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-1 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図２－２は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-2 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図２－３は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-3 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図２－４は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-4 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図２－５は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-5 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図２－６は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-6 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図２－７は、本発明の実施の形態１にかかる太陽電池セルの製造工程を説明するための断面図である。FIGS. 2-7 is sectional drawing for demonstrating the manufacturing process of the photovoltaic cell concerning Embodiment 1 of this invention. FIGS. 図３は、ＩＰＡの飽和蒸気圧の温度依存性を示す特性図である。FIG. 3 is a characteristic diagram showing the temperature dependence of the saturated vapor pressure of IPA. 図４は、エッチングによる一定面積における核形成密度の温度依存性を示す特性図である。FIG. 4 is a characteristic diagram showing the temperature dependence of the nucleation density in a certain area by etching. 図５は、アルカリ水溶液を用いたシリコン基板のエッチングにおけるエッチング速度の温度依存性を示す特性図である。FIG. 5 is a characteristic diagram showing the temperature dependence of the etching rate in the etching of a silicon substrate using an alkaline aqueous solution. 図６－１は、本発明の実施の形態における凹凸形状の形成工程を説明するための模式図である。FIG. 6A is a schematic diagram for explaining the uneven shape forming step according to the embodiment of the present invention. 図６－２は、本発明の実施の形態における凹凸形状の形成工程を説明するための模式図である。FIG. 6B is a schematic diagram for explaining the uneven shape forming step in the embodiment of the present invention. 図６－３は、本発明の実施の形態における凹凸形状の形成工程を説明するための模式図である。FIG. 6C is a schematic diagram for explaining the uneven shape forming step in the embodiment of the present invention. 図７－１は、従来の凹凸形状の形成工程を説明するための模式図である。FIG. 7A is a schematic diagram for explaining a conventional uneven shape forming process. 図７－２は、従来の凹凸形状の形成工程を説明するための模式図である。FIG. 7B is a schematic diagram for explaining a conventional uneven shape forming process. 図７－３は、従来の凹凸形状の形成工程を説明するための模式図である。FIG. 7C is a schematic diagram for explaining a conventional uneven shape forming process. 図７－４は、従来の凹凸形状の形成工程を説明するための模式図である。FIG. 7D is a schematic diagram for explaining a conventional uneven shape forming process.
　以下に、本発明にかかる基板の粗面化方法、光起電力装置の製造方法の実施の形態を図面に基づいて詳細に説明する。なお、本発明は以下の記述に限定されるものではなく、特に基板の粗面化方法と直接関係のない工程や構造に関しては、本発明の要旨を逸脱しない範囲において適宜変更可能である。また、以下に示す図面においては、理解の容易のため、各部材の縮尺が実際とは異なる場合がある。各図面間においても同様である。 Embodiments of a substrate roughening method and a photovoltaic device manufacturing method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the following description, and in particular, processes and structures not directly related to the substrate roughening method can be appropriately changed without departing from the gist of the present invention. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings.
実施の形態
　図１－１～図１－４は、本実施の形態にかかる光起電力装置の製造方法により作製した太陽電池セル１の概略構成を示す図であり、図１－１は、太陽電池セル１の断面図、図１－２は、太陽電池セル１の受光面側のテクスチャー構造を説明する要部断面図、図１－３は、受光面側からみた太陽電池セル１の上面図、図１－４は、受光面と反対側からみた太陽電池セル１の下面図である。図１－１は、図１－３のＡ－Ａ方向における断面図である。 Embodiments FIGS. 1-1 to 1-4 are diagrams showing a schematic configuration of a solar battery cell 1 manufactured by a method of manufacturing a photovoltaic device according to the present embodiment, and FIG. 1 is a cross-sectional view of the battery cell 1, FIG. 1-2 is a cross-sectional view of a main part for explaining the texture structure on the light receiving surface side of the solar cell 1, and FIG. 1-3 is a top view of the solar cell 1 viewed from the light receiving surface side. 1-4 are bottom views of the solar battery cell 1 as viewed from the side opposite to the light receiving surface. FIG. 1-1 is a cross-sectional view in the AA direction of FIG. 1-3.
　太陽電池セル１は、図１－１～図１－３に示されるように、光電変換機能を有する太陽電池基板であってｐｎ接合を有する半導体基板１１と、半導体基板１１の受光面側の面（おもて面）に形成されて受光面での入射光の反射を防止する反射防止膜１７と、半導体基板１１の受光面と反対側の面（裏面）に形成された裏面側電極１９と、半導体基板１１の受光面側の面（おもて面）において反射防止膜１７を貫通してｎ型不純物拡散層１５に接するように形成された受光面側電極２１と、を備える。 As shown in FIGS. 1-1 to 1-3, the solar cell 1 is a solar cell substrate having a photoelectric conversion function and having a pn junction, and a light receiving surface side surface of the semiconductor substrate 11 An antireflection film 17 formed on the (front surface) to prevent reflection of incident light on the light receiving surface; and a back surface side electrode 19 formed on a surface (back surface) opposite to the light receiving surface of the semiconductor substrate 11; And a light receiving surface side electrode 21 formed so as to penetrate the antireflection film 17 and contact the n-type impurity diffusion layer 15 on the light receiving surface side (front surface) of the semiconductor substrate 11.
　半導体基板１１は、ｐ型（第１の導電型）多結晶シリコン層１３と、該ｐ型多結晶シリコン層１３の表面の導電型が反転したｎ型（第２の導電型）不純物拡散層１５とを有し、これらによりｐｎ接合が構成されている。 The semiconductor substrate 11 includes a p-type (first conductivity type) polycrystalline silicon layer 13 and an n-type (second conductivity type) impurity diffusion layer 15 in which the conductivity type of the surface of the p-type polycrystalline silicon layer 13 is inverted. These constitute a pn junction.
　また、半導体基板１１（ｎ型不純物拡散層１５）の受光面側の表面には、テクスチャー構造として微小凹凸が高密度で形成されている。微小凹凸は、受光面において外部からの光を吸収する面積を増加し、受光面における反射率を抑え、光を閉じ込める構造となっている。 Also, fine irregularities are formed at a high density as a texture structure on the light receiving surface side surface of the semiconductor substrate 11 (n-type impurity diffusion layer 15). The micro unevenness increases the area for absorbing light from the outside on the light receiving surface, suppresses the reflectance on the light receiving surface, and has a structure for confining light.
　裏面側電極１９は、半導体基板１１の裏面の全面に形成されている。受光面側電極２１としては、太陽電池セルの表銀グリッド電極２３および表銀バス電極２５を含む。表銀グリッド電極２３は、半導体基板１１で発電された電気を集電するために受光面に局所的に設けられている。表銀バス電極２５は、表銀グリッド電極２３で集電された電気を取り出すために表銀グリッド電極２３にほぼ直交して設けられている。 The back surface side electrode 19 is formed on the entire back surface of the semiconductor substrate 11. The light receiving surface side electrode 21 includes a front silver grid electrode 23 and a front silver bus electrode 25 of the solar battery cell. The front silver grid electrode 23 is locally provided on the light receiving surface in order to collect electricity generated by the semiconductor substrate 11. The front silver bus electrode 25 is provided substantially orthogonal to the front silver grid electrode 23 in order to take out the electricity collected by the front silver grid electrode 23.
　このように構成された太陽電池セル１では、太陽光が太陽電池セル１の受光面側から半導体基板１１のｐｎ接合面（ｐ型多結晶シリコン層１３とｎ型不純物拡散層１５との接合面）に照射されると、ホールと電子が生成する。ｐｎ接合部の電界によって、生成した電子はｎ型不純物拡散層１５に向かって移動し、ホールはｐ型多結晶シリコン層１３に向かって移動する。これにより、ｎ型不純物拡散層１５に電子が過剰となり、ｐ型多結晶シリコン層１３にホールが過剰となる結果、光起電力が発生する。この光起電力はｐｎ接合を順方向にバイアスする向きに生じ、ｎ型不純物拡散層１５に接続した受光面側電極２１がマイナス極となり、ｐ型多結晶シリコン層１３に接続した裏面側電極１９がプラス極となって、図示しない外部回路に電流が流れる。 In the solar cell 1 configured as described above, sunlight is irradiated from the light receiving surface side of the solar cell 1 to the pn junction surface of the semiconductor substrate 11 (the junction surface between the p-type polycrystalline silicon layer 13 and the n-type impurity diffusion layer 15). ), Holes and electrons are generated. Due to the electric field at the pn junction, the generated electrons move toward the n-type impurity diffusion layer 15 and the holes move toward the p-type polycrystalline silicon layer 13. As a result, electrons are excessive in the n-type impurity diffusion layer 15 and holes are excessive in the p-type polycrystalline silicon layer 13. As a result, photovoltaic power is generated. This photovoltaic power is generated in the direction of biasing the pn junction in the forward direction, the light receiving surface side electrode 21 connected to the n-type impurity diffusion layer 15 becomes a negative electrode, and the back surface side electrode 19 connected to the p-type polycrystalline silicon layer 13. Becomes a positive pole, and current flows in an external circuit (not shown).
　以上のように構成された実施の形態にかかる太陽電池セル１においては、半導体基板１１（ｎ型不純物拡散層１５）の受光面側の表面には、テクスチャー構造として微小凹凸が高密度で形成されている。これにより、一度反射した光が再度他の表面に当たるようにして受光面における反射率を抑え、太陽電池セル１内に光を閉じ込める効果をより有効に得ることができるため、太陽電池セル１から得られる電流の量を増加させて、出力特性の向上が図られている。 In the solar battery cell 1 according to the embodiment configured as described above, fine irregularities are formed at a high density as a texture structure on the surface of the semiconductor substrate 11 (n-type impurity diffusion layer 15) on the light receiving surface side. ing. Thereby, since the light reflected once hits another surface again, the reflectance at the light receiving surface can be suppressed, and the effect of confining the light in the solar battery cell 1 can be obtained more effectively. The amount of current generated is increased to improve the output characteristics.
　したがって、実施の形態にかかる太陽電池セル１においては、太陽電池セル１内への光を閉じ込める効果をより向上させることで、光電変換効率に優れた太陽電池セルが実現されている。 Therefore, in the solar cell 1 according to the embodiment, a solar cell excellent in photoelectric conversion efficiency is realized by further improving the effect of confining light in the solar cell 1.
　つぎに、このような太陽電池セル１の製造方法の一例について図２－１～図２－７を参照して説明する。図２－１～図２－７は、本実施の形態にかかる太陽電池セル１の製造工程を説明するための断面図である。 Next, an example of a method for manufacturing such a solar battery cell 1 will be described with reference to FIGS. 2-1 to 2-7. FIGS. 2-1 to 2-7 are cross-sectional views for explaining the manufacturing process of the solar battery cell 1 according to the present embodiment.
　まず、半導体基板として、例えば民生用太陽電池向けとして最も多く使用されているｐ型多結晶シリコン基板を用意する（以下、ｐ型多結晶シリコン基板１１ａと呼ぶ）（図２－１）。ここで、ｐ型多結晶シリコン基板１１ａの厚さや寸法は特に限定されるものではないが、本実施の形態においては、一例としてｐ型多結晶シリコン基板１１ａの厚みは２００μｍ、寸法は１５０ｍｍ×１５０ｍｍとする。 First, as a semiconductor substrate, for example, a p-type polycrystalline silicon substrate that is most frequently used for consumer solar cells is prepared (hereinafter referred to as p-type polycrystalline silicon substrate 11a) (FIG. 2-1). Here, the thickness and dimensions of the p-type polycrystalline silicon substrate 11a are not particularly limited, but in the present embodiment, as an example, the thickness of the p-type polycrystalline silicon substrate 11a is 200 μm and the dimensions are 150 mm × 150 mm. And
　ｐ型多結晶シリコン基板１１ａは、溶融したシリコンを冷却固化してできたインゴットをワイヤーソーでスライスして製造するため、表面にスライス時のダメージが残っている（ダメージ層）。この表層のダメージ層は、結晶性が極めて悪く、半導体素子として十分に機能させる為には、除去する必要がある。そこで、まずはこのダメージ層の除去も兼ねて、ｐ型多結晶シリコン基板１１ａを酸または加熱したアルカリ溶液中、例えば水酸化ナトリウム水溶液に浸漬して表面をエッチングすることにより、シリコン基板の切り出し時に発生してｐ型多結晶シリコン基板１１ａの表面近くに存在するダメージ領域を取り除く。 Since the p-type polycrystalline silicon substrate 11a is manufactured by slicing an ingot formed by cooling and solidifying molten silicon with a wire saw, damage at the time of slicing remains on the surface (damage layer). The damaged layer on the surface layer has extremely poor crystallinity and needs to be removed in order to sufficiently function as a semiconductor element. Therefore, the p-type polycrystalline silicon substrate 11a is first removed by immersing the surface of the p-type polycrystalline silicon substrate 11a in an acid or heated alkaline solution, for example, in an aqueous solution of sodium hydroxide, to etch the silicon substrate. Then, the damaged region existing near the surface of the p-type polycrystalline silicon substrate 11a is removed.
　なお、他のエッチング液の可能性を否定するものではないが、処理の継続性や処理の容易さ等の観点から、エッチング液としては、水酸化ナトリウム水溶液等の水酸化アルカリ水溶液を用いることがより好ましい。 Although there is no denying the possibility of other etching solutions, from the viewpoint of continuity of processing and ease of processing, an alkali hydroxide aqueous solution such as an aqueous sodium hydroxide solution is used as the etching solution. More preferred.
　ダメージ層の残存は、製品である太陽電池の性能面では、主に開放電圧（Ｖｏｃ）や曲線因子（Ｆ．Ｆ．）の低下として現れる。ダメージ層の残存に起因した影響が太陽電池の性能へ出ないようにするためには、ダメージ層のエッチング量として、５μｍ以上のエッチング量が好ましい。 The remaining damage layer appears mainly as a decrease in open circuit voltage (Voc) and fill factor (FF) in terms of the performance of the solar cell as a product. In order to prevent the influence caused by the remaining damage layer from affecting the performance of the solar cell, the etching amount of the damaged layer is preferably 5 μm or more.
　また、ダメージ層の除去に続いて、ｐ型多結晶シリコン基板１１ａの受光面側の表面にテクスチャー構造として微小凹凸を形成する。このようなテクスチャー構造をｐ型多結晶シリコン基板１１ａの受光面側に設けることで、太陽電池セル１の表面側で光の多重反射を生じさせ、太陽電池セル１に入射する光を効率的に半導体基板１１の内部に吸収させることができ、実効的に反射率を低減して変換効率を向上させることができる。 Further, following the removal of the damaged layer, fine irregularities are formed as a texture structure on the light receiving surface side surface of the p-type polycrystalline silicon substrate 11a. By providing such a texture structure on the light receiving surface side of the p-type polycrystalline silicon substrate 11a, multiple reflections of light are generated on the surface side of the solar cell 1, and light incident on the solar cell 1 is efficiently transmitted. It can be absorbed inside the semiconductor substrate 11, and the reflectance can be effectively reduced and the conversion efficiency can be improved.
　テクスチャー構造の形成は、例えばｐ型多結晶シリコン基板１１ａを、ＩＰＡを含有させた水酸化アルカリ水溶液によりエッチングすることで行う。この工程において、ＩＰＡはｐ型多結晶シリコン基板１１ａの表面に一時的に付着してエッチング反応を阻害してエッチング速度を抑制するとともに、前述の核１１０の出現を促進する役割を有する。この核１１０出現の促進の役割を有効に機能させるには、一定以上のＩＰＡ濃度を要する。 The formation of the texture structure is performed, for example, by etching the p-type polycrystalline silicon substrate 11a with an alkali hydroxide aqueous solution containing IPA. In this step, the IPA temporarily adheres to the surface of the p-type polycrystalline silicon substrate 11a, inhibits the etching reaction, suppresses the etching rate, and promotes the appearance of the aforementioned nucleus 110. An IPA concentration of a certain level or more is required for the role of promoting the appearance of the nucleus 110 to function effectively.
　表１に、太陽電池特性の一つである短絡電流（Ｉｓｃ）のＩＰＡ濃度（ｗｔ％）に対する変化を示す。ここで、ＩＰＡ濃度（ｗｔ％）は、テクスチャー構造の形成の際に用いるエッチング液であるＩＰＡを含有させた水酸化アルカリ水溶液中におけるＩＰＡ濃度である。 Table 1 shows changes in the short circuit current (Isc), which is one of the solar cell characteristics, with respect to the IPA concentration (wt%). Here, the IPA concentration (wt%) is an IPA concentration in an aqueous alkali hydroxide solution containing IPA which is an etching solution used in forming the texture structure.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１より、ＩＰＡ濃度が１．８ｗｔ％以下の処理では微小凹凸の形成が十分でない為、短絡電流（Ｉｓｃ）が低いことが分かる。このことから、ＩＰＡ濃度の下限は、２．０ｗｔ％以上が好ましく、より好ましくは２．４ｗｔ％以上である。なお、ＩＰＡ濃度の上限については、実用上、無用な消費を防ぐ意味から、５ｗｔ％以下が妥当である。ただし、必ずしも、それ以上の濃度を否定するものではない。 From Table 1, it can be seen that the short-circuit current (Isc) is low because the formation of fine irregularities is not sufficient in the treatment with the IPA concentration of 1.8 wt% or less. For this reason, the lower limit of the IPA concentration is preferably 2.0 wt% or more, and more preferably 2.4 wt% or more. Note that the upper limit of the IPA concentration is practically 5 wt% or less from the viewpoint of preventing unnecessary consumption. However, it does not necessarily deny higher concentrations.
　一方、ＩＰＡは高い揮発性を有する物質であり、特に、高い温度ではそれが顕著である。図３は、ＩＰＡの飽和蒸気圧の温度依存性を示す特性図である。図３に示されるように、温度が高くなるに従って蒸気圧は高くなる。このため、エッチング液が高温の場合はエッチング液中のＩＰＡが離脱しやすく、核１１０の形成に適した環境を保つには大量のＩＰＡの補充を要し、制御が非常に難しい。 On the other hand, IPA is a highly volatile substance, and it is particularly noticeable at high temperatures. FIG. 3 is a characteristic diagram showing the temperature dependence of the saturated vapor pressure of IPA. As shown in FIG. 3, the vapor pressure increases as the temperature increases. For this reason, when the etching solution is high in temperature, the IPA in the etching solution is easily detached, and a large amount of IPA needs to be replenished in order to maintain an environment suitable for the formation of the nucleus 110, which is very difficult to control.
　エッチング液の温度を低くすることにより、エッチング液中のＩＰＡ濃度を制御しやすくなり、核１１０の形成に適した環境を保ち易く、ＩＰＡの補充も少なくて済む。したがって、コストと環境負荷の両面でエッチング液の液温は低い方が好ましい。 By lowering the temperature of the etching solution, the IPA concentration in the etching solution can be easily controlled, an environment suitable for the formation of the nucleus 110 can be easily maintained, and the replenishment of IPA can be reduced. Therefore, it is preferable that the temperature of the etching solution is low in terms of both cost and environmental load.
　上記の検証、即ちＩＰＡによる微小凹凸の形成能力の良否は、核の密度で測ると良い。図４は、エッチングによる一定面積における核形成密度の温度依存性を示す特性図である。図４では、エッチング時間が３分と１０分との場合について、エッチング液としてＩＰＡを含有させた水酸化アルカリ水溶液を用いた場合におけるエッチング液の温度と核形成密度とを示している。上述の通り、エッチング時間が３分と１０分の場合とも、エッチング液の温度低下に伴って核の密度が高くなっており、エッチング液の温度が７５℃以下の条件では概ね安定傾向にある。これは、エッチング液の温度低下に伴ってＩＰＡの離脱が減少し、７５℃以下では、実用上、影響を無視できる程度まで離脱が減少している為である。したがって、ＩＰＡによる良好な核形成能力を保持するためには、エッチング液の液温を７５℃以下とすることが好ましい。 The quality of the above verification, that is, the ability to form minute irregularities by IPA may be measured by the density of the nucleus. FIG. 4 is a characteristic diagram showing the temperature dependence of the nucleation density in a certain area by etching. FIG. 4 shows the temperature of the etching solution and the nucleation density when an alkali hydroxide aqueous solution containing IPA is used as the etching solution when the etching time is 3 minutes and 10 minutes. As described above, when the etching time is 3 minutes and 10 minutes, the density of the nuclei increases as the temperature of the etching solution decreases, and it tends to be generally stable when the temperature of the etching solution is 75 ° C. or lower. This is because the IPA detachment decreases as the temperature of the etching solution decreases, and at 75 ° C. or less, the detachment decreases to a practically negligible level. Therefore, in order to maintain a good nucleation ability by IPA, it is preferable that the temperature of the etching solution is 75 ° C. or lower.
　ただし、実用上は、できるだけ短い時間でエッチング処理を行う必要もある為、エッチング液の液温は、ある程度の高い温度も必要である。入射光を効率良くシリコン内部に取り込む為には、微小凹凸の大きさは１～５μｍの範囲にあることが好ましい。ここで、微小凹凸の大きさとは、（１００）面に近い結晶粒を例に取れば、最稠密面である（１１１）面に囲まれた、ピラミッド状の形状一つ一つの大きさや高さを示している。この大きさの微小凹凸を形成するためには、少なくとも同程度のエッチング量を必要とし、生産性を考慮すると、長くとも１０分以内、好ましくは５分以内に必要量のエッチングを行えることが望ましい。したがって、少なくとも０．１μｍ／分以上、できれば０．２μｍ／分以上のエッチング速度が望まれる。上記の条件をうまくバランスさせることにより、良好な凹凸形状を効率良く形成できる条件が設定される。 However, in practice, since it is necessary to perform the etching process in as short a time as possible, the temperature of the etching solution needs to be high to some extent. In order to efficiently take incident light into the silicon, the size of the minute irregularities is preferably in the range of 1 to 5 μm. Here, the size of the micro unevenness is, for example, a crystal grain close to the (100) plane, and the size and height of each pyramid-shaped shape surrounded by the (111) plane which is the most dense surface. Is shown. In order to form minute irregularities of this size, at least the same amount of etching is required, and considering productivity, it is desirable that the required amount of etching can be performed within 10 minutes at the most, preferably within 5 minutes. . Therefore, an etching rate of at least 0.1 μm / min or more, preferably 0.2 μm / min or more is desired. By properly balancing the above conditions, conditions are set that allow efficient formation of a good concavo-convex shape.
　図５は、アルカリ水溶液を用いたシリコン基板のエッチングにおけるエッチング速度の温度依存性を示す特性図である。図５では、ＩＰＡ濃度３ｗｔ％、水酸化ナトリウム濃度３．２ｗｔ％のアルカリ水溶液を用いた場合のエッチング液の温度とエッチング速度との関係を示している。図５から、上記の必要エッチング速度に対応する温度を求めると、少なくとも５５℃以上、できれば６５℃以上の液温が好ましい。水酸化ナトリウムの濃度については、反応律速の濃度維持と実用上の消費妥当性から、１．５ｗｔ％以上１０ｗｔ％以下が妥当である。ただし、必ずしも、これ以外の濃度を否定するものではない。以上の条件をうまくバランスさせることにより、良好な凹凸形状を効率良く形成できる条件が設定される。 FIG. 5 is a characteristic diagram showing the temperature dependence of the etching rate in etching a silicon substrate using an alkaline aqueous solution. FIG. 5 shows the relationship between the etching solution temperature and the etching rate when an alkaline aqueous solution having an IPA concentration of 3 wt% and a sodium hydroxide concentration of 3.2 wt% is used. When the temperature corresponding to the required etching rate is obtained from FIG. 5, a liquid temperature of at least 55 ° C. or higher, preferably 65 ° C. or higher is preferable. As for the concentration of sodium hydroxide, 1.5 wt% or more and 10 wt% or less is appropriate from the standpoint of maintaining the reaction rate-limiting concentration and practical consumption. However, other concentrations are not necessarily denied. By properly balancing the above conditions, conditions that can efficiently form a good concavo-convex shape are set.
　図６－１～図６－３は、本実施の形態における凹凸形状の形成工程を説明するための模式図である。本実施の形態では、ダメージ層を除去したｐ型多結晶シリコン基板１１ａ（図６－１）に対して、例えば濃度３．２ｗｔ％、温度７０℃の水酸化ナトリウム水溶液に対してＩＰＡを濃度３ｗｔ％で添加したアルカリ水溶液を用いて、引き続きのエッチング処理を行う。このようなアルカリ水溶液を用いてエッチングを行うことにより、初期には等方性の高い一様なシリコンの溶解が進みながら、確率論的にエッチング速度の遅い方位面に囲まれた小さな核１１０が高い密度でｐ型多結晶シリコン基板１１ａの表面に形成される。したがって、平坦部１１１が比較的少ない凹凸形状が形成される（図６－２）。そして、さらにエッチングが進行することで、エッチング速度の遅い方位面のエッチングが進行し、それが各所で複合的に重なって、平坦部が少なく、より多くの凹凸が形成された密度の高いテクスチャー構造がｐ型多結晶シリコン基板１１ａの表面に形成される（図６－３）。これにより、後述する反射防止膜と合わせて、入射光を効率的に半導体基板１１内部に吸収させる為の構造を形成することができる。 FIGS. 6-1 to 6-3 are schematic diagrams for explaining the uneven shape forming step in the present embodiment. In the present embodiment, for example, the p-type polycrystalline silicon substrate 11a (FIG. 6-1) from which the damaged layer has been removed has an IPA concentration of 3 wt% with respect to an aqueous sodium hydroxide solution having a concentration of 3.2 wt% and a temperature of 70 ° C. Subsequent etching treatment is performed using an aqueous alkali solution added at%. By performing etching using such an alkaline aqueous solution, small nuclei 110 surrounded by azimuth planes with a low etching rate are stochastically developed while uniform silicon with high isotropy is initially dissolved. It is formed on the surface of p-type polycrystalline silicon substrate 11a with a high density. Therefore, an uneven shape with relatively few flat portions 111 is formed (FIG. 6-2). As the etching progresses further, the etching of the azimuth plane with a slow etching rate progresses, and it overlaps with each other in a complex manner, and there are few flat parts and more uneven textures are formed. Is formed on the surface of the p-type polycrystalline silicon substrate 11a (FIG. 6-3). Accordingly, a structure for efficiently absorbing incident light into the semiconductor substrate 11 can be formed together with an antireflection film described later.
　従来との比較のために、従来の凹凸形状の形成工程について図７－１～図７－４を参照して説明する。図７－１～図７－４は、従来の凹凸形状の形成工程を説明するための模式図である。 For comparison with the prior art, a conventional uneven shape forming process will be described with reference to FIGS. 7-1 to 7-4. FIGS. 7A to 7D are schematic views for explaining a conventional process for forming an uneven shape.
　ダメージ層を除去したｐ型多結晶シリコン基板３１ａに対して、例えば濃度３．２ｗｔ％、温度９０℃の水酸化ナトリウム水溶液に対してＩＰＡを濃度３ｗｔ％で添加したアルカリ水溶液を用いてエッチング処理を行う。初期には等方性の高い一様な溶解が進みながら、確率論的にエッチング速度の遅い方位面に囲まれた小さな核１１０ができる（図７－１）。ここで、従来の方法では、本実施の形態の場合のように良好な凹凸形状を効率良く形成できる条件が設定されていないため、本実施の形態の場合のように核１１０が高い密度で形成されない。 For example, the p-type polycrystalline silicon substrate 31a from which the damaged layer has been removed is etched using an alkaline aqueous solution in which IPA is added at a concentration of 3 wt% to a sodium hydroxide aqueous solution at a concentration of 3.2 wt% and a temperature of 90 ° C. Do. Initially, uniform melting with high isotropic progresses, and small nuclei 110 surrounded by azimuth planes with a stochastically slow etching rate are formed (FIG. 7-1). Here, in the conventional method, conditions for efficiently forming a good concavo-convex shape as in the case of the present embodiment are not set, so the nuclei 110 are formed at a high density as in the case of the present embodiment. Not.
　そして、エッチングの進行にしたがって、エッチング速度の遅い方位面のエッチングが進行し（図７－２）、さらにその方位面が各所で複合的に重なって、最終的に凹凸形状が形成される（図７－３）。しかしながら、本実施の形態の場合のようにエッチングの初期において核１１０が高い密度で形成されていないため、最終的に形成される凹凸の密度も本実施の形態の場合と比較して低くなる。したがって、従来の方法で形成したテクスチャー構造の場合は、本実施の形態の方法で形成した場合と比較して、太陽電池セルにおけるテクスチャー構造による反射率の低減効果が少ない。或いは、十分な反射率低減効果を得るために、より多くのエッチング量を要し、結果、基板厚さが一層薄くなって、破損リスクを高めてしまう。 As the etching progresses, the etching of the azimuth plane having a low etching rate proceeds (FIG. 7-2), and the azimuth planes overlap at various places to finally form a concavo-convex shape (FIG. 7). 7-3). However, since the nuclei 110 are not formed at a high density at the initial stage of etching as in the case of the present embodiment, the density of the unevenness finally formed is also lower than that in the case of the present embodiment. Therefore, in the case of the texture structure formed by the conventional method, the effect of reducing the reflectance by the texture structure in the solar battery cell is less than that in the case of forming by the method of the present embodiment. Alternatively, in order to obtain a sufficient reflectivity reduction effect, a larger amount of etching is required. As a result, the substrate thickness is further reduced and the risk of breakage is increased.
　つぎに図２－２に戻り、テクスチャー構造として表面に微小凹凸が形成されたｐ型多結晶シリコン基板１１ａを熱酸化炉へ投入し、ｎ型の不純物であるリン（Ｐ）の雰囲気下で加熱する。この工程によりｐ型多結晶シリコン基板１１ａの表面にリン（Ｐ）を拡散させて、ｎ型不純物拡散層１５を形成して半導体ｐｎ接合を形成する（図２－２）。なお、図２－２～図２－７においては、微小凹凸の記載は省略している。本実施の形態では、ｐ型多結晶シリコン基板１１ａをオキシ塩化リン（ＰＯＣｌ３）ガス雰囲気中において、例えば８００℃～８５０℃の温度で加熱することにより、ｎ型不純物拡散層１５を形成する。また、ｎ型不純物拡散層１５のシート抵抗が３０Ω／□～８０Ω／□、好ましくは４０Ω／□～６０Ω／□となるようにリン（Ｐ）を拡散を制御する。 Next, returning to FIG. 2-2, the p-type polycrystalline silicon substrate 11a having a textured surface with minute irregularities formed thereon is put into a thermal oxidation furnace and heated in an atmosphere of phosphorus (P) which is an n-type impurity. To do. Through this step, phosphorus (P) is diffused on the surface of the p-type polycrystalline silicon substrate 11a to form an n-type impurity diffusion layer 15 to form a semiconductor pn junction (FIG. 2-2). In FIG. 2-2 to FIG. 2-7, the description of minute irregularities is omitted. In the present embodiment, the n-type impurity diffusion layer 15 is formed by heating the p-type polycrystalline silicon substrate 11a in a phosphorus oxychloride (POCl 3 ) gas atmosphere at a temperature of, for example, 800 ° C. to 850 ° C. Further, the diffusion of phosphorus (P) is controlled so that the sheet resistance of the n-type impurity diffusion layer 15 is 30Ω / □ to 80Ω / □, preferably 40Ω / □ to 60Ω / □.
　ここで、ｎ型不純物拡散層１５の形成直後の表面にはガラスを主成分とするリンガラス層が形成されているため、該リンガラス層をフッ酸溶液等を用いて除去する。 Here, since the phosphor glass layer mainly composed of glass is formed on the surface immediately after the formation of the n-type impurity diffusion layer 15, the phosphor glass layer is removed using a hydrofluoric acid solution or the like.
　つぎに、ｎ型不純物拡散層１５を形成したｐ型多結晶シリコン基板１１ａの受光面側に、光電変換効率改善のために、反射防止膜１７として例えばシリコン窒化膜（ＳｉＮ膜）を形成する（図２－３）。反射防止膜１７の形成には、例えばプラズマＣＶＤ法を使用し、シランとアンモニアの混合ガスを用いて反射防止膜１７としてシリコン窒化膜を形成する。反射防止膜１７の膜厚および屈折率は、光反射を最も抑制する値に設定する。なお、反射防止膜１７として、屈折率の異なる２層以上の膜を積層してもよい。また、反射防止膜１７の形成には、スパッタリング法などの異なる成膜方法を用いてもよい。また、反射防止膜１７としてシリコン酸化膜を形成してもよい。 Next, for example, a silicon nitride film (SiN film) is formed as an antireflection film 17 on the light receiving surface side of the p-type polycrystalline silicon substrate 11a on which the n-type impurity diffusion layer 15 is formed in order to improve the photoelectric conversion efficiency ( Fig. 2-3). For the formation of the antireflection film 17, for example, a plasma CVD method is used, and a silicon nitride film is formed as the antireflection film 17 using a mixed gas of silane and ammonia. The film thickness and refractive index of the antireflection film 17 are set to values that most suppress light reflection. As the antireflection film 17, two or more films having different refractive indexes may be laminated. In addition, a different film forming method such as a sputtering method may be used for forming the antireflection film 17. A silicon oxide film may be formed as the antireflection film 17.
　つぎに、リン（Ｐ）の拡散によりｐ型多結晶シリコン基板１１ａの裏面に形成されたｎ型不純物拡散層１５を除去する。これにより、第１導電型層であるｐ型多結晶シリコン層１３と、該ｐ型多結晶シリコン層１３の受光面側に形成された第２導電型層であるｎ型不純物拡散層１５と、によりｐｎ接合が構成された半導体基板１１が得られる（図２－４）。 Next, the n-type impurity diffusion layer 15 formed on the back surface of the p-type polycrystalline silicon substrate 11a is removed by diffusion of phosphorus (P). Thus, the p-type polycrystalline silicon layer 13 as the first conductivity type layer, the n-type impurity diffusion layer 15 as the second conductivity type layer formed on the light receiving surface side of the p-type polysilicon layer 13, Thus, a semiconductor substrate 11 having a pn junction is obtained (FIG. 2-4).
　ｐ型多結晶シリコン基板１１ａの裏面に形成されたｎ型不純物拡散層１５の除去は、例えば片面エッチング装置を用いて行う。または、反射防止膜１７をマスク材として活用し、エッチング液にｐ型多結晶シリコン基板１１ａの全体を浸漬させる方法を用いてもよい。エッチング液は、水酸化ナトリウム、水酸化カリウムなどのアルカリ水溶液を、室温～９５℃、好ましくは５０℃～７０℃に加熱したものを用いる。また、エッチング液として、硝酸とフッ酸との混合水溶液を用いてもよい。 The removal of the n-type impurity diffusion layer 15 formed on the back surface of the p-type polycrystalline silicon substrate 11a is performed using, for example, a single-sided etching apparatus. Alternatively, a method of using the antireflection film 17 as a mask material and immersing the entire p-type polycrystalline silicon substrate 11a in an etching solution may be used. As the etching solution, an alkaline aqueous solution such as sodium hydroxide or potassium hydroxide heated to room temperature to 95 ° C., preferably 50 ° C. to 70 ° C. is used. Alternatively, a mixed aqueous solution of nitric acid and hydrofluoric acid may be used as the etching solution.
　ついで、スクリーン印刷により電極を形成する。まず、裏面側電極１９を作成する（焼成前）。すなわち、半導体基板１１の裏面側にスクリーン印刷によって、裏面側電極１９の形状に電極材料ペーストであるアルミニウムペースト１９ａを塗布し、乾燥させる（図２－５）。 Next, electrodes are formed by screen printing. First, the back surface side electrode 19 is produced (before baking). That is, an aluminum paste 19a, which is an electrode material paste, is applied to the shape of the back surface side electrode 19 by screen printing on the back surface side of the semiconductor substrate 11 and dried (FIG. 2-5).
　つぎに、受光面側電極２１を作製する（焼成前）。すなわち、半導体基板１１の受光面である反射防止膜１７上に、表銀グリッド電極２３および表銀バス電極２５の形状に、受光面側電極材料ペーストである銀ペースト２１ａをスクリーン印刷によって塗布した後、銀ペーストを乾燥させる（図２－６）。 Next, the light-receiving surface side electrode 21 is produced (before firing). That is, after applying the silver paste 21a, which is the light receiving surface side electrode material paste, to the shape of the front silver grid electrode 23 and the front silver bus electrode 25 on the antireflection film 17 that is the light receiving surface of the semiconductor substrate 11 by screen printing. The silver paste is dried (FIGS. 2-6).
　その後、ペーストを焼成することで、裏面側電極１９と、受光面側電極２１としての表銀グリッド電極２３および表銀バス電極２５とが得られる（図２－７）。焼成は、大気雰囲気中、例えば７５０～８５０℃の範囲で選択して実施する。焼成温度の選択は、セル構造やペースト種類を考慮して行う。また、受光面側電極２１中の銀が反射防止膜１７を貫通して、ｎ型不純物拡散層１５と受光面側電極２１とが電気的に接続する。これにより、ｎ型不純物拡散層１５は、受光面側電極２１と良好な抵抗性接合を得ることができる。 Thereafter, the paste is baked to obtain the back surface side electrode 19, and the front silver grid electrode 23 and the front silver bus electrode 25 as the light receiving surface side electrode 21 (FIG. 2-7). Firing is performed by selecting in the air atmosphere, for example, in the range of 750 to 850 ° C. The firing temperature is selected in consideration of the cell structure and paste type. Further, silver in the light receiving surface side electrode 21 penetrates the antireflection film 17, and the n-type impurity diffusion layer 15 and the light receiving surface side electrode 21 are electrically connected. Thereby, the n-type impurity diffusion layer 15 can obtain a good resistive junction with the light receiving surface side electrode 21.
　以上のような工程を実施することにより、図１－１～図１－４に示す本実施の形態にかかる太陽電池セル１を作製することができる。なお、電極材料であるペーストの半導体基板１１への配置の順番を、受光面側と裏面側とで入れ替えてもよい。 By performing the steps as described above, the solar cell 1 according to the present embodiment shown in FIGS. 1-1 to 1-4 can be manufactured. In addition, the order of arrangement of the paste, which is an electrode material, on the semiconductor substrate 11 may be switched between the light receiving surface side and the back surface side.
　上述したように、実施の形態にかかる太陽電池セルの製造方法においては、半導体基板１１（ｎ型不純物拡散層１５）の受光面側の表面に、テクスチャー構造として微小凹凸を高密度で形成する。これにより、受光面において外部からの光を吸収する面積を増加し、受光面における反射率を抑え、太陽電池セル１内に光を閉じ込める効果をより有効に得ることができるため、太陽電池セル１から得られる電流の量を増加させて、出力特性を向上させることができる。 As described above, in the method for manufacturing a solar battery cell according to the embodiment, minute irregularities are formed at a high density as a texture structure on the surface of the semiconductor substrate 11 (n-type impurity diffusion layer 15) on the light receiving surface side. Thereby, the area which absorbs the light from the outside on the light receiving surface can be increased, the reflectance on the light receiving surface can be suppressed, and the effect of confining the light in the solar battery cell 1 can be obtained more effectively. The output characteristics can be improved by increasing the amount of current obtained from the above.
　また、実施の形態にかかる太陽電池セルの製造方法においては、ＩＰＡによる微小凹凸の形成能力と実用上の消費妥当性とを考慮して、エッチング液である水酸化アルカリ水溶液とイソプロピルアルコールとの混合溶液の液温が５５℃以上７５℃以下の条件でエッチングを施す。これにより、ｐ型多結晶シリコン基板１１ａの受光面側に微小凹凸を効率良く高密度で形成することができる。また、凹凸の形成に要する資材や動力の消費も抑制でき、製造コストの低減および環境負荷の低減も実現できる。 In addition, in the method for manufacturing a solar battery cell according to the embodiment, in consideration of the ability to form minute irregularities by IPA and the practical consumption validity, a mixture of an alkali hydroxide aqueous solution and isopropyl alcohol as an etchant is used. Etching is performed under the condition that the solution temperature is 55 ° C. or higher and 75 ° C. or lower. Thereby, minute irregularities can be efficiently and densely formed on the light receiving surface side of the p-type polycrystalline silicon substrate 11a. In addition, consumption of materials and power required for forming irregularities can be suppressed, and manufacturing costs and environmental loads can be reduced.
　したがって、実施の形態にかかる太陽電池セルの製造方法によれば、太陽電池セル１内への光を閉じ込める効果をより向上させて、光電変換効率に優れた太陽電池セルを作製することができる。 Therefore, according to the method for manufacturing a solar cell according to the embodiment, the effect of confining light in the solar cell 1 can be further improved, and a solar cell excellent in photoelectric conversion efficiency can be produced.
　なお、上述した実施の形態においては、シリコン系基板を破損させることなく該シリコン系基板の表面に良好な凹凸形状を効率良く形成するために水酸化アルカリ水溶液とイソプロピルアルコールの混合溶液を用いる場合について説明したが、本発明は該混合溶液として水酸化アルカリ水溶液とアルコールとの混合溶液を前記アルコールの飽和蒸気圧が２００ｍｍＨｇ以上６００ｍｍＨｇ以下の環境下で用いる場合において適用可能であり、上記と同様の効果を得ることができる。このようなアルコールとしては、イソプロピルアルコールの他にエタノールや１－プロパノールなどが挙げられる。アルコールの飽和蒸気圧が６００ｍｍＨｇよりも大である環境下では、混合液からのアルコールの離脱速度が早く、シリコンのエッチング反応が安定しない。また、アルコールの飽和蒸気圧が２００ｍｍＨｇ未満である環境下では、アルコールの離脱速度には問題ないが、混合相手である水酸化アルカリ水溶液の方の反応速度が低下し過ぎる為、結果として、生産的でなくなる。
In the above-described embodiment, a case where a mixed solution of an alkali hydroxide aqueous solution and isopropyl alcohol is used in order to efficiently form a favorable uneven shape on the surface of the silicon substrate without damaging the silicon substrate. As described above, the present invention is applicable when a mixed solution of an alkali hydroxide aqueous solution and an alcohol is used as the mixed solution in an environment where the saturated vapor pressure of the alcohol is 200 mmHg or more and 600 mmHg or less. Can be obtained. Examples of such alcohol include ethanol and 1-propanol in addition to isopropyl alcohol. In an environment where the saturated vapor pressure of alcohol is greater than 600 mmHg, the rate of alcohol removal from the mixture is high, and the silicon etching reaction is not stable. In addition, in an environment where the saturated vapor pressure of alcohol is less than 200 mmHg, there is no problem with the rate of alcohol release, but the reaction rate of the aqueous alkali hydroxide solution that is the mixing partner is too low. Not.
　また、上述した実施の形態においては、半導体基板としてｐ型のシリコン基板を使用する場合について説明したが、半導体基板としてｎ型のシリコン基板を用いてｐ型の拡散層を形成する逆導電型の太陽電池セルにおいても上述した本発明の効果を得ることができる。また、上述した実施の形態においては、半導体基板として多結晶シリコン基板を用いたが、半導体基板として単結晶シリコン基板を用いた場合においても上述した本発明の効果を得られることは言うまでもない。 In the above-described embodiment, the case where a p-type silicon substrate is used as the semiconductor substrate has been described. However, the reverse conductivity type in which a p-type diffusion layer is formed using an n-type silicon substrate as the semiconductor substrate. The effects of the present invention described above can also be obtained in solar cells. In the above-described embodiment, the polycrystalline silicon substrate is used as the semiconductor substrate. However, it goes without saying that the above-described effects of the present invention can be obtained even when a single crystal silicon substrate is used as the semiconductor substrate.
　さらに、上述した実施の形態においては、半導体基板の基板厚が２００μｍである場合について説明したが、基板が自己保持できる厚みであれば、例えば５０μｍ程度まで薄板化した基板を用いることもできる。また、上述した実施の形態においては、半導体基板の寸法が１５０ｍｍ×１５０ｍｍである場合について説明したが、この寸法よりも大きな寸法あるいは小さな寸法の基板を用いた場合においても上述した本発明の効果が得られるのは言うまでもない。 Furthermore, although the case where the substrate thickness of the semiconductor substrate is 200 μm has been described in the above-described embodiment, a substrate thinned to about 50 μm, for example, can be used as long as the substrate can be self-held. In the above-described embodiment, the case where the size of the semiconductor substrate is 150 mm × 150 mm has been described. However, even when a substrate having a size larger or smaller than this size is used, the above-described effect of the present invention is achieved. Needless to say, you can get it.
　以上のように、本発明にかかる基板の粗面化方法は、基板の表面に微小凹凸を効率的に且つ高密度に形成する場合に有用であり、特に、太陽電池基板の粗面化に適している。 As described above, the method for roughening a substrate according to the present invention is useful for efficiently and densely forming minute irregularities on the surface of the substrate, and is particularly suitable for roughening a solar cell substrate. ing.
　１　太陽電池セル
　１１　半導体基板
　１１ａ　ｐ型多結晶シリコン基板
　１３　ｐ型多結晶シリコン層
　１５　ｎ型不純物拡散層
　１７　反射防止膜
　１９　裏面側電極
　１９ａ　アルミニウムペースト
　２１　受光面側電極
　２１ａ　銀ペースト
　２３　表銀グリッド電極
　２５　表銀バス電極
　３１ａ　ｐ型多結晶シリコン基板
　１１０　核
　１１１　平坦部 DESCRIPTION OF SYMBOLS 1 Solar cell 11 Semiconductor substrate 11a p-type polycrystalline silicon substrate 13 p-type polycrystalline silicon layer 15 n-type impurity diffusion layer 17 Antireflection film 19 Back surface side electrode 19a Aluminum paste 21 Light-receiving surface side electrode 21a Silver paste 23 Table silver grid Electrode 25 Surface silver bus electrode 31a p-type polycrystalline silicon substrate 110 nucleus 111 flat portion

Claims (7)

  1. 　シリコン系基板に表面処理を施すことにより前記シリコン系基板の表面にテクスチャー構造を形成する基板の粗面化方法であって、
    　前記シリコン系基板の表面に対して、水酸化アルカリ水溶液とアルコールとの混合溶液を前記アルコールの飽和蒸気圧が２００ｍｍＨｇ以上６００ｍｍＨｇ以下の環境下でエッチング液として用いて、前記エッチング液の液温が５５℃以上７５℃以下の条件でエッチングを施すことにより、前記シリコン系基板の表面に微細凹凸を形成する凹凸形成工程を含むこと、
    　を特徴とする基板の粗面化方法。     A surface roughening method for forming a texture structure on the surface of a silicon substrate by subjecting the silicon substrate to a surface treatment,
    A mixed solution of an alkali hydroxide aqueous solution and an alcohol is used as an etchant with respect to the surface of the silicon substrate in an environment where the saturated vapor pressure of the alcohol is 200 mmHg or more and 600 mmHg or less, and the liquid temperature of the etchant is 55. Including an unevenness forming step of forming fine unevenness on the surface of the silicon-based substrate by performing etching under conditions of not lower than 75 ° C and not higher than 75 ° C;
    A method for roughening a substrate.
  2. 　前記凹凸形成工程において、前記エッチング液の液温が６５℃以上７５℃以下の条件でエッチングを施すこと、
    　を特徴とする請求項１に記載の基板の粗面化方法。     In the unevenness forming step, etching is performed under conditions where the liquid temperature of the etching solution is 65 ° C. or higher and 75 ° C. or lower,
    The method for roughening a substrate according to claim 1.
  3. 　前記シリコン系基板は、インゴットをスライスして切り出された基板であり、
    　前記凹凸形成工程の前に、前記シリコン系基板の表面をエッチングして前記スライスにより生じた前記シリコン系基板の表面のダメージ層を除去するダメージ層除去工程を有すること、
    　を特徴とする請求項１に記載の基板の粗面化方法。     The silicon-based substrate is a substrate cut out by slicing an ingot,
    Before the step of forming the irregularities, it has a damage layer removal step of removing the damage layer on the surface of the silicon substrate generated by the slicing by etching the surface of the silicon substrate,
    The method for roughening a substrate according to claim 1.
  4. 　前記アルコールが、イソプロピルアルコール、エタノール、１－プロパノールのいずれか１種であること、
    　を特徴とする請求項１に記載の基板の粗面化方法。     The alcohol is any one of isopropyl alcohol, ethanol, and 1-propanol;
    The method for roughening a substrate according to claim 1.
  5. 　前記水酸化アルカリ水溶液が、水酸化ナトリウム水溶液であること、
    　を特徴とする請求項４に記載の基板の粗面化方法。     The aqueous alkali hydroxide solution is an aqueous sodium hydroxide solution,
    The method for roughening a substrate according to claim 4.
  6. 　前記水酸化ナトリウム水溶液の濃度が１．５ｗｔ％以上１０ｗｔ％以下であり、前記アルコールの濃度が２．０ｗｔ％以上５．０ｗｔ％以下であること、
    　を特徴とする請求項５に記載の基板の粗面化方法。     The concentration of the sodium hydroxide aqueous solution is 1.5 wt% or more and 10 wt% or less, and the concentration of the alcohol is 2.0 wt% or more and 5.0 wt% or less.
    The method for roughening a substrate according to claim 5.
  7. 　請求項１～５のいずれか１つに記載の基板の粗面化方法により第１導電型のシリコン系基板の一面側を粗面化する粗面化工程と、
    　前記シリコン系基板の一面側に、第２導電型の不純物元素を拡散して不純物拡散層を形成する不純物拡散層形成工程と、
    　前記シリコン系基板の一面側における電極形成領域および前記シリコン系基板の他面側に電極を形成する電極形成工程と、
    　を含むことを特徴とする光起電力装置の製造方法。     A roughening step of roughening one surface side of the first conductivity type silicon substrate by the method of roughening a substrate according to any one of claims 1 to 5;
    An impurity diffusion layer forming step of forming an impurity diffusion layer by diffusing an impurity element of a second conductivity type on one surface side of the silicon-based substrate;
    Forming an electrode on one side of the silicon-based substrate and an electrode forming region on the other side of the silicon-based substrate; and
    A method for manufacturing a photovoltaic device, comprising:
PCT/JP2009/068028 2009-10-19 2009-10-19 Method for roughening substrate surface, and method for manufacturing photovoltaic device WO2011048656A1 (en)

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JP2013143404A (en) * 2012-01-06 2013-07-22 Mitsubishi Electric Corp Silicon substrate etching method
JPWO2012165288A1 (en) * 2011-06-03 2015-02-23 三洋電機株式会社 Manufacturing method of solar cell

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JPWO2012165288A1 (en) * 2011-06-03 2015-02-23 三洋電機株式会社 Manufacturing method of solar cell
JP2013143404A (en) * 2012-01-06 2013-07-22 Mitsubishi Electric Corp Silicon substrate etching method

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