JP2016002434A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can prevent unexpected operation by an unused circuit.SOLUTION: Random number circuits 508a and 508b are provided with random number circuits of 4 channels respectively, it is set so that only channels 0 and 1 of the random number circuit 508b are started and channels 0 to 3 of the random number circuit 508a and channels 2 and 3 of the random number circuit 508b are set to be unused and not to be activated. A set value which is different from an initial value (all 0) at the time of factory shipment and does not cause any problem even granting that operation is wrongly started is set as a set value corresponding to operation setting of the unused random number circuit in a program management area.

Description

  The present invention relates to a gaming machine capable of performing a predetermined game, such as a pachinko gaming machine or a slot machine.

  As this type of gaming machine, there is a game control microcomputer equipped with a plurality of circuits such as a random number circuit for generating a random number value used for a lottery or the like. There has been proposed one that can arbitrarily set the use / non-use of a plurality of circuits by changing the set area (see, for example, Patent Document 1).

JP 2007-54438 A

  As in the slot machine described in Patent Document 1, a game control microcomputer equipped with a plurality of circuits is provided. Depending on the model, only a part of the circuit may be used. Even if the unused circuit is set to be unused, the circuit may operate due to noise or the like, and there is a possibility that the microcomputer may cause an unexpected operation.

  The present invention has been made paying attention to such problems, and an object thereof is to provide a gaming machine that can prevent an unexpected operation by an unused circuit.

In order to solve the above-mentioned problem, a gaming machine according to means 1 of the present invention provides:
In a gaming machine (slot machine 1) capable of performing a predetermined game,
Control circuits for performing predetermined control (channels 0 to 3 of the random number circuit 508a, channels 0 to 3 of the random number circuit 508b);
First information (16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2) indicating whether to use the control circuit (channels 0 to 3 of the random number circuit 508a, channels 0 to 3 of the random number circuit 508b) (KRL2), 8-bit random number initial setting 1 (KRS1), activation method selection in 8-bit random number initial setting 2 (KRS2)) and the control circuit (channels 0 to 3 of the random number circuit 508a, channel 0 of the random number circuit 508b) To 3) second information (16 bit random number initial setting 1 (KRL1), 16 bit random number initial setting 2 (KRL2), 8 bit random number initial setting) indicating whether or not the control by the setting different from the predetermined setting is performed. 1 (KRS1), 8-bit random number initial setting 2 (KRS2) update clock setting, random number sequence change method setting, 16-bit random number initial setting 3 (KR Start destination setting of the 3), a setting of changing the presence or absence of each system reset), a storage area (program management area region of ROM 41b) which but is at least stored,
With
In the storage area, information indicating that the control circuit (channels 0 to 3 of the random number circuit 508a, channels 2 and 3 of the random number circuit 508b) is not used as the first information (setting corresponding to activation by setting the maximum value) Even if the value and the maximum value are not set), control by the control circuit (channels 0 to 3 of the random number circuit 508a and channels 2 and 3 of the random number circuit 508b) is previously performed as the second information. Information indicating that the setting is different from the specified setting is stored (for two external clock cycles, random number sequence automatic change, start value based on ID number, start value changed at each system reset) It is characterized by.
According to this feature, even when information indicating that the control circuit is not used is stored as the first information in the storage area, the control by the control circuit is set in advance as the second information. Since the information indicating that the setting is different from the setting is stored, even if the control circuit that is set not to be used is operated for some reason, it is predetermined as the standard specification as the second information. In this case, setting that does not cause a problem even if the operation is performed instead of the initial setting can prevent an unexpected operation by the control circuit.
Note that a gaming machine capable of performing a predetermined game corresponds to a pachinko gaming machine, a slot machine, or the like installed in a game hall.
The control circuit that performs predetermined control corresponds to, for example, a random number circuit that generates a random number, a communication circuit that performs communication, a reset circuit that generates a reset signal, an interrupt control circuit that controls an interrupt, and the like. .

The gaming machine according to means 2 of the present invention is the gaming machine according to means 1,
A plurality of the control circuits are provided,
In the storage area, information indicating that it is used as the first information for one control circuit (channels 0 and 1) to be used among a plurality of similar control circuits (channels 0 to 3 of the random number circuit 508b) ( Auto-start at user mode transition) is stored and indicates that it is not used as the first information for other control circuits (channels 2 and 3) different from the one control circuit among the plurality of similar control circuits Information (setting value corresponding to start-up with maximum value setting and non-maximum value setting) is stored.
According to this feature, unexpected operation by an unused control circuit can be prevented when only a necessary control circuit is used among a plurality of similar control circuits.

The gaming machine according to means 3 of the present invention is the gaming machine according to means 2,
In the storage area, information indicating that the second information about the other control circuit (channels 2 and 3) is set with the same setting as the second information about the one control circuit (external clock signal). 2 rounds, automatic random number change, start value based on ID number, and change start value at every system reset) are stored.
According to this feature, even if another control circuit that is set not to be used is operated for some reason, the second information is used instead of the initial setting predetermined as the standard specification. By setting the same setting as that of the same type of control circuit to which the effect is set, the operation by the control circuit can be kept within the expected range.

A gaming machine according to means 4 of the present invention is the gaming machine according to any one of means 1 to 3,
The control circuit includes a random number circuit (channels 2 and 3 of the random number circuit 508b) for generating numerical data to be a random number value,
In the storage area, information indicating that the random number circuit (channels 2 and 3 of the random number circuit 508b) is not used as the first information (a setting value corresponding to activation with a maximum value setting and a non-maximum value setting) As the second information for the random number circuit (channels 2 and 3 of the random number circuit 508b), information indicating that the initial value for starting the update of the numerical data is changed at each activation (at each system reset) The feature is that the start value is changed).
According to this feature, even if it is an unused random number circuit, it is difficult to specify the numerical data generated by the random number circuit, so that fraud using the numerical data can be prevented in advance.

The gaming machine according to means 5 of the present invention is the gaming machine according to any one of means 1 to 4,
The control circuit includes a random number circuit (channels 2 and 3 of the random number circuit 508b) for generating numerical data to be a random number value,
In the storage area, information indicating that the random number circuit (channels 2 and 3 of the random number circuit 508b) is not used as the first information (a setting value corresponding to activation with a maximum value setting and a non-maximum value setting) And information indicating that the numerical data update method is to be changed (random number sequence automatic change) is stored as the second information for the random number circuit (channels 2 and 3 of the random number circuit 508b). It is characterized by.
According to this feature, even if it is an unused random number circuit, it is difficult to specify the numerical data generated by the random number circuit, so that fraud using the numerical data can be prevented in advance.

The gaming machine according to means 6 of the present invention is the gaming machine according to any one of means 1 to 5,
Determination means (update monitoring circuit 537) for determining whether or not an abnormality has occurred in the control in the control circuit;
A determination information storage area (internal information register (CIF)) in which information indicating the determination result of the determination means is stored;
With
The determination means determines whether or not an abnormality (update abnormality) has occurred in an unused control circuit (channels 2 and 3 of the random number circuit 508b),
In the determination information storage area (internal information register (CIF)), information indicating a determination result for the unused control circuit (channels 2 and 3 of the random number circuit 508b) is also stored.
According to this feature, if an abnormality occurs in an unused control circuit, the presence or absence can be confirmed.

  In addition, this invention may have only the invention specific matter described in the claim of this invention, and has a structure other than this invention specific matter with the invention specific matter described in the claim of this invention. It may be a thing.

It is a front view of the slot machine of Example 1 to which the present invention was applied. It is a perspective view which shows the internal structure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure which shows an example of the address map in a main control part. It is a figure which illustrates the main part of a program management area. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the correspondence of the setting data and operation | movement in a header (KHDR). It is a figure which shows an example of the setting content in a program code end address (KPCE), a program code start address 2 (KPCS2), and a program code end address 2 (KPCE2). It is a figure which shows an example of the setting content in reset setting (KRES). It is a figure which shows an example of the setting content in 16 bit random number initial setting 1 (KRL1). It is a figure which shows an example of the setting content in 16 bit random number initial setting 2 (KRL2). It is a figure which shows an example of the setting content in 16 bit random number initial setting 3 (KRL3). It is a figure which shows an example of the setting content in 8-bit random number initial setting 1 (KRS1). It is a figure which shows an example of the setting content in 8-bit random number initial setting 2 (KRS2). It is a figure which shows an example of the setting content in security time setting (KSES). It is a figure which shows an example of the setting content in random number clock monitoring setting (KRCS). It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the example of 1 structure of an 8-bit random number circuit. It is a block diagram which shows one structural example of a 16-bit random number circuit. It is explanatory drawing which shows an example of a structure example and setting content of RL0 hard latch selection register 0 (RL0LS0). It is explanatory drawing which shows an example of a structure example and setting content of RL0 hard latch selection register 1 (RL0LS1). It is explanatory drawing which shows an example of a structure of a RLn hard latch selection register (RLnLS), and an example of a setting content. It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch selection register 0 (RSLS0). It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch selection register 1 (RSLS1). It is explanatory drawing which shows an example of a structure of RL interruption control register 0 (RLIC0), and an example of the setting content. It is explanatory drawing which shows an example of a structure of RL interruption control register 1 (RLIC1), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RS interruption control register (RSIC), and an example of the setting content. It is explanatory drawing which shows an example of a structure of a RLn maximum value setting register (RLnMX), and an example of the setting content. It is explanatory drawing which shows an example of a structure example of RSn maximum value setting register (RSnMX), and a setting content. It is explanatory drawing which shows an example of a structure example and setting content of a random number sequence change register (RDSC). It is explanatory drawing which shows an example of a structure example and setting content of a random number soft latch register (RDSL). It is explanatory drawing which shows an example of a structure of a random number soft latch flag register (RDSF), and an example of the setting content. It is explanatory drawing which shows an example of a structure of a RLn soft latch random number value register (RLnSV), and an example of setting content. It is explanatory drawing which shows an example of a structure example of RSn soft latch random number value register (RSnSV), and a setting content. It is explanatory drawing which shows an example of a structure of RL hard latch flag register 0 (RLHF0), and an example of the setting content. It is explanatory drawing which shows an example of a structure example and setting content of RL hard latch flag register 1 (RLHF1). It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch flag register (RSHF). It is explanatory drawing which shows an example of a structure of a RL0 hard latch random number value register m (RL0mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure example of RL1 hard latch random number value register m (RL1mHV), and a setting content. It is explanatory drawing which shows an example of a structure of a RL2 hard latch random number value register m (RL2mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RL3 hard latch random number value register m (RL3mHV), and an example of the setting content. It is explanatory drawing which shows an example of a structure example of RSn hard latch random number value register (RSnHV), and a setting content.

  The form for implementing the game machine of this invention is demonstrated below based on an Example.

  An embodiment of a slot machine, which is an example of a gaming machine to which the present invention is applied, will be described with reference to the drawings. As shown in FIG. The front door 1b is pivotally supported at the side end of the housing 1a.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C and 2R (hereinafter referred to as a left reel, a middle reel and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  As shown in FIG. 3, on the outer periphery of the reels 2L, 2C, and 2R, “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of types of mutually distinguishable symbols such as “plum”, “watermelon”, “cherry”, “bell”, and “orange” are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in upper, middle, and lower three stages in the see-through window 3 provided at the approximate center of the front door 1b.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  At the position corresponding to each of the reels 2L, 2C, and 2R on the front door 1b, a horizontally-long rectangular see-through window 3 that allows the reels 2L, 2C, and 2R to be seen through from the front side is provided. The reels 2L, 2C, and 2R can be visually recognized from the player side.

  As shown in FIG. 1, on the front door 1b, there are a medal insertion portion 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value). The MAXBET switch 6 that is operated when setting the maximum bet number (3 in any game state in the present embodiment) among the specified number of bets determined according to the game state within the range. The settlement switch 10 that is operated when the medals stored as credits and the medals used for setting the number of bets are settled (the medals used for setting the credits and the number of bets are returned), and the game is started. Start switch 7 that is operated at the time, and stop switches 8L, 8C, and 8R that are operated when the rotation of the reels 2L, 2C, and 2R is stopped, respectively, for performance. Use the switch 56 are respectively provided so as to be operated by the player.

  In this embodiment, among the three reels 2L, 2C, and 2R that have started to rotate, the reel that stops first is referred to as a first stop reel, and the stop is referred to as a first stop. Similarly, the reel that stops second is called the second stop reel, the stop is called second stop, the reel that stops third is called the third stop reel, and the stop is the third stop. Alternatively, it is called final stop.

  Further, as shown in FIG. 1, the front door 1b has a liquid crystal display 51 that can display an image, a credit display 11 that displays the number of medals stored as credits, and a payout due to the occurrence of a prize. Game auxiliary indicator 12 that displays the number of medals and an error code indicating the contents when an error occurs, 1 BETLED 14 that notifies that the bet number is set by 1, and lights that the bet number is set to 2 2BETLED 15 for informing, 3BETLED 16 for informing that the number of bets is set by 3 lighting, insertion request LED 17 for informing that a medal can be inserted by lighting, and start operation of the game by operating the start switch 7 are effective. Start valid LED 18 to notify that there is light, wait (a certain period of time has elapsed since the start of the previous game The game is provided with a waiting LED 19 for notifying the fact that the reel is starting to be rotated because it has not been turned on, and a replaying LED 20 for notifying that the replay game is to be described later. A display unit 13 is provided.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the bet amount by the operation of the MAXBET switch 6 is valid, and stop switches 8L, 8C, The left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 4) are provided inside the 8R to notify that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid by lighting. It has been.

  As shown in FIG. 2, a reset switch 23 (see FIG. 4) for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation is provided inside the front door 1b. A setting value display 24 that displays the setting value at that time while changing the setting value to be confirmed or checking the setting value, a stop state at the end of the bonus (a state in which the progress of the game is restricted until a reset operation is performed) A stop switch 36a for selecting whether the stop function to be controlled is valid / invalid, for automatic settlement processing at the end of the bonus (processing to settle (return) medals stored as credits regardless of the player's operation) An automatic settlement switch 36b for selecting whether the automatic settlement function to be controlled is valid / invalid, and a flow path for medals inserted from the medal insertion section 4 are provided in the case 1 described later provided in the housing 1a. -A flow path switching solenoid 30 (see FIG. 4) for selectively switching to either the tank 34a side or the medal payout exit 9 side, and a medal that has been inserted from the medal insertion unit 4 and has flowed to the hopper tank 34a side is detected. A medal selector 29 having an inserted medal sensor 31 (see FIG. 4) and a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b are provided.

  As shown in FIG. 2, the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R (see FIG. 4), and the reel reference positions of the reels 2L, 2C, and 2R are detected inside the housing 1a. A reel unit 2 including possible reel sensors 33L, 33C, and 33R (see FIG. 4), an external output board 1000 (see FIG. 4) for outputting an external output signal, and a medal inserted from the medal insertion unit 4 are stored. A hopper tank 34a, a hopper motor 34b for paying out medals stored in the hopper tank 34a from the medal payout opening 9 (see FIG. 4), and a payout sensor 34c for detecting the medals paid out by driving the hopper motor 34b (see FIG. 4). 4) and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full tank sensor 35a is provided for detecting that the amount of stored medal is equal to or greater than a predetermined amount, that is, the overflow tank 35 is full.

  As shown in FIG. 2, a function key switch 37 for switching to a setting change state or a setting confirmation state is provided on the front surface of the power supply box 100, and functions as a reset switch for canceling an error state or a stop state in normal times. In the setting change state, a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery described later, and a power source that is operated when turning on / off the power source A switch 39 is provided.

  The power supply box 100 is provided inside the housing 1a, and the front door 1b can be opened by a predetermined key operation held by a store clerk or the like. The set key switch 37, the reset / setting switch 38, and the power switch 39 are operated only by a person such as a store clerk who has the key, and cannot be operated by the player. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires further key operation after the front door 1b is opened by key operation, only the store clerk possessing the key for operating the setting key switch 37 among the game store clerk. Operation is possible.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the state where the game can be started. Become. In the present embodiment, when the prescribed number of bets is set to three regardless of the gaming state and the prescribed number of bets is set, the pay line LN becomes valid. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged in the horizontal direction in the middle stage of the reel 2L, the middle stage of the reel 2C, the middle stage of the reel 2R, that is, the middle stage, is used as the winning line. It has been established. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  Further, in the present embodiment, invalid lines LM1 to LM1 are set apart from the winning line LN in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning line. The invalid lines LM1 to LM4 are not determined based on the combination of symbols arranged in the invalid lines LM1 to LM4. When the combination of symbols constituting a specific prize is arranged on the winning line LN, the invalid line is displayed. When a combination of symbols (for example, bell-bell-bell) that is awarded when the winning line LN is aligned with any of the LM1 to LM4 is arranged, the symbols constituting a specific winning in the winning line LN It is easy to recognize that the combination is complete. In this embodiment, as shown in FIG. 1, an invalid line LM1 and a lower stage of the reel 2L, which are set across the symbols arranged horizontally in the upper stage of the reel 2L, the upper stage of the reel 2C, the upper stage of the reel 2R, that is, the upper stage. , The lower stage of the reel 2C, the lower stage of the reel 2R, that is, the invalid line LM2 set across the symbols arranged horizontally in the lower stage, the upper stage of the reel 2L, the middle stage of the reel 2C, the lower stage of the reel 2R, that is, the lower side There are four types of invalid lines LM3 set across straddling symbols LM3, lower stage of reel 2L, middle stage of reel 2C, upper stage of reel 2R, that is, invalid line LM4 set straddling to the right. It is defined as.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  When one of the reels 2L, 2C, and 2R is stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a role) is displayed on the reels 2L, 2C, and 2R on the winning line LN. If the game stops as a result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when the combination of symbols accompanying the transition of the gaming state on the winning line LN is stopped as a display result of each reel 2L, 2C, 2R, the gaming state according to the combination of symbols is shifted. .

  In this embodiment, the game starts when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and the game ends when all the reels are stopped. Further, one unit of control (game control) for executing a game starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

  In this embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, a configuration using four or more reels may be used. In the configuration using two or more reels, a winning determination may be made based on a combination of display results derived for all two or more reels. In this embodiment, the variable display device is configured by physical reels. However, the variable display device may be configured by an image display device such as a liquid crystal display.

  In the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated and the symbols start to change, any one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped, and the symbols are stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

  The reels 2L, 2C and 2R rotate 80 times per minute, and 80 × 21 (the number of symbols per reel) = 1680 frames, so the maximum of 4 symbols is drawn in 190 ms. Will be able to. In other words, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are four frames ahead of them, for a total of five symbols.

  For this reason, for example, when any one of the stop switches 8L, 8C, 8R is operated and the symbol displayed on the lower stage of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead is used. Since the symbols can be displayed in the lower row, in each of the reels 2L, 2C, 2R, when any one of the stop switches 8L, 8R is operated, the symbol displayed in the middle row of the reel corresponding to the stop switch. The symbols arranged within 5 frames including can be displayed on the winning line.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected through the. The power supply line for supplying power to the effect control board is directly connected from the power supply board 101 to the effect control board 90 without going through the game control board 40, and the power supply board 101 directly supplies power to the effect control board 90. May be supplied.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the above-described MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, insertion medal sensor 31, door open The detection switch 25 and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Detection signals from these connected switches are input.

  Further, the game control board 40 includes the credit indicator 11, the game auxiliary indicator 12, 1-3 BET LEDs 14-16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, the BET switch valid LED 21, the left The middle and right stop valid LEDs 22L, 22C and 22R, the set value display 24, the flow path switching solenoid 30, the reel motors 32L, 32C and 32R are connected, and the hopper motor 34b described above is connected via the power supply board 101. These electrical components are connected, and are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a control clock generation circuit 42, a random number clock generation circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, and a power interruption detection circuit. 48 and a reset circuit 49 are mounted.

  The main control unit 41 performs processing related to the progress of the game, and directly or indirectly controls each unit of the control circuit mounted on the game control board 40. In the main control unit 41, the CPU 41a described later executes control in accordance with a program stored in the ROM 41b. Therefore, what the main control unit 41 executes (or performs processing) below specifically refers to the CPU 41a. Is to execute control according to the program. The same applies to the sub-control unit 91 described later. However, as described later, when the power to the slot machine 1 is turned on or a system reset occurs, the main control unit 41 sets the internal reset operation, the setting of the mounted circuit, the setting of the register, etc. according to the setting contents of the program management area. However, this setting operation is executed by the main control unit 41 in hardware regardless of the program.

  The control clock generation circuit 42 generates a control clock CCLK serving as an oscillation signal having a predetermined frequency outside the main control unit 41. The control clock CCLK generated by the control clock generation circuit 42 is supplied to the clock circuit 502. The random number clock generation circuit 43 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the main control unit 41. The random number clock RCLK generated by the random number clock generation circuit 43 is supplied to the random number circuits 508a and 508b. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be set to be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42. Alternatively, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be higher than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42.

  In the present embodiment, the case where the dedicated random number clock RCLK is input from the random number clock generation circuit 43 to the random number circuits 508a and 508b is shown, but the present invention is not limited thereto. For example, instead of using a dedicated clock, the control clock CCLK from the control clock generation circuit 42 may be input to the random number circuits 508 a and 508 b inside the main control unit 41. In this case, for example, a random number counter (random number generation circuits 525a and 525b described later) incorporated in the random number circuits 508a and 508b may be updated using a signal obtained by dividing the control clock CCLK. In this case, the random number clock generation circuit 43 may not be provided on the game control board 40.

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit 47 transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 provides a system reset signal to the main control unit 41 in a state where the power is unstable, such as when the power is turned on or when the power is turned off.

  FIG. 5 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 5 is a one-chip microcomputer, and the main control unit 41 shown in FIG. 5 is an external bus interface 501, a clock circuit 502, a verification block 503, and a unique information storage circuit 504. , An arithmetic circuit 505, a reset / interrupt controller 506, a CPU (Central Processing Unit) 56, a ROM (Read Only Memory) 54, a RAM (Random Access Memory) 55, a free-run counter circuit 507, and a random number circuit 508a and 508b, a timer circuit 509, an interrupt controller 510, a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decoding circuit 514.

  The reset / interrupt controller 506 is a circuit that controls external interrupt requests and interrupt requests from built-in peripheral circuits (eg, serial communication circuit 512, random number circuits 508a and 508b, timer circuit 509). The reset / interrupt controller 506 includes an out-of-designated area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it is detected that the user program is executed outside the designated area. The watchdog timer 506b has a function of generating a timeout signal for each set period.

  The reset controlled by the reset / interrupt controller 506 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. In this embodiment, a system reset is also generated when a watchdog timer (WDT) time-out signal is generated or when travel outside the specified area is prohibited (IAT) due to the reset setting (KRES). There are things to do. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  Interrupts controlled by the reset / interrupt controller 506 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 41a is in an interrupt-disabled state. An interrupt that occurs. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 41a, and can execute multiple interrupts by setting priority. The cause of maskable interrupt INT is that a low level signal is input to external maskable interrupt terminal XINT (also used as input port PI5) for a certain period of time, a timeout occurs in timer circuit 509, a serial communication circuit There are a plurality of types of interrupt factors, such as the occurrence of an interrupt factor due to data reception or data transmission at 512, and the occurrence of an interrupt factor due to the acquisition of numerical data as a random value in the random number circuits 508a and 508b. It may be determined in advance.

  The external bus interface 501 is a bus interface having an interface function between an external bus and an internal bus of a chip constituting the main control unit 41, an address bus, a data bus, and a direction control function of each control signal. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the main control unit 41, and transmits / receives address signals, data signals, various control signals, and the like to / from these external devices. Anything to do.

  The clock circuit 502 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EX by two. The generated internal system clock is output from the external output terminal (CLKO terminal) to the outside.

  The verification block 503 is connected to an external verification machine and has a function of performing chip verification. The arithmetic circuit 505 is a circuit that performs multiplication and division.

  The unique information storage circuit 504 is a circuit that stores a plurality of types of unique information that is internal information of the main control unit 41. As an example, the unique information storage circuit 504 stores three kinds of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 41b code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 41b, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. The ID number is an 8-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. Here, it is sufficient that the chip individual number can be read from the user program while the ID number cannot be read from the user program. The unique information storage circuit 504 may be included in the ROM 41b by using a predetermined area of the ROM 41b, for example. Alternatively, the unique information storage circuit 504 may be included in the CPU 41a by using, for example, a built-in register of the CPU 41a.

  The CPU 41a is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, the CPU 41a reads fixed data from the ROM 41b, the variable data writing operation in which the CPU 41a writes various fluctuation data to the RAM 41c and temporarily stores them, and the CPU 41a is temporarily stored in the RAM 41c. A variable data reading operation for reading out various variable data being received, a receiving operation in which the CPU 41a receives input of various signals from the outside of the main control unit 41 via the external bus interface 501, the parallel input port 511, the serial communication circuit 512, etc. However, a transmission operation for outputting various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like is also performed.

  The ROM 41b stores a control code indicating a user program (game control processing program for game control), fixed data, and the like.

  The RAM 41c provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

  As the free-run counter circuit 507, four channels of 8-bit free-run counters are mounted.

  The random number circuit 508a is a circuit that generates an 8-bit random number, and the random number circuit 508b is a circuit that generates a 16-bit random number. In this embodiment, a hardware random number generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b is used as a random number for internal lottery and a random number for freeze lottery described later. In the example shown in FIG. 5, one random number circuit 508a that generates an 8-bit random number and one random number circuit 508b that generates a 16-bit random number are illustrated. 4 circuits (4 channels) are mounted on each of the random number circuit 508a that generates the 16 bits and the random number circuit 508b that generates the 16-bit random numbers. In this embodiment, the four channels of the random number circuit 508a that generates an 8-bit random number may be expressed as RS0 to RS3, respectively, and the four channels of the random number circuit 508b that generates a 16-bit random number are expressed as RL0 to RL3, respectively. Sometimes expressed.

  The timer circuit 509 is an 8-bit programmable timer, and the main control unit 41 includes three channels of 8-bit counters as the timer circuit 509. In this embodiment, it is possible to perform a real-time interrupt request and time measurement by using a timer circuit 509 and setting by a user program.

  The interrupt controller 510 is a circuit that controls an external interrupt request from the PI5 / XINT terminal and an interrupt request from a built-in peripheral circuit (for example, serial communication circuit 512, random number circuits 508a and 508b, timer circuit 509). is there.

  The parallel input port 511 incorporates an 8-bit wide input-only port (PIP). Further, the parallel output port 513 provided in the main control unit 41 shown in FIG. 5 incorporates an output-only port (POP) having an 11-bit width.

  The serial communication circuit 512 is a circuit that performs asynchronous serial communication in input / output with respect to the outside. The main control unit 41 includes, as the serial communication circuit 512, a 1-channel circuit for both transmission and reception and a 3-channel circuit for transmission only.

  The address decoding circuit 514 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. In response to the chip select signal, the internal circuit of the main control unit 41 or the external device serving as a peripheral device is selectively operated effectively and can be accessed from the CPU 41a.

  FIG. 6 shows an example of an address map in the main control unit 41. As shown in FIG. 6, the area from address 0000H to address 2FFFH is allocated to the ROM 41b of the main control unit 41 and includes a program code / data area (an area for storing user programs and data) and a program management area. . FIG. 7 shows an example of the usage and contents of the main part of the program management area in the ROM 41b. The area from address F000H to address F3FFH is allocated to the RAM 41c of the main control unit 41. An area from address FE00H to address FEBFH is a built-in register area assigned to the built-in register of the main control unit 41. 8 to 10 show examples of uses and contents of the main part of the built-in register area. The area from the address FED0H to the address FEFDH is an XCS / XCSE decode area allocated to the address decode circuit 514.

  The program management area is a storage area for storing information necessary for the main control unit 41 to perform various settings such as internal reset operation settings and random number circuits 508a and 508b during system reset. As shown in FIG. 7, the program management area includes a header (KHDR), a program code end address (KPCE), a program code start address 2 (KPCS2), a program code end address 2 (KPCE2), a reset setting (KRES), 16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2 (KRL2), 16-bit random number initial setting 3 (KRL3), 8-bit random number initial setting 1 (KRS1), 8-bit random number initial setting 2 (KRS2), Security time setting (KSES), random number clock monitoring setting (KRCS), and the like are included. As shown in FIGS. 8 to 10, the internal register area includes an internal information register (CIF), various registers used in the random number circuits 508a and 508b, and the like.

  The header (KHDR) stored in the program management area indicates the setting of an 8-byte code string indicating the start of the program management area and the reading setting of internal data in the main control unit 41. FIG. 11 illustrates the correspondence between the setting data and the operation in the header (KHDR). Here, the main control unit 41 can set a ROM read prevention function and a bus output mask function. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 41b included in the main control unit 41, and the read data stored in the ROM 41b cannot be read in a state where reading is prohibited. The bus output mask function is used to output an address bus, a data bus, and a control signal in the external bus interface 501 when there is a read request for the internal data of the main control unit 41 from an external device connected to the external bus interface 501. This function disables reading of internal data from an external device by applying a mask. As shown in FIG. 11, in accordance with setting data set as an 8-byte code string indicating the start of the program management area, the operation combinations of the ROM read prevention function and the bus output mask function are set to be different. Of the setting data shown in FIG. 11, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data. In this embodiment, ROM read prohibition data is set, ROM read is prohibited, and the bus output mask is valid.

  The program code end address (KPCE) stored in the program management area indicates the setting of the final address of the program code area that continues from 0000H of the user program. FIG. 12A shows an example of setting contents in the program code end address (KPCE).

  In this embodiment, two program code areas can be set in the program code / data area from address 0000H to address 2FBFH. Specifically, the first program code area can be set as an area from address 0000H to the address set by the program code end address (KPCE), and the second program code area is the program code start It can be set as an area from the address set by address 2 (KPCS2) to the address set by program code end address 2 (KPCE2). Hereinafter, the program code stored in the first program code area is also referred to as program code 1, and the program code stored in the second program code area is also referred to as program code 2.

  As shown in FIG. 12A, the lower address of the final address of the program code 1 is set in the address 2FD3H of the program code end address (KPCE). In addition, the upper address of the final address of the program code 1 is set in the address 2FD4H.

  Program code start address 2 (KPCS2) stored in the program management area indicates the setting of the start address of the second program code area when the user program is divided into two blocks. FIG. 12B shows an example of setting contents at the program code start address 2 (KPCS2).

  As shown in FIG. 12B, the lower address of the head address of the program code 2 is set in the address 2FD5H of the program code start address 2 (KPCS2). In addition, the upper address of the head address of the program code 2 is set in the address 2FD6H. If the program code area is not divided into two, 0000H may be set to address 2FD5H and address 2FD6H of program code start address 2 (KPCS2).

  The program code end address 2 (KPCE2) stored in the program management area indicates the setting of the final address of the second program code area when the user program is divided into two blocks. FIG. 12C shows an example of setting contents in the program code end address 2 (KPCE2).

  As shown in FIG. 12C, the lower address of the final address of the program code 2 is set in the address 2FD7H of the program code end address 2 (KPCE2). In addition, the upper address of the final address of the program code 2 is set in the address 2FD8H. If the program code area is not divided into two, 0000H may be set to address 2FD7H and address 2FD8H of program code end address 2 (KPCE2).

  The setting contents of the program code end address (KPCE), the program code start address 2 (KPCS2), and the program code end address 2 (KPCE2) shown in FIG. 12 are executed correctly in the designated area by the IAT circuit 506a. Referenced when monitoring whether or not. That is, the IAT circuit 506a designates from 0000H to the address indicated by the program code end address (KPCE) or from the address indicated by the program code start address 2 (KPCS2) to the address indicated by the program code end address 2 (KPCE2). It is determined whether or not the user program is being executed within the range, and an IAT signal is output based on the detection that the user program is being executed outside the specified range.

  The reset setting (KRES) stored in the program management area indicates an internal reset operation and a setting for enabling / disabling the operation of the watchdog timer (WDT) 506b. FIG. 13 shows an example of setting contents in the reset setting (KRES).

  Bit [7] of reset setting (KRES) is internally reset when a time-out signal is input from watchdog timer (WDT) 506b or when an IAT occurs (when an IAT signal is input from IAT circuit 506a) It shows the setting of the operation when this occurs. In the example shown in FIG. 13, if the bit value in the reset setting (KRES) bit [7] is “0”, a user reset occurs when a time-out signal or an IAT signal is input. On the other hand, if the bit value in the reset setting (KRES) bit [7] is “1”, a system reset occurs when a time-out signal or an IAT signal is input.

  Bit [6] of the reset setting (KRES) indicates the setting of the activation method of the watchdog timer (WDT) 506b. In the example shown in FIG. 13, if the bit value in the reset setting (KRES) bit [6] is “0”, the watch is automatically set based on the fact that the user mode is entered when a reset occurs regardless of the user program. The dog timer (WDT) 506b is activated and time measurement is started. On the other hand, if the bit value in the bit [6] of the reset setting (KRES) is “1”, after shifting to the user mode, the watchdog timer (WDT) 506b is started by the software (user program) and time Measurement starts.

Bit [5-4] of the reset setting (KRES) indicates the setting of the reference clock signal of the watchdog timer (WDT) 506b. In the example illustrated in FIG. 13, when “00” is set in the bit [5-4] of the reset setting (KRES), 2 ¹⁵ × TSCLK is selected as the reference clock signal. Further, when “01” is set in the reset setting (KRES) bit [5-4], 2 ¹⁹ × TSCLK is selected as the reference clock signal. Further, when “10” is set in the bit [5-4] of the reset setting (KRES), 2 ²² × TSCLK is selected as the reference clock signal. Further, when “11” is set in the bit [5-4] of the reset setting (KRES), 2 ²⁵ × TSCLK is selected as the reference clock signal. SCLK indicates an internal system clock of the main control unit 41, and TSCLK indicates 1 / SCLK.

Bits [3-0] of the reset setting (KRES) indicate the setting of the timeout time of the watchdog timer (WDT) 506b. Specifically, the timeout time of the watchdog timer (WDT) 506b is set to the reference clock selected by the bit [5-4] of the reset setting (KRES) using the bits [3-0] of the reset setting (KRES). It is a value obtained by multiplying the set value. For example, when “1000” is set to the bit [3-0] of the reset setting (KRES) (that is, the value “8” is set), “00” is set to the bit [5-4] of the reset setting (KRES). When set, the timeout time is 2 ¹⁵ × TSCLK × 8, and when reset setting (KRES) bit [5-4] is set to “01”, the timeout time is 2 ¹⁹ × TSCLK × 8. When the reset setting (KRES) bit [5-4] is set to “10”, the timeout time is 2 ²² × TSCLK × 8, and the reset setting (KRES) bit [5-4] is set to “11”. If you set ", the timeout time is ^{2 25} × TSCLK × 8. Further, when “1111” is set to the bit [3-0] of the reset setting (KRES) (that is, the value “15” is set), “00” is set to the bit [5-4] of the reset setting (KRES). When set, the timeout time is 2 ¹⁵ × TSCLK × 15. When the reset setting (KRES) bit [5-4] is set to “01”, the timeout time is 2 ¹⁹ × TSCLK × 15. When the reset setting (KRES) bit [5-4] is set to “10”, the timeout time is 2 ²² × TSCLK × 15, and the reset setting (KRES) bit [5-4] is set to “11”. If set to "the timeout time is ^{2 25} × TSCLK × 15. FIG. 13 also shows specific examples of timeout values when the internal system clock is 10.0 MHz and 12.0 MHz.

  When setting so as not to use the watchdog timer (WDT) 506b, it is only necessary to set “0000” in bits [3-0] of the reset setting (KRES) as shown in FIG. However, even if the reset setting (KRES) bit [3-0] is set to “0000” and the watchdog timer (WDT) 506b is disabled, the reset setting (KRES) bit is set. By setting the value of [7], it is possible to set whether to perform system reset or user reset.

In this embodiment, “0” is set as the set value of bit [7] of the reset setting (KRES), and a user reset occurs when a time-out signal or an IAT signal is input. In addition, “0” is set as the set value of bit [6] of the reset setting (KRES), and the watchdog timer (automatically based on the transition to the user mode when a reset occurs regardless of the user program). WDT) 506b is activated and time measurement is started. In addition, “11” is set as the setting value of the bit [5-4] of the reset setting (KRES), and “1111” is set as the setting value of the bit [3-0] of the reset setting (KRES). (WDT) 506b ^{2 25} × TSCLK as a reference clock signal is selected, the timeout time is ^{2 25} × TSCLK × 15.

  16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2 (KRL2), and 16-bit random number initial setting 3 (KRL3) stored in the program management area indicate settings of the 16-bit random number circuit 508b. FIG. 14 shows an example of setting contents in 16-bit random number initial setting 1 (KRL1). FIG. 15 shows an example of setting contents in 16-bit random number initial setting 2 (KRL2). Further, FIG. 16 shows an example of setting contents in 16-bit random number initial setting 3 (KRL3).

  First, the setting contents in 16-bit random number initial setting 1 (KRL1) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 1 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 14, if the bit value of the bit “7” of the 16-bit random number initial setting 1 (KRL1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. As a result, the 16-bit random number circuit 508b of channel 1 is activated. On the other hand, if the bit value in bit “7” of 16-bit random number initial setting 1 (KRL1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 1 is activated.

  Bit “6” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 1. In the example shown in FIG. 14, if the bit value of bit “6” of 16-bit random number initial setting 1 (KRL1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 16-bit random number initial setting 1 (KRL1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 described above is input via the random number external clock terminal (RCK terminal), and the random number clock RCLK is divided by two. The signal is used as an update clock. The same applies to the 16-bit random number circuit 508b and the 8-bit random number circuit 508a of other channels.

  Bit “5-4” of 16-bit random number initial setting 1 (KRL1) indicates whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 1. In the example shown in FIG. 14, if the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is not changed. . If the bit value in bit “5-4” of 16-bit random number initial setting 1 (KRL1) is “01”, the random number sequence updated by 16-bit random number circuit 508b of channel 1 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In the present embodiment, “1” is set as the setting value of bit “7” of 16-bit random number initial setting 1 (KRL1), and based on the fact that the user mode is entered when a reset occurs regardless of the user program. The 16-bit random number circuit 508b for channel 1 is automatically activated. Further, “1” is set as the set value of bit “6” of 16-bit random number initial setting 1 (KRL1), and a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is a channel. 1 is used as an update clock for the 16-bit random number circuit 508b. Also, “10” is set as the set value of bits “5-4” of 16-bit random number initial setting 1 (KRL1), and the random number sequence updated by the 16-bit random number circuit 508b of channel 1 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 0 among the 16-bit random number circuit 508b of 4 channels. In the example shown in FIG. 14, if the bit value in the bit “3” of the 16-bit random number initial setting 1 (KRL1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the channel 0 16-bit random number circuit 508b is activated. On the other hand, if the bit value in bit “3” of 16-bit random number initial setting 1 (KRL1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 0 is activated.

  Bit “2” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 0. In the example illustrated in FIG. 14, if the bit value in the bit “2” of the 16-bit random number initial setting 1 (KRL1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 1 (KRL1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bits “1-0” of 16-bit random number initial setting 1 (KRL1) indicate whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 0. In the example shown in FIG. 14, if the bit value in the bit “1-0” of 16-bit random number initialization 1 (KRL1) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of channel 0 is not changed. . If the bit value in bits “1-0” of 16-bit random number initialization 1 (KRL1) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of channel 0 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 0 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 0 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In the present embodiment, “1” is set as the set value of bit “3” of 16-bit random number initial setting 1 (KRL1), and based on the transition to the user mode when a reset occurs regardless of the user program. The channel 0 16-bit random number circuit 508b is automatically activated. Also, “1” is set as the set value of bit “2” of 16-bit random number initial setting 1 (KRL1), and the signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is the channel. This is used as an update clock for the 0 16-bit random number circuit 508b. Also, “10” is set as the setting value of bits “1-0” of 16-bit random number initial setting 1 (KRL1), and the random number sequence updated by the 16-bit random number circuit 508b of channel 0 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in 16-bit random number initial setting 2 (KRL2) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 3 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 15, if the bit value in bit “7” of 16-bit random number initial setting 2 (KRL2) is “0”, the maximum random number is set by software (user program) after shifting to the user mode. Is activated, the 16-bit random number circuit 508b of channel 3 is activated. On the other hand, if the bit value in bit “7” of 16-bit random number initial setting 2 (KRL2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 3 is activated.

  Bit “6” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 3. In the example shown in FIG. 15, if the bit value of bit “6” of 16-bit random number initialization 2 (KRL2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 16-bit random number initial setting 2 (KRL2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bit “5-4” of 16-bit random number initial setting 2 (KRL2) indicates whether or not the random number sequence updated by the 16-bit random number circuit 508b of channel 3 is changed. In the example shown in FIG. 15, if the bit value in the bit “5-4” of the 16-bit random number initialization 2 (KRL2) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is not changed. . If the bit value in bit “5-4” of 16-bit random number initialization 2 (KRL2) is “01”, the random number sequence updated by 16-bit random number circuit 508b of channel 3 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 16-bit random number initial setting 2 (KRL2) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in bit “5-4” of 16-bit random number initialization 2 (KRL2) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of channel 3 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In this embodiment, “0” is set as the setting value of the bit “7” of the 16-bit random number initial setting 2 (KRL2). After shifting to the user mode, the maximum random number value is set by software (user program). Is set to start the 16-bit random number circuit 508b of channel 3, but the maximum value is not set by software for the 16-bit random number circuit 508b of channel 3 as described later. Thus, the setting is unused so that the 16-bit random number circuit 508b of channel 3 is not activated. Also, “1” is set as the set value of bit “6” of 16-bit random number initial setting 2 (KRL2), and a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is a channel. 3 is used as an update clock for the 16-bit random number circuit 508b. Also, “10” is set as the setting value of the bit “5-4” of the 16-bit random number initial setting 2 (KRL2), and the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. That is, by setting the bit “7” of the 16-bit random number initial setting 2 (KRL2) to “0” and not setting the maximum value of the 16-bit random number circuit 508b of the channel 3 by software, the 16-bit random number circuit 508b of the channel 3 is set. However, the setting of the update clock of the 16-bit random number circuit 508b of channel 3 and the setting of whether or not to change the random number sequence to be updated are the initial values (the values at the time of shipment (all 0) ), And the same setting as that of the 16-bit random number circuit 508b of channels 0 and 1, which is not an unused setting.

  Bit “3” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 2 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 15, if the bit value in the bit “3” of the 16-bit random number initial setting 2 (KRL2) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the 16-bit random number circuit 508b of channel 2 is activated. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 2 (KRL2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 2 is activated.

  Bit “2” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 2. In the example shown in FIG. 15, if the bit value of bit “2” of 16-bit random number initial setting 2 (KRL2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 2 (KRL2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bits “1-0” of 16-bit random number initial setting 2 (KRL2) indicate whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 2. In the example shown in FIG. 15, if the bit value in the bit “1-0” of 16-bit random number initialization 2 (KRL2) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is not changed. . If the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is changed by software (user program). it can. If the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is automatically updated from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 16-bit random number initial setting 2 (KRL2) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 2 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In this embodiment, “0” is set as the setting value of the bit “3” of the 16-bit random number initial setting 2 (KRL2), and after the transition to the user mode, the maximum value of the random number is set by software (user program). Is set to start the 16-bit random number circuit 508b of channel 2, but the maximum value is not set by software for the 16-bit random number circuit 508b of channel 2 as will be described later. Thus, the setting is unused so that the 16-bit random number circuit 508b of channel 2 is not activated. Also, “1” is set as the set value of bit “2” of 16-bit random number initial setting 2 (KRL2), and the signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is the channel. 2 is used as an update clock for the 16-bit random number circuit 508b. Also, “10” is set as the setting value of bits “1-0” of 16-bit random number initial setting 2 (KRL2), and the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. That is, by setting the bit “3” of the 16-bit random number initial setting 2 (KRL2) to “0” and not setting the maximum value of the 16-bit random number circuit 508b of the channel 2 by software, the 16-bit random number circuit 508b of the channel 2 is set. However, the setting of the update clock of the 16-bit random number circuit 508b of channel 2 and the setting of whether or not to change the random number sequence to be updated are the initial values (the values at the time of shipment (all 0) ), And the same setting as that of the 16-bit random number circuit 508b of channels 0 and 1, which is not an unused setting.

  Next, setting contents in 16-bit random number initial setting 3 (KRL3) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 3 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value at bit “7” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “7” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used. Since the ID number of the main control unit 41 is different for each chip, it is possible to make it difficult to predict the update timing of the random number by using a value based on the ID number as the start value, and aim for the update timing of the random number. Thus, it is possible to prevent acts that illegally generate jackpots. The ID number itself may be used as a value based on the ID number, or a predetermined calculation (for example, a value obtained by adding or subtracting a predetermined value) may be used for the ID number.

  Bit “6” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 3 is changed at every system reset. In the example shown in FIG. 16, if the bit value of bit “6” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  In this embodiment, “1” is set as the setting value of the bit “7” of the 16-bit random number initial setting 3 (KRL3), and the start value of the first round of the random number update of the 16-bit random number circuit 508b of the channel 3 is set. A value based on the ID number of the main control unit 41 is used. Further, “1” is set as the set value of the bit “6” of the 16-bit random number initial setting 3 (KRL3), and the start value of the 16-bit random number circuit 508b of the channel 3 is changed at every system reset. That is, by setting the bit “7” of the 16-bit random number initial setting 2 (KRL2) to “0” and not setting the maximum value of the 16-bit random number circuit 508b of the channel 3 by software, the 16-bit random number circuit 508b of the channel 3 is set. However, the start value setting from the first round of the 16-bit random number circuit 508b of channel 3 is not the initial value (the factory default value (all 0)), The same setting as the 16-bit random number circuit 508b of the non-channel 0 and 1 is made.

  Bit “5” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 2 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value at bit “5” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “5” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used.

  Bit “4” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 2 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “4” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  In this embodiment, “1” is set as the setting value of the bit “5” of the 16-bit random number initial setting 3 (KRL3), and the start value of the first round of the random number update of the 16-bit random number circuit 508b of the channel 2 is set. A value based on the ID number of the main control unit 41 is used. Further, “1” is set as the set value of the bit “4” of the 16-bit random number initial setting 3 (KRL3), and the start value of the 16-bit random number circuit 508b of the channel 2 is changed at every system reset. That is, by setting the bit “3” of the 16-bit random number initial setting 2 (KRL2) to “0” and not setting the maximum value of the 16-bit random number circuit 508b of the channel 2 by software, the 16-bit random number circuit 508b of the channel 2 is set. However, the start value setting from the first round of the 16-bit random number circuit 508b of channel 2 is not the initial value (factory value (all 0)), The same setting as the 16-bit random number circuit 508b of the non-channel 0 and 1 is made.

  Bit “3” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 1 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value in bit “3” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used.

  Bit “2” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 1 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “2” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  In this embodiment, “1” is set as the set value of bit “3” of 16-bit random number initial setting 3 (KRL3), and the start value of the first round of random number update of the 16-bit random number circuit 508b of channel 1 A value based on the ID number of the main control unit 41 is used. Also, “1” is set as the setting value of bit “2” of 16-bit random number initial setting 3 (KRL3), and the start value of the 16-bit random number circuit 508b of channel 1 is changed at each system reset.

  Bit “1” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 0 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value at bit “1” of 16-bit random number initialization 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value of the bit “1” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the main control unit 41 is used as the start value for the first round of random number update. The value set to is used.

  Bit “0” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 0 is changed at every system reset. In the example shown in FIG. 16, if the bit value in bit “0” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “0” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  In this embodiment, “1” is set as the setting value of bit “1” of 16-bit random number initial setting 3 (KRL3), and the start value of the first round of random number update of the 16-bit random number circuit 508b of channel 0 A value based on the ID number of the main control unit 41 is used. Further, “1” is set as the set value of bit “0” of 16-bit random number initial setting 3 (KRL3), and the start value of the 16-bit random number circuit 508b of channel 0 is changed at each system reset.

  The 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) stored in the program management area indicate settings of the 8-bit random number circuit 508a. FIG. 17 shows an example of setting contents in the 8-bit random number initial setting 1 (KRS1). FIG. 18 shows an example of setting contents in the 8-bit random number initial setting 2 (KRS2).

  First, the setting contents in 8-bit random number initial setting 1 (KRS1) will be described with reference to FIG. Bit “7” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 1 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 17, if the bit value in the bit “7” of the 8-bit random number initial setting 1 (KRS1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. As a result, the 8-bit random number circuit 508a of channel 1 is activated. On the other hand, if the bit value in the bit “7” of the 8-bit random number initial setting 1 (KRS1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 8-bit random number circuit 508a of channel 1 is activated.

  Bit “6” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 1. In the example shown in FIG. 17, if the bit value of bit “6” of 8-bit random number initial setting 1 (KRS1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 8-bit random number initial setting 1 (KRS1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bit “5-4” of 8-bit random number initial setting 1 (KRS1) indicates whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 1. In the example shown in FIG. 17, if the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is not changed. . If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of channel 1 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In this embodiment, “0” is set as the setting value of the bit “7” of the 8-bit random number initial setting 1 (KRS1). After shifting to the user mode, the maximum random number value is set by software (user program). Is set to activate the channel 1 8-bit random number circuit 508a. However, as described later, the maximum value is not set by software for the channel 1 8-bit random number circuit 508a. Thus, the setting is unused so that the 8-bit random number circuit 508a of channel 1 is not activated. Further, “1” is set as the set value of bit “6” of 8-bit random number initial setting 1 (KRS1), and a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is a channel. 1 is used as an update clock for the 8-bit random number circuit 508a. Also, “10” is set as the set value of bits “5-4” of 8-bit random number initial setting 1 (KRS1), and the random number sequence updated by the 8-bit random number circuit 508a of channel 1 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. That is, by setting the bit “7” of the 8-bit random number initial setting 1 (KRS1) to “0” and not setting the maximum value of the 8-bit random number circuit 508a of the channel 1 by software, the 8-bit random number circuit 508a of the channel 1 is set. However, the setting of the update clock of the 8-bit random number circuit 508a of channel 1 and the setting of whether or not to change the random number sequence to be updated are the initial values (the values at the time of shipment (all 0) ), And the same setting as that of the 16-bit random number circuit 508b of channels 0 and 1, which is not an unused setting.

  Bit “3” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 0 out of the 4-channel 8-bit random number circuit 508a. In the example shown in FIG. 17, if the bit value in the bit “3” of the 8-bit random number initial setting 1 (KRS1) is “0”, after entering the user mode, the maximum random number value is set by software (user program). As a result, the 8-bit random number circuit 508a of channel 0 is activated. On the other hand, if the bit value in the bit “3” of the 8-bit random number initial setting 1 (KRS1) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 0 is activated.

  Bit “2” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 0. In the example shown in FIG. 17, if the bit value in the bit “2” of the 8-bit random number initial setting 1 (KRS1) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 8-bit random number initial setting 1 (KRS1) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by two is used. Used as an update clock.

  Bits “1-0” of 8-bit random number initial setting 1 (KRS1) indicate whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 0. In the example shown in FIG. 17, if the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 0 is not changed. . If the bit value in bits “1-0” of 8-bit random number initial setting 1 (KRS1) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 0 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in bits “1-0” of the 8-bit random number initial setting 1 (KRS1) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In this embodiment, “0” is set as the setting value of the bit “3” of the 8-bit random number initial setting 1 (KRS1). After shifting to the user mode, the maximum random number is set by software (user program). Is set to activate the channel 0 8-bit random number circuit 508a, but the maximum value is not set by software for the channel 0 8-bit random number circuit 508a, as will be described later. Thus, the setting is unused so that the 8-bit random number circuit 508a of channel 0 is not activated. Also, “1” is set as the setting value of bit “2” of 8-bit random number initial setting 1 (KRS1), and a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is a channel. It is used as an update clock for the 0 8-bit random number circuit 508a. Also, “10” is set as the set value of bits “1-0” of 8-bit random number initial setting 1 (KRS1), and the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. That is, by setting the bit “3” of the 8-bit random number initial setting 1 (KRS1) to “0” and not setting the maximum value of the 8-bit random number circuit 508a of the channel 0 by software, the 8-bit random number circuit 508a of the channel 0 is set. However, the setting of the update clock of the 8-bit random number circuit 508a of channel 0 and the setting of whether or not to change the random number sequence to be updated are the initial values (the values at the time of shipment (all 0) ), And the same setting as that of the 16-bit random number circuit 508b of channels 0 and 1, which is not an unused setting.

  Next, setting contents in the 8-bit random number initial setting 2 (KRS2) will be described with reference to FIG. Bit “7” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 3 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 18, if the bit value of the bit “7” of the 8-bit random number initial setting 2 (KRS2) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the 8-bit random number circuit 508a of channel 3 is activated. On the other hand, if the bit value in the bit “7” of the 8-bit random number initial setting 2 (KRS2) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 3 is activated.

  Bit “6” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the update clock of the 8-bit random number circuit 508a of the channel 3. In the example shown in FIG. 18, if the bit value of bit “6” of 8-bit random number initial setting 2 (KRS2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 8-bit random number initial setting 2 (KRS2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is obtained. Used as an update clock.

  Bit “5-4” of 8-bit random number initial setting 2 (KRS2) indicates whether to change the random number sequence updated by 8-bit random number circuit 508a of channel 3. In the example shown in FIG. 18, if the bit value in the bit “5-4” of the 8-bit random number initialization 2 (KRS2) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is not changed. . If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically updated from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In this embodiment, “0” is set as the setting value of the bit “7” of the 8-bit random number initial setting 2 (KRS2), and after the transition to the user mode, the maximum random number is set by software (user program). Is set to activate the 8-bit random number circuit 508a of channel 3, but the maximum value is not set by software for the 8-bit random number circuit 508a of channel 1 as will be described later. Thus, the setting is unused so that the 8-bit random number circuit 508a of channel 3 is not activated. Also, “1” is set as the set value of bit “6” of 8-bit random number initial setting 2 (KRS2), and a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is a channel. 3 is used as an update clock for the 8-bit random number circuit 508a. Further, “10” is set as the setting value of the bit “5-4” of the 8-bit random number initial setting 2 (KRS2), and the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. That is, by setting the bit “7” of the 8-bit random number initial setting 2 (KRS2) to “0” and not setting the maximum value of the 8-bit random number circuit 508a of the channel 3 by software, the 8-bit random number circuit 508a of the channel 3 is set. However, the setting of the update clock of the 8-bit random number circuit 508a of channel 3 and the setting of whether or not to change the random number sequence to be updated are the initial values (the values at the time of shipment (all 0) ), And the same setting as that of the 16-bit random number circuit 508b of channels 0 and 1, which is not an unused setting.

  Bit “3” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 2 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 18, if the bit value in the bit “3” of the 8-bit random number initial setting 2 (KRS2) is “0”, after the transition to the user mode, the maximum random number is set by software (user program). Is activated, the channel 2 8-bit random number circuit 508a is activated. On the other hand, if the bit value in the bit “3” of the 8-bit random number initial setting 2 (KRS2) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 2 is activated.

  Bit “2” of 8-bit random number initial setting 2 (KRS2) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 2. In the example shown in FIG. 18, if the bit value of bit “2” of 8-bit random number initial setting 2 (KRS2) is “0”, the internal system clock of the main control unit 41 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 8-bit random number initial setting 2 (KRS2) is “1”, a signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is obtained. Used as an update clock.

  Bits “1-0” of 8-bit random number initial setting 2 (KRS2) indicate whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 2. In the example shown in FIG. 18, if the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is not changed. . If the bit value in bits “1-0” of the 8-bit random number initial setting 2 (KRS2) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of channel 2 is changed by software (user program). it can. Further, if the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is automatically set from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  In this embodiment, “0” is set as the setting value of the bit “3” of the 8-bit random number initial setting 2 (KRS2). After shifting to the user mode, the maximum random number value is set by software (user program). Is set to activate the channel 2 8-bit random number circuit 508a, but the maximum value is not set by software for the channel 2 8-bit random number circuit 508a, as will be described later. Thus, the setting is unused so that the 8-bit random number circuit 508a of channel 2 is not activated. Also, “1” is set as the setting value of bit “2” of 8-bit random number initial setting 2 (KRS2), and the signal obtained by dividing the external clock signal input from the outside of the main control unit 41 by 2 is the channel. 2 as an update clock for the 8-bit random number circuit 508a. Also, “10” is set as the setting value of bits “1-0” of 8-bit random number initial setting 2 (KRS2), and the random number sequence updated by the 8-bit random number circuit 508a of channel 2 is automatically started from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. That is, by setting the bit “3” of the 8-bit random number initial setting 2 (KRS2) to “0” and not setting the maximum value of the 8-bit random number circuit 508a of the channel 2 by software, the 8-bit random number circuit 508a of the channel 2 is set. However, the setting of the update clock of the 8-bit random number circuit 508a of channel 2 and the setting of whether or not to change the random number sequence to be updated are the initial values (the values at the time of shipment (all 0) ), And the same setting as that of the 16-bit random number circuit 508b of channels 0 and 1, which is not an unused setting.

  Note that the 8-bit random number circuit 508a does not have a function for setting a start value as shown in FIG. 16, unlike the 16-bit random number circuit 508b.

  The security time setting (KSES) stored in the program management area indicates a time setting for extending the security mode. FIG. 19 shows an example of setting contents in the security time setting (KSES).

  Bit [7-6] of the security time setting (KSES) indicates the setting of the time for extending the security mode time at random. In the example shown in FIG. 19, when “01” is set in the bit [7-6] of the security time setting (KSES), the short mode is set as a mode for extending the security mode time at random. Specifically, when the internal system clock is 10.0 MHz, the time in the range of 0 to 0.816 ms is randomly extended, and when the internal system clock is 12.0 MHz, the range of 0 to 0.51 ms. The time is extended randomly. Further, when “10” is set in the bit [7-6] of the security time setting (KSES), the middle mode is set as a mode in which the security mode time is randomly extended. When the system clock is 10.0 MHz, the time in the range of 0 to 26.112 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 16.32 ms is randomly selected. Extended. Further, when “11” is set in the bit [7-6] of the security time setting (KSES), the long mode is set as a mode for randomly extending the security mode time. When the system clock is 10.0 MHz, the time in the range of 0 to 855.584 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 522.24 ms is randomly selected. Extended.

  When setting so as not to perform random extension of the security mode time, as shown in FIG. 19, the bit [7-6] of the security time setting (KSES) may be set to “00”.

  In this embodiment, “11” is set as the set value of bits [7-6] of the security time setting (KSES), the long mode is set as a mode for extending the security mode time at random, and the internal system When the clock is 10.0 MHz, the time in the range of 0 to 855.584 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 522.24 ms is randomly extended. Is done.

Bit [5] of the security time setting (KSES) indicates the setting of the reference clock signal for the time for fixing and extending the security mode time. In the example shown in FIG. 19, when “0” is set in bit [5] of the security time setting (KSES), 2 ²² × TSCLK is selected as the reference clock signal. When “1” is set in bit [5] of the security time setting (KSES), 2 ²⁴ × TSCLK is selected as the reference clock signal.

Bits [4-0] of the security time setting (KSES) indicate a time setting for extending the security mode time in a fixed manner. Specifically, the fixed extension time of the security mode time is the set value set by the bit [4-0] of the security time setting (KSES) to the reference clock selected by the bit [5] of the security time setting (KSES). Is the value multiplied by. For example, when “00001” is set in the bit [4-0] of the security time setting (KSES) (that is, the value “1” is set), “0” is set in the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 1, and when “1” is set in bit [5] of the security time setting (KSES), the fixed extension time is 2 ²⁴ × TSCLK × 1. It becomes. Further, when “01000” is set in the bit [4-0] of the security time setting (KSES) (that is, the value “8” is set), “0” is set in the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 8, and when “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 2 ²⁴ × TSCLK × 8. It becomes. Also, when “10000” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “16” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 16, and when the security time setting (KSES) bit [5] is set to “1”, the fixed extension time is 2 ²⁴ × TSCLK × 16. It becomes. Further, when “11111” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “31” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 2 ²² × TSCLK × 31. When “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 2 ²⁴ × TSCLK × 31. It becomes. FIG. 19 also shows specific examples of fixed extension time values when the internal system clock is 10.0 MHz and 12.0 MHz.

  When setting so that the security mode time is not fixedly extended, “00000” may be set to bits [4-0] of the security time setting (KSES) as shown in FIG.

  In this embodiment, “0” is set as the setting value of bit [5] of the security time setting (KSES), and “00000” is set as the setting value of bits [4-0] of the security time setting (KSES). The security mode time is not fixed and extended.

  As shown in FIG. 19, the security mode time is randomly extended by setting bit [7-6] of security time setting (KSES) and fixed extension by setting of bit [5-0] of security time setting (KSES). The extension can be set in two ways. And the addition time of the time set by these two types of methods becomes the extension time of the final security mode time.

  The random number clock monitoring setting (KRCS) stored in the program management area indicates the setting of the monitoring frequency of the external clock signal input from the random number external clock terminal (RCK terminal). FIG. 20 shows an example of setting contents in the random number clock monitoring setting (KRCS).

  Bit [7-2] of the random number clock monitoring setting (KRCS) is a fixed bit (that is, a bit that is not particularly used for setting), and all bits are always set to “0”.

Bits [1-0] of the random number clock monitoring setting (KRCS) are input clocks when an external clock signal input from the random number external clock terminal (RCK terminal) is selected as a clock for updating the random number. The setting of the frequency used as the detection target of frequency anomalies is shown. In the example shown in FIG. 20, when “00” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock). When “01” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock) / 2. Further, when "10" is set to bits [1-0] of the random number clock monitoring settings (KRCS) sets the frequency lower than the SCLK (internal system clock) / ^{2 2} as the monitoring frequency. Further, when "11" is set to bits [1-0] of the random number clock monitoring settings (KRCS) sets the SCLK frequency lower than the (internal system clock) / ^{2 3} as a monitoring frequency.

In this embodiment, “10” is set as the set value of bits [1-0] of the random number clock monitoring setting (KRCS), and the monitoring frequency is set to less than the frequency of SCLK (internal system clock) / 2 ^2. The

  When an abnormality in the monitoring frequency of the external clock signal input from the random number external clock terminal (RCK terminal) is detected, “1” is set in bit 3 of the internal information register (CIF) described later.

  In this embodiment, the main control unit 41 has a function of detecting an operation abnormality (external clock frequency abnormality) of the 16-bit random number circuit 508b out of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b. Yes. Specifically, the main control unit 41 is set in the random number clock monitoring setting (KRCS) when the external clock signal input from the random number external clock terminal (RCK terminal) is selected as the random number update clock. Based on the monitored frequency, it is detected whether or not the frequency of the external clock signal has decreased, and when the frequency of the external clock signal has been decreased (external clock frequency abnormality), an internal information register (CIF) (to be described later) ) Is set to “1”.

  Further, the main control unit 41 has a function of monitoring the update state of the random number of the 16-bit random number circuit 508b, and when an abnormality is detected in the update state (for example, the random number value is not updated with the same value or is normally disturbed). When the value of the random number is counted up one by one but the value of the random number is suddenly increased by 2 or more), the corresponding bit of bits 7 to 4 of the internal information register (CIF) Set “1” to.

  In this embodiment, the 16-bit random number circuit 508b for channels 2 and 3 is set to be unused. However, even when an update abnormality of the 16-bit random number circuit 508b for channels 2 and 3 is detected, the internal information register ( "1" is set to the corresponding bit of the corresponding bits 7 and 6 of the CIF), and the internal information register ( By acquiring the value of (CIF), it is possible to confirm whether or not an abnormality in the update state has been detected.

  In particular, in this embodiment, the CPU 41a acquires the value of the internal information register (CIF) in an error determination process performed at a predetermined trigger (for example, at startup, every predetermined interval, once per game, etc.) It is determined whether or not the value of the information register (CIF) is 0, and other than 0, that is, any bit of the internal information register (CIF) is set to “1”, and an abnormal frequency of the external clock signal is detected. Whether the update state is detected in any of the channels 0 to 3 and the 16-bit random number circuit 506b of the 8-bit random number circuit 506a. Control is made to an error state, the progress of the game is disabled, and a notification that a random number abnormality has occurred is made.

  This embodiment shows a case where the monitoring frequency of the external clock signal to be monitored is set with respect to detection of an abnormal operation of the 16-bit random number circuit 508b by setting using the random number clock monitoring setting (KRCS). However, it may be configured to be able to set whether or not to detect the external clock frequency abnormality itself, or to be able to set whether or not to detect the update abnormality itself. In this case, it may be configured such that the setting of whether or not the external clock frequency abnormality detection itself is performed and the setting of whether or not the update abnormality detection itself is performed can be performed independently. It is also possible to configure such that only can be enabled or disabled collectively.

  In the present embodiment, a dedicated random number clock RCLK is externally input to the random number circuits 508a and 508b from the random number clock generation circuit 43. For example, a control clock from the control clock generation circuit 42 is shown. Even when a clock other than the dedicated random number clock RCLK is externally input, such as when CCLK is externally input, it is possible to detect an external clock frequency abnormality or update abnormality. Regarding detection of update abnormality in the random number circuit, other clocks such as a random number update using a dedicated random number clock RCLK from the random number clock generation circuit 43 and a control clock CCLK from the control clock generation circuit 42 are used. It may be configured so that it can be set only in either of the cases where random number is updated by using.

  In the present embodiment, the CPU 41a acquires the value of the internal information register (CIF), determines whether the value of the internal information register (CIF) is 0, and determines an error when the value is other than 0. That is, the specific error cause is not specified, but the error cause may be specified from the value of the internal information register (CIF), and the cause may be notified so that the cause can be recognized.

  Further, in this embodiment, the abnormality of the external clock frequency is detected, and the abnormality of the frequency of the internal system clock SCLK of the main control unit 41 is not particularly detected, for the following reason. That is, when the internal system clock SCLK is used for updating the random number, the operation of the CPU 41a itself should have stopped in a situation where an abnormality has occurred in the internal system clock SCLK. However, there is no case where only the update of the random number is stopped, and there is no possibility that some problem will occur. On the other hand, when an external clock signal is used for the random number update, there is a possibility that only the update of the random number is stopped even though the CPU 41a is operating, which may cause an adverse effect. It is.

  The reset / interrupt controller 506 uses the internal information register CIF (address FE25H) among the built-in registers included in the main control unit 41 as shown in FIGS. 8 to 10 to control interrupts and manage resets. Do. The internal information register CIF is a register for managing a reset factor generated immediately before, reading a random number update state, and a state of an input frequency when the random number update clock is an external clock.

  FIG. 21A shows a configuration example of the internal information register CIF. FIG. 21B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data RL3ER stored in the bit number [7] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL3 updated by the 16-bit random number circuit 508b of the channel 3. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL3 is not detected, the bit value of the internal information data RL3ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL3 is detected. The bit value is “1”. The internal information data RL2ER stored in the bit number [6] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL2 updated by the 16-bit random number circuit 508b of the channel 2. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL2 is not detected, the bit value of the internal information data RL2ER becomes “0”, while when the update abnormality of the 16-bit random number RL2 is detected. The bit value is “1”. The internal information data RL1ER stored in the bit number [5] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL1 updated by the 16-bit random number circuit 508b of the channel 1. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL1 is not detected, the bit value of the internal information data RL1ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL1 is detected. The bit value is “1”. The internal information data RL0ER stored in the bit number [4] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL0 updated by the 16-bit random number circuit 508b of the channel 0. In the example shown in FIG. 21B, when the update abnormality of the 16-bit random number RL0 is not detected, the bit value of the internal information data RL0ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL0 is detected. The bit value is “1”. The bit number [7-4] of the internal information register CIF is set to “0” as an initial value.

  As described above, the 16-bit random number circuit 508b for the channels 2 and 3 is set to be unused, but the internal information register ( "1" is set to the corresponding bit of the corresponding bits 7 and 6 of the CIF), and the internal information register ( By acquiring the value of (CIF), it is possible to confirm whether or not an abnormality in the update state has been detected.

  The internal information data RCER stored in the bit number [3] of the internal information register CIF is obtained when the external clock signal input from the random number external clock terminal (RCK terminal) is selected as the random number update clock. Indicates a frequency error in the external clock signal. In the example shown in FIG. 21B, when the frequency abnormality of the external clock signal is not detected, the bit value of the internal information data RCER becomes “0”, while when the frequency abnormality of the external clock signal is detected, The bit value is “1”. The bit number [3] of the internal information register CIF is set to “0” as an initial value.

  The internal information data SRSF stored in the bit number [2] of the internal information register CIF indicates that the reset factor generated immediately before is a system reset. In the example shown in FIG. 21B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data SRSF is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”. The bit number [2] of the internal information register CIF is set to “1” as an initial value.

  The internal information data WDTF stored in the bit number [1] of the internal information register CIF indicates that the reset factor generated immediately before is a user reset due to the input of a time-out signal from the watchdog timer (WDT) 506b. In the example shown in FIG. 21B, when the reset factor immediately before is not a user reset by the timeout signal (user reset by the timeout signal has not occurred), the bit value of the internal information data WDTF becomes “0”, while the timeout occurs. When it is a user reset by a signal (a user reset is generated by a timeout signal), the bit value becomes “1”. The bit number [1] of the internal information register CIF is set to “0” as an initial value.

  Internal information data IATF stored in bit number [0] of internal information register CIF indicates that the reset factor generated immediately before is a user reset due to the input of an IAT generation signal from IAT circuit 506a. In the example shown in FIG. 21B, when the immediately preceding reset factor is not a user reset by the IAT generation signal (user reset has not occurred by the IAT generation signal), the bit value of the internal information data IATF becomes “0”. When the user reset is performed by the IAT generation signal (user reset is generated by the IAT generation signal), the bit value is “1”. The bit number [0] of the internal information register CIF is set to “0” as an initial value.

  FIG. 22 is a block diagram illustrating a configuration example of the 8-bit random number circuit 508a. FIG. 23 is a block diagram illustrating a configuration example of the 16-bit random number circuit 508b. As shown in FIGS. 22 and 23, the 8-bit random number circuit 508a and the 16-bit random number circuit 508b include a random number sequence change selection circuit 523a, 523b, a random number generation circuit 525a, 525b, a random number sequence change circuit 526a, 526b, and a maximum value. Comparing circuits 527a and 527b are provided. In addition to the components included in the 8-bit random number circuit 508a, the 16-bit random number circuit 508b includes a random number start value selection circuit 535, as shown in FIG. Further, as shown in FIG. 23, the 16-bit random number circuit 508b includes an update monitoring circuit 537 in addition to the components included in the 8-bit random number circuit 508a.

  In the example shown in FIG. 23, only the configuration of the circuit portion of the 16-bit random number circuit 508b is shown, and description of each register used by the 16-bit random number circuit 508b other than the random number sequence change register 522 and the maximum value setting register 524b is omitted. doing. Specifically, the 16-bit random number circuit 508b replaces the RS hard latch selection registers 528a and 528b shown in FIG. 22 with RL0 hard latch selection registers 0 (RL0LS0) to RL3 hard latch selection registers (RL3LS) shown in FIG. ), Instead of the RS0 hard latch random value register 529a to RS3 hard latch random value register 529d shown in FIG. 22, the RL0 hard latch random value register 0 (RL0HV0) to RL3 hard latch random value register shown in FIGS. 1 (RL3HV1) is used, and instead of the RS hard latch flag register 530 shown in FIG. 22, RL hard latch flag register 0 (RLHF0) to RL hard latch flag register 1 (RLHF1) shown in FIG. Instead of RS interrupt control register 531 RL interrupt control register 0 (RLIC0) to RL interrupt control register 1 (RLIC1) shown in FIG. 8 are used instead of RS0 soft latch random value register 533a to RS3 soft latch random value register 533d shown in FIG. 9, RL0 soft latch random value register (RL0SV) to RL3 soft latch random value register (RL3SV) are used. The 16-bit random number circuit 508b uses the same register as the 8-bit random number circuit 508a for the random value soft latch register 532 and the random number soft latch flag register 534.

  The 8-bit random number circuit 508a is an 8-bit random number initial setting 521a (8-bit random number initial setting 1 (KRS1) and 8-bit random number initial setting 2 (KRS2) shown in FIG. 7) provided in the program management area already described. Operates according to the set contents.

  The 16-bit random number circuit 508b is a 16-bit random number initial setting 521b (16-bit random number initial setting 1 (KRL1) to 16-bit random number initial setting 2 (KRL2) shown in FIG. 7) provided in the program management area already described. Operates according to the set contents. In addition to the function of the 8-bit random number circuit 508a, the 16-bit random number circuit 508b sets the 16-bit random number initial setting 536 (16-bit random number initial setting 3 (KRL3) shown in FIG. 7). By operating according to the contents, it has a function of changing the start value of the random number value in the first round (see FIG. 16).

  Further, in the 16-bit random number circuit 508b, the random number generation circuit 525b includes an update monitoring circuit 537. In addition to the function of the 8-bit random number circuit 508a, the update monitoring circuit 537 operates to cause an external clock frequency abnormality and an update abnormality. (See FIG. 20). In this embodiment, the case where both the external clock frequency abnormality and the update abnormality are detected by one update monitoring circuit 537 is shown, but the monitoring circuit for detecting the external clock frequency abnormality and the monitoring circuit for detecting the update abnormality are shown. And may be provided separately.

  The 8-bit random number circuit 508a may also be configured to include an update monitoring circuit so that an external clock frequency abnormality and an update abnormality of the 8-bit random number circuit 508a can be detected.

  The random number sequence change register 522 corresponds to the random number sequence change register RDSC included in the built-in register of the main control unit 41 as shown in FIG. As the random number sequence change register RDSC, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The maximum value setting registers 524a and 524b correspond to the RS0 maximum value setting register (RS0MX) to the RS3 maximum value setting register (RS3MX) included in the built-in register of the main control unit 41 as shown in FIG. In the case of the 16-bit random number circuit 508b, it corresponds to the RL0 maximum value setting register (RL0MX) to the RL3 maximum value setting register (RL3MX)).

  The hard latch selection register 528a corresponds to the RS hard latch selection register 0 (RSLS0) included in the built-in register of the main control unit 41 as shown in FIG. The hard latch selection register 528b corresponds to the RS hard latch selection register 1 (RSLS1) included in the built-in register of the main control unit 41 as shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL0 hard latch selection register 0 (RL0LS0) to RL3 hard latch selection register 3 (RL3LS) shown in FIG.

  The RS0 hard latch random value registers 529a to RS3 hard latch random value registers 529d are RS0 hard latch random value registers (RS0HV) to RS3 hard latch random numbers included in the built-in registers of the main control unit 41 as shown in FIG. This corresponds to the register (RS3HV). In the case of the 16-bit random number circuit 508b, the RL0 hard latch random value register 0 (RL0HV0) to RL1 hard latch random value register 1 (RL1HV1) shown in FIG. 9 and the RL2 hard latch random value register 0 (RL2HV0) shown in FIG. ) To RL3 hard latch random number value register 1 (RL3HV1).

  The RS hard latch flag register 530 corresponds to the RS hard latch flag register (RSHF) shown in FIG. The 16-bit random number circuit 508b corresponds to the RL hard latch flag register 0 (RLHF0) to RL hard latch flag register 1 (RLHF1) shown in FIG.

  The RS interrupt control register 531 corresponds to the RS interrupt control register (RSIC) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL interrupt control register 0 (RLIC0) to the RL interrupt control register 1 (RLIC1) shown in FIG.

  The random number soft latch register 532 corresponds to the random number soft latch register (RDSL) shown in FIG. As the soft latch register RDSL, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The RS0 soft latch random value registers 533a to RS3 soft latch random value registers 533d correspond to the RS0 soft latch random value registers (RS0SV) to RS3 soft latch random value registers (RS3SV) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL0 soft latch random number value (RL0SV) to the RL3 soft latch random value (RL3SV) shown in FIG.

  The random number soft latch flag register 534 corresponds to the random number soft latch flag register (RDSF) shown in FIG. As the random number soft latch flag register RDSF, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The random number sequence change selection circuits 523a and 523b follow the setting contents of the 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) shown in FIGS. 17 and 18 (in the case of the 16-bit random number circuit 508b). According to the setting contents of 16-bit random number initial setting 1 (KRL1) and 16-bit random number initial setting 2 (KRL2) shown in FIG. 14 and FIG. 15, the change method of the random number sequence is “do not change”, “change by software” , “Automatically change from the second lap” or “Automatically change from the first lap” is selected. Then, when any one of “change by software”, “automatic change from the second round” or “automatic change from the first round” is selected, the random number sequence changing circuits 526a and 526b receive random numbers according to the selection method. Change the column. Further, when “Do not change” is selected, control for changing the random number sequence is not performed.

  The random number sequence changing circuits 526a and 526b are circuits that can change the permutation of the numerical data generated by the random number generating circuits 525a and 525b in accordance with instructions from the random number sequence change selecting circuits 523a and 523b. For example, when “change by software” is instructed, the random number sequence change circuits 526a and 526b change the random number sequence updated by the random number generation circuits 525a and 525b by software (user program). Further, for example, when the instruction “automatic change from the second round” is instructed, the random number sequence change circuits 526a and 526b automatically change the random number sequence updated by the random number generation circuits 525a and 525b from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. Further, for example, when “automatic change from the first round” is instructed, the random number sequence change circuits 526a and 526b automatically change the random number sequence updated by the random number generation circuits 525a and 525b from the first round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed.

  The random number generation circuits 525a and 525b are configured by, for example, an 8-bit counter (a 16-bit counter in the case of the 16-bit random number circuit 508b) and the like. In the range, the circuit cyclically updates from a predetermined initial value to a predetermined final value. For example, the random number generation circuits 525a and 525b are configured to add one by one from the initial value set within the range from “0” to “255” in response to the falling edge in the random number update clock signal. The numerical data is counted up (in the case of the 16-bit random number circuit 508b, the numerical data is incremented by 1 from the initial value set within the range of “0” to “65535” to “65535”. Count up) Then, after counting up to “255”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The maximum value comparison circuits 527a and 527b are set according to the setting contents of the 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) shown in FIG. 17 and FIG. In accordance with the setting contents of 16-bit random number initial setting 1 (KRL1) and 16-bit random number initial setting 2 (KRL2) shown in FIGS. 14 and 15, the maximum value of the random number values generated by the random number generation circuits 525a and 525b is set.

  FIG. 24A shows a configuration example of the RL0 hard latch selection register 0 (RL0LS0). FIG. 24B shows an example of setting contents in each bit of data stored in the RL0 hard latch selection register 0 (RL0LS0). The data RL01RF stored in the bit number [7] of the RL0 hard latch selection register 0 (RL0LS0) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 1 (RL0HV1) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 24B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL01RF becomes “0”. When the value is set to be latched, the bit value is “1”.

  In this embodiment, regarding the program management area and the register of the built-in register, specifically, by setting the corresponding bit in the program management area or the like to a value of “0” or “1”, the correspondence is made. The value of the bit to be read is read, and the read “0” or “1” value is written to the control register of the main control unit 41 by hardware, so that various settings are made.

  For bit 7 (RL01RF) of RL0 hard latch select register 0 (RL0LS0), if the value read from bit 7 is “0”, “0” is stored in the control register of main control unit 41 in hardware. If the value is not read from the RL0 hard latch random number register 1 (RL0HV1) by writing, the next value is not latched. If the value read from bit 7 is “1”, the main control unit When “1” is written to the control register 41 by hardware, the next value is latched without reading the value from the RL0 hard latch random value register 1 (RL0HV1). The same applies to each setting item in other program management areas and each bit of each register of the built-in register.

  In this embodiment, “1” is set as the setting value of the bit number [7] of the RL0 hard latch selection register 0 (RL0LS0), and the value need not be read from the RL0 hard latch random number value register 1 (RL0HV1). The following values can be latched.

  The data RL01LS0 to RL01LS2 stored in the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0) is input to the RL0 hard latch random number value register 1 (RL0HV1) according to which external terminal is input. It shows the setting of whether to import a value. In the example shown in FIG. 24B, when “000” is set in the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RL0 hard latch select register 0 (RL0LS0), the setting is invalid.

  In this embodiment, “111” is set as the set value of the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0), and depending on the external terminal input, the RL0 hard latch random number register 1 (RL0HV1) ) Is set so that the value of the 16-bit random number RL0 is not captured.

  The data RL00RF stored in the bit number [3] of the RL0 hard latch select register 0 (RL0LS0) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 0 (RL0HV0) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 24B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL00RF becomes “0”. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the set value of the bit number [3] of the RL0 hard latch selection register 0 (RL0LS0), and it is not necessary to read the value from the RL0 hard latch random number register 0 (RL0HV1). The following values can be latched.

  The data RL00LS0 to RL00LS2 stored in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0) is input to the RL0 hard latch random number value register 0 (RL0HV0) according to which external terminal is input to the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 24B, when “000” is set in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0), the setting is invalid. In addition, the data RL00LS0 to RL00LS2 is set to “000” as an initial value.

  In this embodiment, “000” is set as the set value of the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0), and input from the PI0 terminal (input of the operation detection signal of the start switch 7). ) Is set so that the value of the 16-bit random number RL0 is taken into the RL0 hard latch random number value register 0 (RL0HV1).

  FIG. 25A shows a configuration example of the RL0 hard latch selection register 1 (RL0LS1). FIG. 25B shows an example of setting contents in each bit of data stored in the RL0 hard latch selection register 1 (RL0LS1). The data RL03RF stored in the bit number [7] of the RL0 hard latch selection register 1 (RL0LS1) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 3 (RL0HV3) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 25B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL03RF becomes “0”. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the set value of the bit number [7] of the RL0 hard latch selection register 1 (RL0LS1), and the value need not be read from the RL0 hard latch random value register 3 (RL0HV3). The following values can be latched.

  The data RL03LS0 to RL03LS2 stored in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1) is input to the RL0 hard latch random value register 3 (RL0HV3) according to which external terminal is input to the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 25B, when “000” is set in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected. When "101" is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1), the setting is invalid.

  In this embodiment, “111” is set as the set value of the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1). Depending on the external terminal input, the RL0 hard latch random number register 3 (RL0HV3) ) Is set so that the value of the 16-bit random number RL0 is not captured.

  The data RL02RF stored in the bit number [3] of the RL0 hard latch selection register 1 (RL0LS1) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 2 (RL0HV2) by external terminal input. The setting of conditions is shown. In the example shown in FIG. 25B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL02RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the set value of the bit number [3] of the RL0 hard latch selection register 1 (RL0LS1), and it is not necessary to read the value from the RL0 hard latch random value register 2 (RL0HV2). The following values can be latched.

  The data RL02LS0 to RL02LS2 stored in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1) is input to the RL0 hard latch random number value register 2 (RL0HV2) according to which external terminal is input to the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 25B, when “000” is set in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1), the setting is invalid.

  In this embodiment, “111” is set as the set value of the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1). Depending on the external terminal input, the RL0 hard latch random value register 2 (RL0HV2) is set. ) Is set so that the value of the 16-bit random number RL0 is not captured.

  FIG. 26A shows a configuration example of the RLn hard latch selection register (RLnLS). FIG. 26B shows an example of setting contents in each bit of data stored in the RLn hard latch selection register (RLnLS). In FIG. 26, n takes a value from 0 to 3. Data RLn1RF stored in the bit number [7] of the RLn hard latch selection register (RLnLS) is a condition when the value of the 16-bit random number RLn is input to the RLn hard latch random value register 1 (RLnHV1) by an external terminal input. Shows the settings. In the example shown in FIG. 26B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RLn1RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the setting value of the bit number [7] of the RLn hard latch selection register (RLnLS), and the next value is not read from the RLn hard latch random value register 1 (RLnHV1). The value of can be latched.

  The data RLn1LS0 to RLn1LS2 stored in the bit number [6-4] of the RLn hard latch selection register (RLnLS) is the value of the 16-bit random number RLn depending on which external terminal is input to the RLn hard latch random value register 1 (RLnHV1). Indicates whether to capture. In the example shown in FIG. 26B, when “000” is set in the bit number [6-4] of the RLn hard latch selection register (RLnLS), the PI0 terminal is selected and “001” is set. In this case, the PI1 terminal is selected. When “010” is set, the PI2 terminal is selected. When “011” is set, the PI3 terminal is selected. When “100” is set. When the PI4 terminal is selected and “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RLn hard latch selection register (RLnLS), the setting is invalid.

  In this embodiment, “111” is set as the setting value of the bit number [6-4] of the RLn hard latch selection register (RLnLS), and depending on the external terminal input, the RLn hard latch random number value register 1 (RLnHV1) The 16-bit random number RLn is not taken in.

  Data RLn0RF stored in the bit number [3] of the RLn hard latch selection register (RLnLS) is a condition when the value of the 16-bit random number RLn is input to the RLn hard latch random value register 0 (RLnHV0) by an external terminal input. Shows the settings. In the example shown in FIG. 26B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RLn0RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the setting value of the bit number [3] of the RLn hard latch selection register (RLnLS), and the next value is not read from the RLn hard latch random value register 0 (RLnHV0). The value of can be latched.

  The data RLn0LS0 to RLn0LS2 stored in the bit number [2-0] of the RLn hard latch selection register (RLnLS) is the value of the 16-bit random number RLn depending on which external terminal is input to the RLn hard latch random value register 0 (RLnHV0). Indicates whether to capture. In the example shown in FIG. 26B, when “000” is set in the bit number [2-0] of the RLn hard latch selection register (RLnLS), the PI0 terminal is selected and “001” is set. In this case, the PI1 terminal is selected. When “010” is set, the PI2 terminal is selected. When “011” is set, the PI3 terminal is selected. When “100” is set. When the PI4 terminal is selected and “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [2-0] of the RLn hard latch selection register (RLnLS), the setting is invalid.

  In this embodiment, “001” is set as the set value of the bit number [2-0] of the RL1 hard latch selection register (RL1LS), and input from the PI1 terminal (input of the operation detection signal of the MAXBET switch 6). Accordingly, the value of the 16-bit random number RL1 is set to be taken into the RL1 hard latch random number value register 0 (RL1HV0). On the other hand, “111” is set as the setting value of the bit number [2-0] of the RL2 hard latch selection register (RL2LS) and the setting value of the bit number [2-0] of the RL3 hard latch selection register (RL3LS). Depending on the external terminal input, the RL2 hard latch random value register 0 (RL2HV0) and the RL3 hard latch random value register 0 (RL3HV0) are set so that the values of the 16-bit random numbers RL2 and RL3 are not taken in.

  FIG. 27A shows a configuration example of the RS hard latch selection register 0 (RSLS0). FIG. 27B shows an example of setting contents in each bit of data stored in the RS hard latch selection register 0 (RSLS0). Data RS1RF stored in the bit number [7] of the RS hard latch selection register 0 (RSLS0) is a condition for capturing the value of the 8-bit random number RS1 into the RS1 hard latch random value register (RS1HV) by external terminal input. Shows the settings. In the example shown in FIG. 27B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS1RF becomes “0”. When the value is set to be latched, the bit value is “1”.

  In the present embodiment, “1” is set as the setting value of the bit number [7] of the RS hard latch selection register 0 (RSLS0). The value of can be latched.

  The data RS1LS0 to RS1LS2 stored in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0) is an 8-bit random number RS1 value depending on which external terminal is input to the RS1 hard latch random value register (RS1HV). Indicates whether to capture. In the example shown in FIG. 27B, when “000” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0), the setting is invalid.

  In this embodiment, “111” is set as the setting value of the bit number [6-4] of the RS hard latch selection register 0 (RSLS0). Depending on the external terminal input, the RS1 hard latch random number value register (RS1HV) Is set so that the value of the 8-bit random number RS1 is not captured.

  Data RS0RF stored in the bit number [3] of the RS hard latch selection register 0 (RSLS0) is a condition for taking the value of the 8-bit random number RS0 into the RS0 hard latch random value register (RS0HV) by inputting an external terminal Shows the settings. In the example shown in FIG. 27B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS0RF becomes “0”. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the set value of the bit number [3] of the RS hard latch selection register 0 (RSLS0), and the next value is not read from the RS0 hard latch random value register (RS0HV). The value of can be latched.

  The data RS0LS0 to RS0LS2 stored in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0) is the value of the 8-bit random number RS0 depending on which external terminal input to the RS0 hard latch random value register (RS0HV). Indicates whether to capture. In the example shown in FIG. 27B, when “000” is set in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0), the setting is invalid.

  In this embodiment, “111” is set as the setting value of the bit number [2-0] of the RS hard latch selection register 0 (RSLS0). Depending on the external terminal input, the RS hard latch selection register 0 (RSLS0) Is set so that the value of the 8-bit random number RS0 is not captured.

  FIG. 28A shows a configuration example of the RS hard latch selection register 1 (RSLS1). FIG. 28B shows an example of setting contents in each bit of data stored in the RS hard latch selection register 1 (RSLS1). Data RS3RF stored in the bit number [7] of the RS hard latch selection register 1 (RSLS1) is a condition for taking the value of the 8-bit random number RS3 into the RS3 hard latch random number value register (RS3HV) by external terminal input Shows the settings. In the example shown in FIG. 28B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS3RF becomes “0”. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the setting value of the bit number [7] of the RS hard latch selection register 1 (RSLS1), and the next value is not read from the RS3 hard latch random number value register (RS3HV). The value of can be latched.

  The data RS3LS0 to RS3LS2 stored in the bit number [6-4] of the RS hard latch selection register 1 (RSLS1) is an 8-bit random number RS3 value depending on which external terminal is input to the RS3 hard latch random number value register (RS3HV). Indicates whether to capture. In the example shown in FIG. 28B, when “000” is set in the bit number [6-4] of the RS hard latch selection register 1 (RSLS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS1), the setting is invalid.

  In this embodiment, “111” is set as the set value of the bit number [6-4] of the RS hard latch selection register 1 (RSLS1). Depending on the external terminal input, the RS3 hard latch random number value register (RS3HV) Is set so that the value of the 8-bit random number RS3 is not captured.

  Data RS2RF stored in the bit number [3] of the RS hard latch selection register 1 (RSLS1) is a condition for taking the value of the 8-bit random number RS2 into the RS2 hard latch random value register (RS2HV) by inputting an external terminal Shows the settings. In the example shown in FIG. 28B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS2RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”.

  In this embodiment, “1” is set as the setting value of the bit number [3] of the RS hard latch selection register 1 (RSLS1), and the next value is not read from the RS2 hard latch random value register (RS2HV). The value of can be latched.

  The data RS2LS0 to RS2LS2 stored in the bit number [2-0] of the RS hard latch selection register 1 (RSLS1) is an 8-bit random number RS2 value depending on which external terminal is input to the RS2 hard latch random value register (RS2HV). Indicates whether to capture. In the example shown in FIG. 28B, when the bit number [2-0] of the RS hard latch selection register 1 (RSLS1) is set to “000”, the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RS hard latch selection register 1 (RSLS1), the setting is invalid.

  In this embodiment, “111” is set as the setting value of the bit number [2-0] of the RS hard latch selection register 1 (RSLS1). Depending on the external terminal input, the RS2 hard latch random number value register (RS2HV) Is set so that the value of the 8-bit random number RS2 is not captured.

  FIG. 29A shows a configuration example of the RL interrupt control register 0 (RLIC0). FIG. 29B shows an example of setting contents in each bit of data stored in the RL interrupt control register 0 (RLIC0). The bit value of bit [7-6] of RL interrupt control register 0 (RLIC0) is always set to “0”.

  The data RL11IE stored in the bit number [5] of the RL interrupt control register 0 (RLIC0) is prohibited from being interrupted due to the fact that the random number value is captured in the RL1 hard latch random value register 1 (RL1HV1). / Indicates permission settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL11IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. It becomes.

  The data RL10IE stored in the bit number [4] of the RL interrupt control register 0 (RLIC0) is prohibited from being interrupted due to the fact that a random value is captured in the RL1 hard latch random number value register 0 (RL1HV0). / Indicates permission settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL10IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. It becomes.

  The data RL03IE stored in the bit number [3] of the RL interrupt control register 0 (RLIC0) is prohibited from being interrupted due to the fact that the random number value is captured in the RL0 hard latch random number value register 3 (RL0HV3). / Indicates permission settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL03IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. It becomes.

  The data RL02IE stored in the bit number [2] of the RL interrupt control register 0 (RLIC0) is prohibited from being interrupted due to the fact that the random number value is taken into the RL0 hard latch random value register 2 (RL0HV2). / Indicates permission settings. In the example shown in FIG. 29B, the bit value of the data RL02IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data RL01IE stored in the bit number [1] of the RL interrupt control register 0 (RLIC0) is prohibited from being interrupted due to the fact that the random number value is taken into the RL0 hard latch random number value register 1 (RL0HV1). / Indicates permission settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL01IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. It becomes.

  The data RL00IE stored in the bit number [1] of the RL interrupt control register 0 (RLIC0) is prohibited from being interrupted due to the fact that the random number value is captured in the RL0 hard latch random value register 0 (RL0HV0). / Indicates permission settings. In the example shown in FIG. 29B, when the interrupt is disabled, the bit value of the data RL00IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. It becomes.

  In this embodiment, “0” is set as the set values of the bit numbers [5] to [0] of the RL interrupt control register 0 (RLIC0), and the RL0 hard latch random number register 0 (RL0HV0) ~ RL0 hard latch random value register 3 (RL0HV3), RL1 hard latch random value register 0 (RL1HV0) ~ RL1 hard latch random value register 1 (RL1HV1) It has become so.

  FIG. 30A shows a configuration example of the RL interrupt control register 1 (RLIC1). FIG. 30B shows an example of setting contents in each bit of data stored in the RL interrupt control register 1 (RLIC1). The bit values of the bits [7-6] and [3-2] of the RL interrupt control register 1 (RLIC1) are always “0”.

  The data RL31IE stored in the bit number [5] of the RL interrupt control register 1 (RLIC1) is prohibited from being interrupted due to the fact that the random number value is captured in the RL3 hard latch random number value register 1 (RL3HV1). / Indicates permission settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL31IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. It becomes.

  The data RL30IE stored in the bit number [4] of the RL interrupt control register 1 (RLIC1) is prohibited from being interrupted due to the fact that the random number value is captured in the RL3 hard latch random value register 0 (RL3HV0). / Indicates permission settings. In the example shown in FIG. 30B, the bit value of the data RL30IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data RL21IE stored in the bit number [1] of the RL interrupt control register 1 (RLIC1) is prohibited from being interrupted due to the fact that the random number value is captured in the RL2 hard latch random value register 1 (RL2HV1). / Indicates permission settings. In the example shown in FIG. 30B, the bit value of the data RL21IE is “0” when interrupt disabled is set, while the bit value is “1” when interrupt enabled is set. It becomes.

  The data RL20IE stored in the bit number [0] of the RL interrupt control register 1 (RLIC1) is prohibited from being interrupted due to the fact that the random number value is captured in the RL2 hard latch random value register 0 (RL2HV0). / Indicates permission settings. In the example shown in FIG. 30B, the bit value of the data RL20IE is “0” when interrupt disabled is set, while the bit value is “1” when interrupt enabled is set. It becomes.

  In this embodiment, “0” is set as the set values of the bit numbers [5], [4], [1], and [0] of the RL interrupt control register 1 (RLIC1), and the RL2 hardware Random random value register 0 (RL2HV0) to RL2 hard latch random value register 1 (RL2HV1), RL3 hard latch random value register 0 (RL3HV0) to RL3 hard latch random value register 1 (RL3HV1) Interruption as a factor is prohibited.

  FIG. 31A shows a configuration example of the RS interrupt control register (RSIC). FIG. 31B shows an example of setting contents in each bit of data stored in the RS interrupt control register (RSIC). The RS interrupt control register (RSIC) is a register used in common by the 8-bit random number circuit 508a and the free-run counter circuit 507, and bits [7-4] of the RS interrupt control register (RSIC) are The settings related to the hard latch registers (FRC0 hard latch register (FR0HV) to FRC3 hard latch register (FR3HV)) used by the free-run counter circuit 507 are shown.

  The data FR3IE stored in the bit number [7] of the RS interrupt control register (RSIC) is set to disable / enable interrupts due to the fact that a random value is taken into the FRC3 hard latch register (FR3HV). Is shown. In the example shown in FIG. 31B, the bit value of the data FR3IE is “0” when interrupt disabled is set, whereas the bit value is “1” when interrupt enabled is set. It becomes.

  The data FR2IE stored in the bit number [6] of the RS interrupt control register (RSIC) is set to prohibit / permit interrupts due to the fact that a random value is taken into the FRC2 hard latch register (FR2HV). Is shown. In the example shown in FIG. 31B, the bit value of the data FR2IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data FR1IE stored in the bit number [5] of the RS interrupt control register (RSIC) is set to disable / enable interrupts due to the fact that a random number value is taken into the FRC1 hard latch register (FR1HV). Is shown. In the example shown in FIG. 31B, the bit value of the data FR1IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data FR0IE stored in the bit number [4] of the RS interrupt control register (RSIC) is set to disable / permit interrupts due to the fact that a random number value is taken into the FRC0 hard latch register (FR0HV). Is shown. In the example shown in FIG. 31B, the bit value of the data FR0IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  In this embodiment, “0” is set as the set values of the bit numbers [7] to [4] of the RL interrupt control register 0 (RLIC0), and the FRC0 hardware latch register (FR0HV) to FRC3 hardware Interruption due to the fact that a random value is taken into the latch register (FR3HV) is prohibited.

  The data RS3IE stored in the bit number [3] of the RS interrupt control register (RSIC) is disabled / permitted for interrupts due to the fact that the RS3 hard latch random value register (RS3HV) has received a random value. Shows the settings. In the example shown in FIG. 31B, the bit value of the data RS3IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data RS2IE stored in the bit number [2] of the RS interrupt control register (RSIC) is prohibited / permitted for interrupts due to the fact that the RS2 hard latch random number value register (RS2HV) has received a random value. Shows the settings. In the example shown in FIG. 31B, the bit value of the data RS2IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data RS1IE stored in the bit number [1] of the RS interrupt control register (RSIC) is prohibited / permitted for interrupts due to the fact that the RS1 hard latch random value register (RS1HV) has received a random value. Shows the settings. In the example shown in FIG. 31B, the bit value of the data RS1IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  The data RS0IE stored in the bit number [0] of the RS interrupt control register (RSIC) is prohibited / permitted for interrupts due to the fact that the random value is taken into the RS0 hard latch random number value register (RS0HV). Shows the settings. In the example shown in FIG. 31B, the bit value of the data RS0IE is “0” when the interrupt is disabled, whereas the bit value is “1” when the interrupt is enabled. It becomes.

  In this embodiment, “0” is set as the set values of the bit numbers [3] to [0] of the RL interrupt control register 0 (RLIC0), and the RS0 hard latch random number value register (RS0HV) to Interrupts caused by random number values taken into the RS3 hard latch random value register (RS3HV) are prohibited.

  FIG. 32A shows a configuration example of the RLn maximum value setting register (RLnMX). FIG. 32B shows an example of setting contents in each bit of data stored in the RLn maximum value setting register (RLnMX). In FIG. 32, n takes a value from 0 to 3. As shown in FIG. 32B, the maximum value of the 16-bit random number RLn is set in the data RLnMX15 to RLnMX0 stored in the bit number [15-0] of the RLn maximum value setting register (RLnMX).

  The RLn maximum value setting register (RLnMX) can be set by software (user program) after shifting to the user mode. In the 16-bit random number initial setting 1 and 2 (KRL 1 and 2), the 16-bit random number circuit 508b By setting the maximum value (1 to 65536) in the RLn maximum value setting register (RLnMX) corresponding to the 16-bit random number circuit 508b of the channel set to be activated by software as the activation method, the 16-bit random number of the corresponding channel is set. The circuit 508b is activated, and random numbers are generated in the range of 0 to the maximum value. It should be noted that as a starting method of the 16-bit random number circuit 508b, the maximum value is not set in the RLn maximum value setting register (RLnMX) corresponding to the 16-bit random number circuit 508b of the channel set to be started by software. The bit random number circuit 508b can be set to unused without being activated.

  In this embodiment, the activation by software is set as the activation method of the 16-bit random number circuit 508b of channels 2 and 3, and the corresponding RL2 maximum value setting register (RL2MX) and RL3 maximum value setting register (RL3MX) are respectively set. Since 0 is set, the 16-bit random number circuit 508b of channels 2 and 3 is set to unused.

  FIG. 33A shows a configuration example of the RSn maximum value setting register (RSnMX). FIG. 33B shows an example of setting contents in each bit of data stored in the RSn maximum value setting register (RSnMX). In FIG. 33, n takes a value from 0 to 3. As shown in FIG. 33B, the maximum value of the 8-bit random number RSn is set in the data RSnMX7 to RSnMX0 stored in the bit number [7-0] of the RSn maximum value setting register (RSnMX).

  The RSn maximum value setting register (RSnMX) can be set by software (user program) after shifting to the user mode. In the 8-bit random number initial setting 1 and 2 (KRL 1 and 2), the 8-bit random number circuit 508a By setting the maximum value (1 to 255) in the RSn maximum value setting register (RSnMX) corresponding to the 8-bit random number circuit 508a of the channel for which activation by software is set as the activation method, the 8-bit random number of the corresponding channel The circuit 508a is activated, and random numbers are generated in the range of 0 to the maximum value. It should be noted that as a starting method of the 8-bit random number circuit 508a, the maximum value is not set in the RSn maximum value setting register (RSnMX) corresponding to the 8-bit random number circuit 508a of the channel set to be started by software. The bit random number circuit 508a can be set to unused without being activated.

  In this embodiment, activation by software is set as the activation method of the 8-bit random number circuit 508a of channels 0 to 3, and the corresponding RL0 maximum value setting register (RL0MX) to RL3 maximum value setting register (RL3MX) are respectively set. Since 0 is set, the 8-bit random number circuit 508a of channels 0 to 3 is set to unused.

  FIG. 34A shows a configuration example of the random number sequence change register (RDSC). FIG. 34B shows an example of setting contents in each bit of data stored in the random number sequence change register (RDSC). Data RS3SC stored in the bit number [7] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of the 8-bit random number RS3. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS3SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS3SC is set to “0” as an initial value.

  Data RS2SC stored in the bit number [6] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of the 8-bit random number RS2. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS2SC becomes “0”, whereas when the random number sequence is set to be changed, the bit value Becomes “1”. The data RS2SC is set to “0” as an initial value.

  The data RS1SC stored in the bit number [5] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 8-bit random number RS1. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS1SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS1SC is set to “0” as an initial value.

  Data RS0SC stored in bit number [4] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 8-bit random number RS0. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RS0SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS0SC is set to “0” as an initial value.

  Data RL3SC stored in bit number [3] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 16-bit random number RL3. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL3SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL3SC is set to “0” as an initial value.

  The data RL2SC stored in the bit number [2] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 16-bit random number RL2. In the example shown in FIG. 34 (B), when the random number sequence is set not to be changed, the bit value of the data RL2SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL2SC is set to “0” as an initial value.

  The data RL1SC stored in the bit number [1] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 16-bit random number RL1. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL1SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL1SC is set to “0” as an initial value.

  Data RL0SC stored in bit number [0] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 16-bit random number RL0. In the example shown in FIG. 34B, when the random number sequence is set not to be changed, the bit value of the data RL0SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL0SC is set to “0” as an initial value.

  FIG. 35A shows a configuration example of a random number soft latch register (RDSL). FIG. 35B shows an example of setting contents in each bit of data stored in the random number soft latch register (RDSL). Data RS3SL stored in bit number [7] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 8-bit random number RS3 into the RS3 soft latch random number value register (RS3SV). In the example shown in FIG. 35B, when the random number value is set not to be taken in, the bit value of the data RS3SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS3SL is set to “0” as an initial value.

  Data RS2SL stored in the bit number [6] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 8-bit random number RS2 into the RS2 soft latch random number value register (RS2SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RS2SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS2SL is set to “0” as an initial value.

  The data RS1SL stored in the bit number [5] of the random number soft latch register (RDSL) indicates a bit for taking the random value of the 8-bit random number RS1 into the RS1 soft latch random value register (RS1SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RS1SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS1SL is set to “0” as an initial value.

  Data RS0SL stored in bit number [4] of the random number soft latch register (RDSL) indicates a bit for taking the random value of the 8-bit random number RS0 into the RS0 soft latch random value register (RS0SV). In the example shown in FIG. 35B, the bit value of the data RS0SL is “0” when the random number value is set not to be captured, while the bit value is set when the random number sequence is changed. Becomes “1”. The data RS0SL is set to “0” as an initial value.

  Data RL3SL stored in the bit number [3] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL3 into the RL3 soft latch random value register (RL3SV). In the example shown in FIG. 35B, the bit value of the data RL3SL becomes “0” when it is set not to take in the random number value, while the bit value when it is set to change the random number sequence. Becomes “1”. The data RL3SL is set to “0” as an initial value.

  Data RL2SL stored in the bit number [2] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL2 into the RL2 soft latch random number value register (RL2SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RL2SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL2SL is set to “0” as an initial value.

  Data RL1SL stored in the bit number [1] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL1 into the RL1 soft latch random number value register (RL1SV). In the example shown in FIG. 35B, when the random value is set not to be taken in, the bit value of the data RL1SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL1SL is set to “0” as an initial value.

  Data RL0SL stored in the bit number [0] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL0 into the RL0 soft latch random value register (RL0SV). In the example shown in FIG. 35B, the bit value of the data RL0SL is “0” when the random value is set not to be captured, while the bit value is set when the random number sequence is set to be changed. Becomes “1”. The data RL0SL is set to “0” as an initial value.

  FIG. 36A shows a configuration example of a random number soft latch flag register (RDSF). FIG. 36B shows an example of setting contents in each bit of data stored in the random number soft latch flag register (RDSF). The data RS3SF stored in the bit number [7] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS3 soft latch random value register (RS3SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS3SF is “0”, whereas when the random value has been captured, the bit value is “ 1 ". The data RS3SF is set to “0” as an initial value.

  The data RS2SF stored in the bit number [6] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS2 soft latch random value register (RS2SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS2SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS2SF is set to “0” as an initial value.

  The data RS1SF stored in the bit number [5] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS1 soft latch random number value register (RS1SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS1SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS1SF is set to “0” as an initial value.

  The data RS0SF stored in the bit number [4] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS0 soft latch random value register (RS0SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RS0SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS0SF is set to “0” as an initial value.

  The data RL3SF stored in the bit number [3] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL3 soft latch random value register (RL3SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL3SF is “0”, while when the random value has been captured, the bit value is “0”. 1 ". The data RL3SF is set to “0” as an initial value.

  The data RL2SF stored in the bit number [2] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL2 soft latch random number value register (RL2SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL2SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL2SF is set to “0” as an initial value.

  The data RL1SF stored in the bit number [1] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL1 soft latch random number value register (RL1SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL1SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL1SF is set to “0” as an initial value.

  Data RL0SF stored in the bit number [0] of the random number soft latch flag register (RDSF) indicates that the random number value has been taken into the RL0 soft latch random number value register (RL0SV). In the example shown in FIG. 36B, when the random value is not captured, the bit value of the data RL0SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL0SF is set to “0” as an initial value.

  FIG. 37A shows a configuration example of the RLn soft latch random value register (RLnSV). FIG. 37B shows an example of the contents stored in each bit of data stored in the RLn soft latch random value register (RLnSV). In FIG. 37, n takes a value from 0 to 3. As shown in FIG. 37B, the data RLnSV15 to RLnSV0 stored in the bit number [15-0] of the RLn soft latch random value register (RLnSV) are 16 bits taken by the random number soft latch register (RDSL). The value of the random number RLn is stored. When a random value is fetched, “1” is set in the corresponding bit of the random number soft latch flag register (RDSF).

  FIG. 38A shows a configuration example of the RSn soft latch random number value register (RSnSV). FIG. 38B shows an example of the contents stored in each bit of data stored in the RSn soft latch random value register (RSnSV). In FIG. 38, n takes a value from 0 to 3. As shown in FIG. 38B, the data RSnSV7 to RSnSV0 stored in the bit number [7-0] of the RSn soft latch random number register (RSnSV) are 8 bits taken by the random number soft latch register (RDSL). The value of the random number RSn is stored. When a random value is fetched, “1” is set in the corresponding bit of the random number soft latch flag register (RDSF).

  FIG. 39A shows a configuration example of the RL hard latch flag register 0 (RLHF0). FIG. 39B shows an example of setting contents in each bit of data stored in the RL hard latch flag register 0 (RLHF0). The bit value of bit [7-6] of the RL hard latch flag register 0 (RLHF0) is always “0”.

  The data RL11HF stored in the bit number [5] of the RL hard latch flag register 0 (RLHF0) indicates that the random number value is taken into the RL1 hard latch random value register 1. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL11HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL11HF is set to “0” as an initial value.

  The data RL10HF stored in the bit number [4] of the RL hard latch flag register 0 (RLHF0) indicates that a random value has been taken into the RL1 hard latch random value register 0. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL10HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL10HF is set to “0” as an initial value.

  The data RL03HF stored in the bit number [3] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 3. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL03HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL03HF is set to “0” as an initial value.

  The data RL02HF stored in the bit number [2] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 2. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL02HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL02HF is set to “0” as an initial value.

  The data RL01HF stored in the bit number [1] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 1. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL01HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL01HF is set to “0” as an initial value.

  The data RL00HF stored in the bit number [0] of the RL hard latch flag register 0 (RLHF0) indicates that a random value has been taken into the RL0 hard latch random value register 0. In the example shown in FIG. 39B, when the random value is not captured, the bit value of the data RL00HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL00HF is set to “0” as an initial value.

  FIG. 40A shows a configuration example of the RL hard latch flag register 1 (RLHF1). FIG. 40B shows an example of setting contents in each bit of data stored in the RL hard latch flag register 1 (RLHF1). The bit values of the bits [7-6] and [3-2] of the RL hard latch flag register 1 (RLHF1) are always “0”.

  Data RL31HF stored in the bit number [5] of the RL hard latch flag register 1 (RLHF1) indicates that a random number value has been taken into the RL3 hard latch random value register 1. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL31HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL31HF is set to “0” as an initial value.

  The data RL30HF stored in the bit number [4] of the RL hard latch flag register 1 (RLHF1) indicates that a random value has been taken into the RL3 hard latch random value register 0. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL30HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL30HF is set to “0” as an initial value.

  The data RL21HF stored in the bit number [1] of the RL hard latch flag register 1 (RLHF1) indicates that a random value has been taken into the RL2 hard latch random value register 1. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL21HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL21HF is set to “0” as an initial value.

  The data RL20HF stored in the bit number [1] of the RL hard latch flag register 1 (RLHF1) indicates that the random number value is taken into the RL2 hard latch random value register 0. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL20HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL20HF is set to “0” as an initial value.

  FIG. 41A shows a configuration example of the RS hard latch flag register (RSHF). FIG. 41B shows an example of setting contents in each bit of data stored in the RS hard latch flag register (RSHF). The RS hard latch flag register (RSHF) is a register that is used by both the 8-bit random number circuit 508a and the free-run counter circuit 507, and bits [7-4] of the RS hard latch flag register (RSHF) are The settings related to the hard latch registers (FRC0 hard latch register (FR0HV) to FRC3 hard latch register (FR3HV)) used by the free-run counter circuit 507 are shown.

  The data RS3HF stored in the bit number [3] of the RS hard latch flag register (RSHF) indicates that the random number value is taken into the RS3 hard latch random value register (RS3HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS3HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS3HF is set to “0” as an initial value.

  The data RS2HF stored in the bit number [2] of the RS hard latch flag register (RSHF) indicates that the random value is taken into the RS2 hard latch random value register (RS2HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS2HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS2HF is set to “0” as an initial value.

  The data RS1HF stored in the bit number [1] of the RS hard latch flag register (RSHF) indicates that the random value has been taken into the RS1 hard latch random value register (RS1HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS1HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS1HF is set to “0” as an initial value.

  The data RS0HF stored in the bit number [0] of the RS hard latch flag register (RSHF) indicates that the random value is taken into the RS0 hard latch random value register (RS0HV). In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RS0HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS0HF is set to “0” as an initial value.

  FIG. 42A shows a configuration example of the RL0 hard latch random number value register m (RL0mHV). FIG. 42B shows an example of the contents stored in each bit of data stored in the RL0 hard latch random number value register m (RL0mHV). In FIG. 42, m takes a value from 0 to 3. As shown in FIG. 42B, the data RL0mHV15 to RL0mHV0 stored in the bit number [15-0] of the RL0 hard latch random number value register m (RL0mHV) are the 16-bit random number RL0 captured by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 0 (RLHF0).

  FIG. 43A shows a configuration example of the RL1 hard latch random number value register m (RL1mHV). FIG. 43B shows an example of the contents stored in each bit of data stored in the RL1 hard latch random number value register m (RL1mHV). In FIG. 43, m takes a value from 0 to 3. As shown in FIG. 43B, the data RL1mHV15 to RL1mHV0 stored in the bit number [15-0] of the RL1 hard latch random number value register m (RL1mHV) are the 16-bit random number RL1 fetched by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 0 (RLHF0).

  FIG. 44A shows a configuration example of the RL2 hard latch random number value register m (RL2mHV). FIG. 44B shows an example of the contents stored in each bit of data stored in the RL2 hard latch random number value register m (RL2mHV). In FIG. 44, m takes a value from 0 to 3. As shown in FIG. 44 (B), the data RL2mHV15 to RL2mHV0 stored in the bit number [15-0] of the RL2 hard latch random value register m (RL2mHV) is the 16-bit random number RL2 captured by the external terminal input. Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 1 (RLHF1).

  FIG. 45A shows a configuration example of the RL3 hard latch random number value register m (RL3mHV). FIG. 45B shows an example of the contents stored in each bit of data stored in the RL3 hard latch random number value register m (RL3mHV). In FIG. 45, m takes a value from 0 to 3. As shown in FIG. 45 (B), the data RL3mHV15 to RL3mHV0 stored in the bit number [15-0] of the RL3 hard latch random number register m (RL3mHV) is the 16-bit random number RL3 fetched by the external terminal input Stores the value. When a random value is fetched, “1” is set in the corresponding bit of the RL hard latch flag register 1 (RLHF1).

  FIG. 46A shows a configuration example of the RSn hard latch random number value register (RSnHV). FIG. 46B shows an example of the contents stored in each bit of data stored in the RSn hard latch random number value register (RSnHV). In FIG. 46, n takes a value from 0 to 3. As shown in FIG. 46B, the data RSnHV7 to RSnHV0 stored in the bit number [70] of the RSn hard latch random number register (RLnHV) stores the value of the 8-bit random number RSn fetched by the external terminal input. Is done. When a random value is taken in, “1” is set in the corresponding bit of the RS hard latch flag register (RSHF).

  In this embodiment, the main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41. In this embodiment, the command is transmitted to the sub-control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but via the serial communication circuit 512. A configuration in which a command is transmitted to the sub-control unit 91, that is, a configuration in which the command is transmitted as a serial signal may be employed.

  The main control unit 41 also receives detection states of various switches connected to the game control board 40 from the parallel input port 511. The main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from the parallel input port 511.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In this embodiment, a timer interrupt process (main), which will be described later, is executed every time a time-out occurs in the timer circuit 509, that is, every fixed time interval (about 0.56 ms in this embodiment).

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. Further, the main control unit 41 executes a timer interrupt process (main) at regular time intervals (about 0.56 ms in this embodiment). In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  An effect switch 56 is connected to the effect control board 90, and a detection signal of the effect switch 56 is input.

  The effect control board 90 is connected to effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55. These effect devices are sub-controls described later mounted on the effect control board 90. It is driven based on control by the unit 91.

  In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, effect effect LED 52, speakers 53 and 54, and reel LED 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units.

  Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  The effect control board 90 is composed of a microcomputer having a sub CPU 91a, ROM 91b, RAM 91c, and I / O port 91d, and a liquid crystal display connected to the effect control board 90, a sub control unit 91 for effect control. 51, a display control circuit 92 for performing display control, an LED driving circuit 93 for controlling driving of the effect LED 52 and the reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53, 54, when the power is turned on or from the sub CPU 91a The reset circuit 95 that gives a reset signal to the sub CPU 91a when the initialization command is not input for a predetermined time, the switch detection circuit 96 that detects the detection signal input from the effect switch 56 connected to the effect control board 90, and date information Clock device 97 for outputting time information including time information, and slot A power interruption detection circuit 98 that monitors a power supply voltage supplied to the thin 1 and outputs a voltage drop signal indicating that to the sub CPU 91a when a voltage drop is detected, and other circuits are mounted. The sub CPU 91a receives various commands transmitted from the game control board 40 and performs various controls for performing the effects, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90. Control.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 It starts at an earlier stage than the unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval.

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the set value display 24 is updated one by one (when the set value 6 is further operated, the set value 1 is set. Return). When the start switch 7 is operated, the display value is determined as the set value. When the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In addition, when the setting key switch 37 is turned on and the power is turned on, the configuration may be changed to the setting change state on condition that the opening of the front door 1b is detected by the door opening detection switch 25. By setting it as such a structure, it can prevent that a setting change will be carried out illegally in the state which the front door 1b is not open | released. Further, in the configuration that shifts to the setting change state on the condition that the opening of the front door 1b is detected, the door opening detection switch 25 does not detect the opening of the front door 1b after shifting to the setting change state. However, it is preferable to maintain the setting change state, so that even if the front door 1b is temporarily closed during the setting change, the operation for changing to the setting change state is not required again, and the setting change state is required. Operation is not complicated. In addition, after shifting to the setting change state, when the setting key switch 37 is turned off after the start switch 7 is operated and the set value is confirmed, the door opening detection switch 25 detects the opening of the front door 1b. On the condition that the setting change state is terminated, it may be configured to shift to a state in which the game can proceed. Even in such a configuration, the setting change is illegally performed when the front door 1b is not opened. Can be prevented.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on in a state where the bet amount is not set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by setting the setting key switch 37 to the off state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  After the game, the setting is made on the condition that the opening of the front door 1b is detected by the door opening detection switch 25 when the setting key switch 37 is turned on with no betting number set. A configuration for shifting to the confirmation state may be adopted, and by adopting such a configuration, it is possible to prevent the setting value from being illegally confirmed without the front door 1b being opened. Further, in the configuration that shifts to the setting confirmation state on the condition that the opening of the front door 1b is detected, the door opening detection switch 25 does not detect the opening of the front door 1b after the transition to the setting confirmation state. However, it is preferable to maintain the setting confirmation state, so that even if the front door 1b is temporarily closed during the setting confirmation, the operation for shifting to the setting confirmation state is not required again, and the setting confirmation state is required. Operation is not complicated. In addition, after shifting to the setting confirmation state, when the set key switch 37 is turned off after the set value is confirmed by operating the start switch 7, the door opening detection switch 25 detects the opening of the front door 1b. On the condition that the setting confirmation state is terminated, it may be configured to return to a state in which the game can proceed. Even in such a configuration, the setting value is illegally set when the front door 1b is not opened. It can be prevented from being confirmed.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not the voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interruption process (main) is executed. When the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, a power interruption process (main) for setting data for determining whether or not the data in the RAM 41c is normal at the next return is performed. Run.

  Then, the main control unit 41 returns the processing state of the main control unit 41 to the state before the power interruption based on the data stored in the RAM 41c on the condition that the data in the RAM 41c is normal at the time of activation. However, if the RAM 41c data is not normal, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state, thereby disabling the progress of the game.

  Further, the sub control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 is detected in the timer interruption process (sub), and when it is determined that the voltage drop signal is detected, A power interruption process (sub) for setting data for determining whether or not the data in the RAM 91c is normal at the next return is executed.

  Then, the sub-control unit 91 returns the processing state of the sub-control unit 91 to the state before the power interruption based on the data stored in the RAM 91c on the condition that the data of the RAM 91c is normal at the time of activation. However, if the data in the RAM 91c is not normal, it is determined that the RAM is abnormal, and the RAM 91c is initialized. In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the performance is not disabled.

  In addition, even when it is determined that the data in the RAM 91c is normal at the time of activation, the sub control unit 91 activates when receiving a setting command (described later) indicating that the setting change state has been entered from the main control unit 41. Even when a later-described return command or setting command indicating that the control state of the main control unit 41 has returned is not received even after a certain period of time has elapsed, the RAM 91c is initialized. In this case, the execution of the performance is not disabled only by initializing the RAM 91c.

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The storage area of the RAM 41c of the main control unit 41 is divided into an important work, a non-saved work, a general work, a special work, an unused area, and a stack area.

  In this embodiment, the main control unit 41 stores data in the RAM 41c when a RAM abnormality error occurs, when the setting key switch 37 is activated with the setting key switch 37 turned on, when the bonus ends, and when the setting key switch 37 is activated with the setting key switch 37 turned off. When not being destroyed, when five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is a setting key switch 37 that is on at the time of startup, and is an initialization that is performed before the transition to the setting change state or an initialization that occurs when a RAM error occurs. In the storage area of the RAM 41c, areas other than the important work and the special work are initialized. Initialization 2 is initialization performed at the end of the bonus. In initialization 2, the general work, the unused area, and the unused stack area in the storage area of the RAM 41c are initialized. Initialization 3 is an initialization performed when the setting key switch 37 is off at the time of startup and the data in the RAM 41c is not destroyed. In the initialization 3, the unsaved work, the unused area, and the The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 41c are initialized.

  In this embodiment, initialization 1 is performed before the change of the setting change state. However, the initialization 1 is performed at the end of the setting change state, or both before the change of the setting change state and at the end of the setting change state. Anyway.

  In the slot machine 1 according to the present embodiment, the prescribed number of bets that can be set according to the gaming state is determined as described above, and the prescribed number of bets that are determined according to the gaming state is set. It becomes possible to start the game on the condition. In the present embodiment, the winning line LN is activated when a specified number of bets according to the gaming state are set.

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line (in the present embodiment, all the pay lines are always enabled. The activated winning line is simply referred to as a winning line). When a combination of symbols called a combination is arranged on the winning line, a winning is achieved. The combination may be a combination of the same symbols or a combination including different symbols.

  The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role.

  In order for winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag of the combination in the RAM 41c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combinations permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, whether or not the main control unit 41 allows the above winning combination is determined before the display results of all the reels 2L, 2C, 2R are derived and displayed (actually, the start switch 7 Is determined). In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value generated by the channel RL0 of the random number circuit 508b and stored in the RL0 hard latch random value register 0 (RL0HV0) is set as the lottery work assigned to the RAM 41c. Then, for each combination determined according to the gaming state and whether or not the special combination is carried over, it is determined according to the numerical data stored in the lottery work, the current gaming state and RT type, the number of bets and the set value. It is performed according to the number of judgment values for each combination.

  As already described with reference to FIG. 24, the channel of the random number circuit 508b is based on the signal (latch signal) from either terminal according to the setting contents of bits 2-0 of the RL0 hard latch select register 0 (RL0LS0). Whether to latch the random number value in the RL0 hard latch random value register 0 (RL0HV0) of RL0 is set. In the present embodiment, setting is made such that the random number value is latched in the RL0 hard latch random number value register 0 (RL0HV0) of the channel RL0 of the random number circuit 508b based on the signal from the PI0 terminal to which the detection signal from the start switch 7 is input. The random number value can be latched in the RL0 hard latch random value register 0 (RL0HV0) in the channel RL0 of the random number circuit 508b at the timing when the start switch 7 is operated.

  In the internal lottery, the number of judgment values determined in accordance with the role that is the subject of the internal lottery, the current gaming state, the current RT type and the set value are stored in a random number for internal lottery (the lottery work) When the result of addition overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the combination determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described.

  The main control unit 41 refers to the table index and the table creation data stored in the ROM 41bA when the rotation of the reel starts and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even when the winning combinations are different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referenced for each situation is registered for each rotating reel, and based on the top address of the table creation data, It is possible to specify the address of the stop control table that should be referred to according to the status of each, and it is necessary according to each status from this specified address. And to be able to identify the stop control table. Even when the reel stop status and the stopped position of the stopped reel are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. In the present embodiment, a stepping motor that makes one turn at a cycle of 336 steps (0 to 335) is used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven in 336 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, the stop control table created by referring to the table index and the table creation data corresponds to the area number, and the area corresponding to each area number is the stop reference position (in this embodiment, the perspective window 3). Sliding frame when an operation of the stop switches 8L, 8C, 8R is detected at a timing (a timing in which the number of steps from the reel reference position is included in the range of the number of steps of each region number). It is a table with each number set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the table creation data, and the stop control table address of the unreacted reel corresponding to the stopped reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table for each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position ahead of the number of sliding frames from the area corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the perspective window 3 It will stop in the lower symbol area).

  In the table index of this embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and further, one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). In other words, table creation data corresponding to one internal winning state in one gaming state and stop control tables corresponding to reel stop states (and stopped positions of stopped reels) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in this embodiment, a value of 0 to 4 is determined as the number of sliding frames, and the reel can be stopped by drawing a maximum of 4 symbols after detecting the stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In this embodiment, when any of the winning combinations is won, the winning combination is drawn to the maximum in the range of 4 frames on the winning line, and the non-winning winning combination is drawn so that it is not aligned on the winning line. A stop control table with a defined number of frames is created and reel stop control is performed. If no winning combination is selected, a stop control table with a determined number of sliding symbols that do not have any combination And stop control of the reel. As a result, when a stop operation is performed, if the winning combination can be stopped on the winning line in the drawing range of up to 4 frames, the control is performed so that the winning combination is stopped. The combination that is not performed is stopped without being aligned in the drawing range of a maximum of 4 frames.

  When a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the winning small role is the maximum in the range of 4 frames on the winning line. The number of sliding frames is fixed so that it can be drawn to the limit, and for the stop operation position where the selected small role cannot be drawn in the range of up to 4 frames in the winning line, the winning special role is in the range of 4 frames in the winning line Then, a stop control table in which the number of sliding frames is determined so as to be pulled in as much as possible is created, and reel stop control is performed. As a result, when a stop operation is performed, if it is possible to stop all the small roles that have been selected in the drawing range of up to 4 frames on the winning line and stop them, control is performed so that the winning combination is stopped. If you can't draw a small role that has been won in the drawing range of up to 4 frames on the line, if you can stop with a special role that has been won in the drawing range of up to 4 frames on the winning line, Control is performed to align and stop this, and the winning combination that has not been won is controlled to be stopped without being aligned in the 4-frame pull-in range. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. When a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn in, and the small combination is not aligned on the winning line at the same time as the special combination.

  In this example, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are simultaneously elected, the special role and the small role are won simultaneously. If the selected special role is given priority over the selected special role, the special role is controlled on the winning line only when the small role cannot be withdrawn. When winning simultaneously, priority is given to the control for aligning the special role on the winning line over the small role, and the control for aligning the small role on the winning line may be performed only when the special role cannot be drawn.

  If a special player and a replaying player are elected at the same time, such as when a replaying player is elected while the special role has been carried over from before the previous game, when the stop operation is performed, In addition, a control is performed in which the symbols of the re-gamer are aligned and stopped within a drawing range of up to 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in, and the special combination is not arranged on the winning line at the same time as the re-playing combination.

  In this embodiment, after the rotation of the reels 2L, 2C, and 2R is started, the main control unit 41 rotates the reels for which the stop operation has not been detected yet until the operation of the stop switches 8L, 8C, and 8R is detected. Continuously, on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, control is performed to stop the display result on the corresponding reel. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In this embodiment, control is performed to stop the display result on the corresponding reel on condition that the operation of the stop switches 8L, 8C, and 8R is detected. However, the rotation of the reel is started. When a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. May be. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  In the present embodiment, the main control unit 41 measures the game time, which is the time elapsed from the start of the reel rotation every time the reel starts rotating after the game starts. After a game is over, when a specified number of bets are set by inserting medals, etc., and the game start operation is enabled, the reel start of the previous game is started. If the game time that started timing from the time point is equal to or longer than a predetermined restriction time (4.1 seconds in this embodiment), that is, if the predetermined restriction time has elapsed since the reel rotation start time of the previous game, At that time, the reels in the game are started to rotate.

  On the other hand, after the end of one game, when a predetermined number of bets are set by inserting medals, etc., and when the game start operation is enabled, the reel rotation of the previous game is started. If the game time that started timing from the time is less than the predetermined regulation time, that is, if the predetermined regulation time has not elapsed since the reel rotation start time of the previous game, the reel rotation is not started at that time, It waits until the game time that has started timing from the start of reel rotation of the previous game reaches a predetermined regulation time, and when the predetermined regulation time is reached, rotation of the reel in the game is started.

  Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described.

  In this embodiment, the main control unit 41 sends to the sub-control unit 91 an inserted number command, a credit command, an internal winning command, a reel rotation start command, a reel stop command, a winning number command, a payout start command, a payout end command, A plurality of types of commands including a return command, a gaming state command, a standby command, a stop command, an error command, a setting command, a setting confirmation command, a door command, and an operation detection command are transmitted.

  These commands consist of 1-byte type data indicating the command type and 1-byte extension data indicating the command content, and the sub-control unit 91 can determine the command type from the type data.

  The inserted number command is a command that can specify the number of inserted medals, that is, the number of medals used for setting the number of bets, and is a state from the end of the game (after changing the setting) to the start of the game. Or, when a prescribed number of bets is not set, a medal is inserted, or when the bet number is set by operating the MAXBET switch 6. The inserted number command is transmitted when the betting number setting operation is performed, so that it is possible to specify that the betting number setting operation has been performed by receiving the inserted number command.

  The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The internal winning command is a command that can specify the internal lottery result, and is transmitted when the start switch 7 is operated to start the game. Further, since the internal winning command is transmitted when the start switch 7 is operated, it is possible to specify that the start switch 7 has been operated by receiving the internal winning command.

  The reel rotation start command is a command for notifying the start of reel rotation in a game that is not controlled in the freeze state, which will be described later, and is transmitted when the rotation of the reels 2L, 2C, and 2R is started.

  The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, the area number of the corresponding reel stop operation position, and the area number of the corresponding reel stop position. And is transmitted each time stop control is performed in accordance with the stop operation of each reel. Since the reel stop command is transmitted when the stop switches 8L, 8C, and 8R are operated, it is possible to specify that the stop switches 8L, 8C, and 8R are operated by receiving the reel stop command. .

  The winning number command is a command that can specify the combination of symbols arranged on the winning line LN, whether or not there is a winning, the type of winning, the number of medals to be paid out, and all the reels are stopped and the winning determination is performed. Sent after.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption.

  The gaming state command is a command that can specify the current gaming state (in BB, in RB, replaying, etc.), and is transmitted when power is restored or when the game ends.

  The standby command is a command indicating a transition to the standby state, and after one game is over, a credit (which was used for setting the bet number) is set when the transition to the standby state is made after a predetermined time without setting the bet number. (Including medals) is sent out after the medal payout is completed and the payout end command is sent.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted.

  An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The setting command is a command indicating the start or end of the setting change state and the setting value after the setting change. At the time of transition to the setting change state, a setting command indicating the start of the setting change state is transmitted, and when the setting change state ends. A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting command indicating the start of setting. .

  The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of setting confirmation is transmitted when entering the setting confirmation state, and the setting confirmation end is indicated when the setting confirmation state ends. A confirmation command is sent.

  The door command is a command indicating the detection state of the door opening detection switch 25, that is, on (open state) / off (closed state), when the power is turned on, at the end of one game (after the game is over, the bet number of the next game) Sent before the setting of ”can be started), and when the detection state of the door opening detection switch 25 changes (from on to off, from off to on).

  The operation detection command is a command indicating the detection state (on / off) of the operation switches (MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R), and is transmitted periodically.

  Of these commands, commands other than the door command and the operation detection command are generated in the basic process, temporarily stored in the command queue provided in the RAM 41c, and transmitted in the command transmission process of the timer interrupt process (main) described above. The

  On the other hand, the door command is generated in the door monitoring process of the timer interrupt process (main), temporarily stored in the command queue provided in the RAM 41c, and transmitted in the subsequent command transmission process of the timer interrupt process (main). Is done.

  The operation detection command is generated based on the detection state of the switch every time the command transmission process of the timer interrupt process (main) is executed 10 times, and is temporarily stored in the command queue provided in the RAM 41c. Then, it is transmitted in the command transmission process of the subsequent timer interrupt process (main).

  Next, the control of the effect performed by the sub-control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  The reception buffer is provided with an area capable of storing a maximum of 16 commands so that a plurality of commands can be accumulated.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED 55, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  In particular, in this embodiment, when the betting number setting operation is performed during the execution of the effect, that is, when the sub-control unit 91 receives the inserted number command indicating that the betting number is set, The production is to be canceled. For this reason, if the player wants to proceed to the next game rather than seeing the production to the end, the production is canceled and the next game can be started. There is no. Further, when a credit or betting amount adjustment operation is performed during the performance, that is, after the sub-control unit 91 receives a game state command indicating the end of the game, it receives an internal winning command indicating the start of the game. When the payout start command is received before, the effect being executed is stopped. Credits and bets are settled when the game is terminated. In such a case, by terminating the performance that is being executed, there is an intention to end the game, but the performance continues unnecessarily. It is designed not to be overwhelmed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  In the present embodiment, the main control unit 41 controls the freeze state in which the operation for advancing the game for a predetermined period is invalidated by delaying the timing at which the operation for advancing the game is validated. A freeze lottery to determine whether or not is performed, and the freeze lottery is won to control the freeze state.

  In the present embodiment, the result of the freeze lottery is determined using the random number value generated by the channel RL1 of the random number circuit 508b.

  As already described with reference to FIG. 26, depending on the setting contents of the bit number [2-0] of the RL1 hard latch selection register (RL1LS), the input from the PI1 terminal (input of the operation detection signal of the MAXBET switch 6). , The RL1 hard latch random value register 0 (RL1HV0) is set so that the value of the 16-bit random number RL1 is taken in, and the RL1 hard latch random value register in the channel RL1 of the random number circuit 508b at the timing when the MAXBET switch 6 is operated. The random number value can be latched to 0 (RL1HV0), but the random number value generated by the channel RL1 of the random number circuit 508b is not latched at the timing according to the detection signal from the operation means, Corresponds to the channel RL1 of the random number circuit 508b at the timing. By setting “1” to bit 1 (RL1SL) of the random number soft latch register (RDSL), the program causes the RL1 soft latch random value register (RL1SV) in the channel RL1 of the random number circuit 508b to latch the random value and freeze lottery You may make it use for the result determination.

  As described above, in this embodiment, the freeze state is controlled according to the result of the freeze lottery. The random number circuit 508b mounted on the main control unit 41 is used for freeze lottery. The random number circuit 508b includes four circuits RL0 to RL3 that generate separate random numbers. In the freeze lottery, since the random number generated in the channel RL1 different from the random number generated in the channel RL0 used for the internal lottery among the random numbers generated by the random number circuit 508b is used, the random number used in the internal lottery and the freeze It can be prevented that the random numbers used in the lottery are synchronized.

  In the present embodiment, random numbers are extracted by extracting random numbers from different channels (channel 0 and channel 1) of the 16-bit random number circuit 508b to perform internal lottery and freeze lottery. Although the case where the random value to be made is different is shown, it is not limited to the mode shown in the present embodiment. For example, even in the same channel of the 16-bit random number circuit 508b, from different hard latch random number value registers used in the same channel (for example, RL0 hard latch random number value register 0 (RL0HV0) and RL0 hard latch random number value of the same channel 0) By extracting a random number value (from register 1 (RL0HV1)), the extracted random number value register may be different.

  In this embodiment, the random number generated by the 16-bit random number circuit 508b is used as the random number used in the freeze lottery. However, the random number generated by the 8-bit random number circuit 508a may be used.

  In this embodiment, the random number generated by the random number circuit 508b is used as the random number used by the freeze lottery. However, a soft random number updated by a program may be used as the random number used by the freeze lottery.

  Further, in this embodiment, the random number generated by the random number circuit 508b is used as a random number used in the freeze lottery for determining whether or not to control the freeze state. The random number generated by the random number circuits 508a and 508b may be used as the random number used for the lottery for determining whether or not to give a privilege advantageous to the player. Moreover, it is good also as a structure by which the result of a freeze lottery is reflected in the determination of the advantage for a player, and the determination of whether to give the privilege advantageous for a player.

  In the present embodiment, use / use of circuits (random number circuits 508a and 508b, watchdog timer 506b, reset / interrupt controller 506, etc.) mounted on the main control unit 41 according to the setting value of the program management area of the main control unit 41. Unused settings can be made. Unnecessary circuits can be set to unused so that circuits set to unused can not be activated. In such a configuration, even if a circuit that is not used is set to be unused, the circuit may operate due to illegal program activation, noise, or the like. If the microcomputer constituting the main control unit 41 is set at the time of factory shipment, the main control unit 41 may cause an unexpected operation.

  In this embodiment, each of the random number circuits 508a and 508b includes a four-channel random number circuit, and is set to start only channels 0 and 1 of the random number circuit 508b. The channels 2 and 3 of the circuit 508b are set to unused and are not activated. And, the setting value corresponding to the operation setting of the unused random number circuit in the program management area is a setting value different from the factory default value (all 0), and no problem occurs even if it operates temporarily. A set value is set. For this reason, even if a random number circuit set to be unused for some reason is operated, it is possible to prevent an unexpected operation due to the unused random number circuit.

  In this embodiment, among the random number circuits of channels 0 to 4 constituting the random number circuit 508b, channels 0 and 1 are set to use, and channels 2 and 3 are set to unused. Setting values (bits “6” and “5-4” of 16-bit random number initial setting 2 (KRL2)) corresponding to operation settings of unused random number circuits in the program management area for the channels 2 and 3 set to be used. And bit “2”, bit 1-0) set value, 16 bit random number initial setting 3 (KRL3 bit “7”, bit “6”, bit “5”, bit “4” set value) Set value of channel 0, 1 set to (16 bit random number initial setting 1 (KRL1) bit “6”, bit “5-4” and bit “2”, bit 1-0) set value, 16 bits Disorder Initialization 3 same set value (bit "3" of KRL3, bit "2", bit "1", the set value of the bit "0") is set. That is, a control circuit that is set to be used for one control circuit to be used among a plurality of control circuits of the same type, is set to be unused for another control circuit different from the one control circuit, and is set to be unused. As the operation setting, the same setting as the operation setting of the same kind of control circuit set to be used is set. For this reason, even if another control circuit set to unused for some reason operates, it is not the same as the factory default setting, but the same type of control circuit set to use By setting, the operation by the control circuit can be kept within the expected range.

  In this embodiment, the channels 2 and 3 of the random number circuit 508b are set to be unused and are not activated. However, the system reset of the channels 2 and 3 of the random number circuit 508b set to be unused is performed. As an operation setting for whether or not to change the initial value of the random number every time, the factory setting value (0), that is, the setting value that does not change the initial value of the random value every time the system is reset, is a system reset. A set value (1) for changing the initial value of the random value is set for each time. For this reason, even if it is an unused random number circuit, it becomes difficult to predict the update timing of the numerical data generated by the random number circuit activated by an unauthorized factor, and the specific numerical data targeted from the update timing of the random number It is possible to prevent fraudulent acts that illegally generate situations that are advantageous to the player.

  In this embodiment, the channels 2 and 3 of the random number circuit 508b are set to be unused and are not activated. However, the system reset of the channels 2 and 3 of the random number circuit 508b set to be unused is performed. After that, as an initial value for the first week of random number update, a setting value (1) that takes a value based on the ID number is set instead of 0001 based on the factory setting value (0). For this reason, even if it is an unused random number circuit, it becomes difficult to predict the update timing of the numerical data generated by the random number circuit activated by an unauthorized factor, and the specific numerical data targeted from the update timing of the random number It is possible to prevent fraudulent acts that illegally generate situations that are advantageous to the player.

  In this embodiment, the channels 0 to 3 of the random number circuit 508a and the channels 2 and 3 of the random number circuit 508b are set to unused and are not activated. However, these random number circuits set to unused. The factory setting value (00), that is, that the random number sequence is not changed is set as an operation setting for whether to change the update method of the random number sequence of the channels 0 to 3 of the channel 508a and the channels 2 and 3 of the random number circuit 508b. A setting value (10) for automatically changing the random number sequence is set instead of the setting value. For this reason, even if it is an unused random number circuit, it becomes difficult to predict the update timing of the numerical data generated by the random number circuit activated by an unauthorized factor, and the specific numerical data targeted from the update timing of the random number It is possible to prevent fraudulent acts that illegally generate situations that are advantageous to the player.

  In this embodiment, the channels 0 to 3 of the random number circuit 508a and the channels 2 and 3 of the random number circuit 508b are set unused and are not activated. However, the channels 0 to 3 of the random number circuit 508a are not activated. Even when an update abnormality is detected in the channels 2 and 3 of the random number circuit 508b, “1” is set in the corresponding bit of the internal information register (CIF), and the internal information register (CIF) By confirming this value, it is possible to confirm whether or not an update abnormality has been detected even in a random circuit set to be unused.

  In this embodiment, the CPU 41a acquires the value of the internal information register (CIF) in the error determination process performed at a predetermined opportunity, determines whether the value of the internal information register (CIF) is 0, Other than that, that is, whether one of the bits of the internal information register (CIF) is set to “1” and the frequency abnormality of the external clock signal is detected, whether the setting is used or not used. First, when an abnormality in the update state is detected in any of the channels 0 to 3 and the 16-bit random number circuit 506b of the 8-bit random number circuit 506a, the error state is controlled. That is, even if the cause of the abnormality is not specified from the value of each bit of the internal information register (CIF), if the CIF value is other than 0, it is clear that an abnormality has occurred around the random number circuit. The CPU 41a determines whether or not the entire value is 0 without specifying the value of each bit in the internal information register (CIF). If it is not 0, it determines that an error has occurred. Can reduce the program capacity.

  In the present embodiment, when the random number circuit mounted on the main control unit 41 is set to be unused, the operation setting is described as an example of setting values different from those at the time of shipment from the factory. For circuits that are set to unused, if there is a possibility that a failure will occur at the factory setting value, by setting a setting value different from the factory setting value so as not to cause a failure, Even if a circuit set to be unused is operated for some reason, it is possible to prevent an unexpected operation from being performed by an unused circuit.

  For example, when the serial communication circuit 512 is set to unused, the factory setting value (for example, setting to use as an attribute-less chip select terminal for an external device) is set as the function setting of the corresponding terminal. By setting different setting values (for example, setting to use as a communication terminal of the serial communication circuit 512), a terminal that is not used when the serial communication circuit 512 is set to be unused is connected to an external device. It is not set to be usable as an attributeless chip select terminal, and unauthorized use such as these terminals being used for reading illegal programs can be prevented.

  In addition, when the watchdog timer 506b is set to be unused, by setting other time instead of the factory setting value (0000) as the timeout time setting, system reset or user reset It is difficult to specify the timing of the system, and it is also difficult to specify the update timing of the hard random number or soft random number from the timing of the system reset or user reset. It is possible to prevent fraudulent acts that may cause a situation that is advantageous to the user.

  In addition, when a specific interrupt factor by the reset / interrupt controller 506 is set to unused, the factory setting value is used as an address setting for interrupt processing executed when the specific interrupt factor is generated. By setting other addresses instead of (00H), it is difficult to specify the storage address of the program to be executed when an interrupt occurs due to the generation of a specific interrupt factor set to unused. Therefore, it is possible to prevent an unauthorized act of executing an unauthorized program by generating the unused interrupt factor.

  Further, in the present embodiment, a part of the same type of control circuit is set to be used and the rest is set to be unused. However, all the same type of control circuits may be set to be unused. Even in such a configuration, if there is a possibility that a malfunction may occur at the factory setting value for a control circuit set to unused, the factory setting value is set so that the malfunction does not occur. By setting a setting value that is different from, even if a circuit that is set to be unused for some reason has been activated, it is possible to prevent an unexpected operation from being performed by the unused circuit. .

  In this embodiment, in the configuration in which a part of the same type of control circuit is set to use and the rest is set to unused, the operation setting for the circuit set to unused is set to use. The same settings as the operation settings for the circuit that is set to use, but only the operation settings that may cause problems at least with the factory default settings. However, it is possible to prevent an unexpected operation from being performed by an unused circuit when a circuit that has been set to unused has been operated for some reason.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  In the above embodiment, the present invention is applied to a slot machine in which bets are set using medals and credits as game values. However, slots for setting bets using game balls as game values are described. The present invention may be applied to a machine or a fully credit type slot machine that sets a bet amount using only credit as a gaming value. In the case of using a game ball as a game value, for example, one medal can correspond to five game balls, and when three bets are set in the first embodiment, 15 game balls are used. This is equivalent to setting the number of bets using.

  Further, the present invention is not limited to the use of only one of a plurality of types of game values such as medals and game balls, for example, a combination of a plurality of types of game values such as medals and game balls. It may be. That is, it is possible to play a game by setting the number of bets using any of a plurality of types of gaming values such as medals and game balls, and a plurality of types of games such as medals and game balls when a winning occurs. You may apply the slot machine which can pay out all of utility values.

  Furthermore, the present invention can be applied to any gaming machine equipped with not only a slot machine but also a microcomputer having a plurality of circuits, and can be used / unused of these installed circuits. The present invention can also be applied to a ball game machine that plays a game by launching a ball into the game area.

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main control unit 91 sub control unit 508a random number circuit 508b random number circuit

Claims (1)

In a gaming machine capable of performing a predetermined game,
A control circuit for performing predetermined control;
A storage area for storing at least information indicating whether to use the control circuit and information indicating whether control by the control circuit is performed with a setting different from a predetermined setting;
With
Even when information indicating that the control circuit is not used is stored in the storage area, information indicating that the control by the control circuit is performed with a setting different from a predetermined setting is stored. A gaming machine characterized by

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