JP2015535631A5 - - Google Patents

Download PDF

Info

Publication number
JP2015535631A5
JP2015535631A5 JP2015544069A JP2015544069A JP2015535631A5 JP 2015535631 A5 JP2015535631 A5 JP 2015535631A5 JP 2015544069 A JP2015544069 A JP 2015544069A JP 2015544069 A JP2015544069 A JP 2015544069A JP 2015535631 A5 JP2015535631 A5 JP 2015535631A5
Authority
JP
Japan
Prior art keywords
cache memory
dirty
line
mask
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015544069A
Other languages
English (en)
Japanese (ja)
Other versions
JP6009688B2 (ja
JP2015535631A (ja
Filing date
Publication date
Priority claimed from US13/687,761 external-priority patent/US9342461B2/en
Application filed filed Critical
Publication of JP2015535631A publication Critical patent/JP2015535631A/ja
Publication of JP2015535631A5 publication Critical patent/JP2015535631A5/ja
Application granted granted Critical
Publication of JP6009688B2 publication Critical patent/JP6009688B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2015544069A 2012-11-28 2013-10-28 動的に割り振られたダーティマスク空間を用いるメモリ管理 Expired - Fee Related JP6009688B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/687,761 US9342461B2 (en) 2012-11-28 2012-11-28 Cache memory system and method using dynamically allocated dirty mask space
US13/687,761 2012-11-28
PCT/US2013/067111 WO2014085002A1 (en) 2012-11-28 2013-10-28 Memory management using dynamically allocated dirty mask space

Publications (3)

Publication Number Publication Date
JP2015535631A JP2015535631A (ja) 2015-12-14
JP2015535631A5 true JP2015535631A5 (enExample) 2016-08-12
JP6009688B2 JP6009688B2 (ja) 2016-10-19

Family

ID=49551817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015544069A Expired - Fee Related JP6009688B2 (ja) 2012-11-28 2013-10-28 動的に割り振られたダーティマスク空間を用いるメモリ管理

Country Status (6)

Country Link
US (1) US9342461B2 (enExample)
EP (1) EP2926257B1 (enExample)
JP (1) JP6009688B2 (enExample)
KR (1) KR101662969B1 (enExample)
CN (1) CN104813293B (enExample)
WO (1) WO2014085002A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160026579A1 (en) * 2014-07-22 2016-01-28 Lsi Corporation Storage Controller and Method for Managing Metadata Operations in a Cache
KR102362239B1 (ko) 2015-12-30 2022-02-14 삼성전자주식회사 디램 캐시를 포함하는 메모리 시스템 및 그것의 캐시 관리 방법
US10585798B2 (en) * 2017-11-27 2020-03-10 Intel Corporation Tracking cache line consumption
US10705590B2 (en) * 2017-11-28 2020-07-07 Google Llc Power-conserving cache memory usage
US11099987B2 (en) * 2019-11-27 2021-08-24 Micron Technology, Inc. Bit masking valid sectors for write-back coalescing
US11630781B2 (en) * 2020-06-23 2023-04-18 Micron Technology, Inc. Cache metadata management
KR102806354B1 (ko) * 2020-08-31 2025-05-13 삼성전자주식회사 전자 장치, 시스템-온-칩, 및 그것의 동작 방법
JP7350699B2 (ja) * 2020-09-11 2023-09-26 株式会社東芝 ライトバックキャッシュ装置
CN112835532A (zh) * 2021-02-25 2021-05-25 上海壁仞智能科技有限公司 用于缓存控制的方法以及计算装置
KR102351237B1 (ko) 2021-04-29 2022-01-13 삼성전자주식회사 메모리 저장 장치 및 통신 시스템
US11681631B2 (en) * 2021-06-25 2023-06-20 Microsoft Technology Licensing, Llc Write-behind optimization of covering cache

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
US5802572A (en) * 1996-03-15 1998-09-01 International Business Machines Corporation Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache
JP3204295B2 (ja) * 1997-03-31 2001-09-04 日本電気株式会社 キャッシュメモリシステム
US6205521B1 (en) 1997-11-03 2001-03-20 Compaq Computer Corporation Inclusion map for accelerated cache flush
JP4434534B2 (ja) * 2001-09-27 2010-03-17 株式会社東芝 プロセッサ・システム
US7203798B2 (en) 2003-03-20 2007-04-10 Matsushita Electric Industrial Co., Ltd. Data memory cache unit and data memory cache system
US7127560B2 (en) * 2003-10-14 2006-10-24 International Business Machines Corporation Method of dynamically controlling cache size
EP1686484A4 (en) 2003-11-18 2008-10-15 Matsushita Electric Industrial Co Ltd CACHE MEMORY AND CONTROL PROCEDURE THEREFOR
KR100837479B1 (ko) 2003-12-22 2008-06-12 마쯔시다덴기산교 가부시키가이샤 캐시 메모리 및 그 제어 방법
CN100445944C (zh) * 2004-12-21 2008-12-24 三菱电机株式会社 控制电路以及控制方法
US20060143397A1 (en) 2004-12-29 2006-06-29 O'bleness R F Dirty line hint array for cache flushing
US7380070B2 (en) 2005-02-17 2008-05-27 Texas Instruments Incorporated Organization of dirty bits for a write-back cache
US20060274070A1 (en) 2005-04-19 2006-12-07 Herman Daniel L Techniques and workflows for computer graphics animation system
US8180968B2 (en) * 2007-03-28 2012-05-15 Oracle America, Inc. Reduction of cache flush time using a dirty line limiter
US7917699B2 (en) 2007-12-21 2011-03-29 Mips Technologies, Inc. Apparatus and method for controlling the exclusivity mode of a level-two cache
JP2011248389A (ja) * 2008-09-09 2011-12-08 Panasonic Corp キャッシュメモリ、キャッシュメモリシステム
TW201015319A (en) * 2008-09-17 2010-04-16 Panasonic Corp Cache memory, memory system, data copying method and data rewriting method
WO2010055494A1 (en) 2008-11-17 2010-05-20 Nxp B.V. A cache management policy and corresponding device
JP2012203560A (ja) * 2011-03-24 2012-10-22 Toshiba Corp キャッシュメモリおよびキャッシュシステム

Similar Documents

Publication Publication Date Title
JP2015535631A5 (enExample)
JP2017151982A5 (enExample)
JP2008529187A5 (enExample)
US10120832B2 (en) Direct access to local memory in a PCI-E device
US10198215B2 (en) System and method for multi-stream data write
JP2020524339A5 (enExample)
US11662952B2 (en) Memory system and method of controlling nonvolatile memory and for reducing a buffer size
US10120580B2 (en) Method and design for dynamic management of descriptors for SGL operation
US8438325B2 (en) Method and apparatus for improving small write performance in a non-volatile memory
JP6406707B2 (ja) 半導体記憶装置
JP2016522942A5 (enExample)
JP2009211227A5 (enExample)
JP2017502435A5 (enExample)
JP2015179307A (ja) キャッシュメモリ、誤り訂正回路およびプロセッサシステム
JP6746747B2 (ja) 記憶システム
JP2015035010A (ja) メモリシステムおよび情報処理装置
CN104603768A (zh) 信息处理设备
TW201102813A (en) Method and apparatus for performing random writing on a non-volatile memory
CN104408069A (zh) 一种基于布隆过滤器思想的一致性目录设计方法
KR20150076187A (ko) 메시지 시그널 인터럽트의 통신
CN103530241B (zh) 一种用户态的双控内存镜像实现方法
JP2023066803A (ja) メモリシステム
JP6517549B2 (ja) メモリコントローラ、記憶装置、データ転送システム、データ転送方法、及びデータ転送プログラム
CN111480151B (zh) 将高速缓存线从共用存储器页面冲洗到存储器
US20150254188A1 (en) Memory system and method of controlling memory system