KR101662969B1 - 동적으로 할당된 더티 마스크 공간을 이용한 메모리 관리 - Google Patents

동적으로 할당된 더티 마스크 공간을 이용한 메모리 관리 Download PDF

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KR101662969B1
KR101662969B1 KR1020157016404A KR20157016404A KR101662969B1 KR 101662969 B1 KR101662969 B1 KR 101662969B1 KR 1020157016404 A KR1020157016404 A KR 1020157016404A KR 20157016404 A KR20157016404 A KR 20157016404A KR 101662969 B1 KR101662969 B1 KR 101662969B1
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dirty
cache memory
line
cache
memory line
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KR20150091101A (ko
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지안 량
춘 유
페이 쉬
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020157016404A 2012-11-28 2013-10-28 동적으로 할당된 더티 마스크 공간을 이용한 메모리 관리 Expired - Fee Related KR101662969B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/687,761 2012-11-28
US13/687,761 US9342461B2 (en) 2012-11-28 2012-11-28 Cache memory system and method using dynamically allocated dirty mask space
PCT/US2013/067111 WO2014085002A1 (en) 2012-11-28 2013-10-28 Memory management using dynamically allocated dirty mask space

Publications (2)

Publication Number Publication Date
KR20150091101A KR20150091101A (ko) 2015-08-07
KR101662969B1 true KR101662969B1 (ko) 2016-10-05

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US (1) US9342461B2 (enExample)
EP (1) EP2926257B1 (enExample)
JP (1) JP6009688B2 (enExample)
KR (1) KR101662969B1 (enExample)
CN (1) CN104813293B (enExample)
WO (1) WO2014085002A1 (enExample)

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US20160026579A1 (en) * 2014-07-22 2016-01-28 Lsi Corporation Storage Controller and Method for Managing Metadata Operations in a Cache
KR102362239B1 (ko) 2015-12-30 2022-02-14 삼성전자주식회사 디램 캐시를 포함하는 메모리 시스템 및 그것의 캐시 관리 방법
US10585798B2 (en) * 2017-11-27 2020-03-10 Intel Corporation Tracking cache line consumption
US10705590B2 (en) * 2017-11-28 2020-07-07 Google Llc Power-conserving cache memory usage
US11099987B2 (en) * 2019-11-27 2021-08-24 Micron Technology, Inc. Bit masking valid sectors for write-back coalescing
US11630781B2 (en) * 2020-06-23 2023-04-18 Micron Technology, Inc. Cache metadata management
KR102806354B1 (ko) * 2020-08-31 2025-05-13 삼성전자주식회사 전자 장치, 시스템-온-칩, 및 그것의 동작 방법
JP7350699B2 (ja) * 2020-09-11 2023-09-26 株式会社東芝 ライトバックキャッシュ装置
CN112835532A (zh) * 2021-02-25 2021-05-25 上海壁仞智能科技有限公司 用于缓存控制的方法以及计算装置
KR102351237B1 (ko) 2021-04-29 2022-01-13 삼성전자주식회사 메모리 저장 장치 및 통신 시스템
US11681631B2 (en) 2021-06-25 2023-06-20 Microsoft Technology Licensing, Llc Write-behind optimization of covering cache

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WO2010055494A1 (en) 2008-11-17 2010-05-20 Nxp B.V. A cache management policy and corresponding device
US20120246410A1 (en) 2011-03-24 2012-09-27 Kabushiki Kaisha Toshiba Cache memory and cache system

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US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
US5802572A (en) * 1996-03-15 1998-09-01 International Business Machines Corporation Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache
JP3204295B2 (ja) * 1997-03-31 2001-09-04 日本電気株式会社 キャッシュメモリシステム
US6205521B1 (en) 1997-11-03 2001-03-20 Compaq Computer Corporation Inclusion map for accelerated cache flush
JP4434534B2 (ja) * 2001-09-27 2010-03-17 株式会社東芝 プロセッサ・システム
US7203798B2 (en) 2003-03-20 2007-04-10 Matsushita Electric Industrial Co., Ltd. Data memory cache unit and data memory cache system
US7127560B2 (en) * 2003-10-14 2006-10-24 International Business Machines Corporation Method of dynamically controlling cache size
KR100826757B1 (ko) 2003-11-18 2008-04-30 마쯔시다덴기산교 가부시키가이샤 캐시 메모리 및 그 제어 방법
WO2005066796A1 (ja) 2003-12-22 2005-07-21 Matsushita Electric Industrial Co., Ltd. キャッシュメモリ及びその制御方法
CN100445944C (zh) * 2004-12-21 2008-12-24 三菱电机株式会社 控制电路以及控制方法
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US7380070B2 (en) 2005-02-17 2008-05-27 Texas Instruments Incorporated Organization of dirty bits for a write-back cache
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JP2011248389A (ja) * 2008-09-09 2011-12-08 Panasonic Corp キャッシュメモリ、キャッシュメモリシステム
TW201015319A (en) * 2008-09-17 2010-04-16 Panasonic Corp Cache memory, memory system, data copying method and data rewriting method

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US20120246410A1 (en) 2011-03-24 2012-09-27 Kabushiki Kaisha Toshiba Cache memory and cache system

Also Published As

Publication number Publication date
WO2014085002A1 (en) 2014-06-05
US9342461B2 (en) 2016-05-17
EP2926257B1 (en) 2019-06-26
JP2015535631A (ja) 2015-12-14
JP6009688B2 (ja) 2016-10-19
CN104813293A (zh) 2015-07-29
EP2926257A1 (en) 2015-10-07
CN104813293B (zh) 2017-10-31
US20140149685A1 (en) 2014-05-29
KR20150091101A (ko) 2015-08-07

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