JP2015529363A5 - - Google Patents
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- JP2015529363A5 JP2015529363A5 JP2015529830A JP2015529830A JP2015529363A5 JP 2015529363 A5 JP2015529363 A5 JP 2015529363A5 JP 2015529830 A JP2015529830 A JP 2015529830A JP 2015529830 A JP2015529830 A JP 2015529830A JP 2015529363 A5 JP2015529363 A5 JP 2015529363A5
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/602,958 US9183614B2 (en) | 2011-09-03 | 2012-09-04 | Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets |
| US13/602,958 | 2012-09-04 | ||
| PCT/US2013/054340 WO2014039210A1 (en) | 2012-09-04 | 2013-08-09 | Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015529363A JP2015529363A (ja) | 2015-10-05 |
| JP2015529363A5 true JP2015529363A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 2016-09-23 |
| JP6388865B2 JP6388865B2 (ja) | 2018-09-12 |
Family
ID=49036636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015529830A Expired - Fee Related JP6388865B2 (ja) | 2012-09-04 | 2013-08-09 | 相互関係のある二次元データセットを効率的かつ高速に処理するプロセッサ、システム、および方法 |
Country Status (6)
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9183614B2 (en) | 2011-09-03 | 2015-11-10 | Mireplica Technology, Llc | Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets |
| CN105608022B (zh) * | 2014-11-25 | 2017-08-01 | 南方电网科学研究院有限责任公司 | 一种基于倒排技术的智能安全芯片的指令分发方法和系统 |
| US9898292B2 (en) * | 2015-02-25 | 2018-02-20 | Mireplica Technology, Llc | Hardware instruction generation unit for specialized processors |
| JP6771018B2 (ja) * | 2015-07-23 | 2020-10-21 | マイヤプリカ テクノロジー エルエルシー | 二次元配列プロセッサの性能向上 |
| US10535114B2 (en) * | 2015-08-18 | 2020-01-14 | Nvidia Corporation | Controlling multi-pass rendering sequences in a cache tiling architecture |
| US10204396B2 (en) * | 2016-02-26 | 2019-02-12 | Google Llc | Compiler managed memory for image processor |
| CN106603692B (zh) * | 2016-12-27 | 2020-12-01 | 中国银联股份有限公司 | 一种分布式存储系统中的数据存储方法及装置 |
| CN111126589B (zh) * | 2019-12-31 | 2022-05-20 | 昆仑芯(北京)科技有限公司 | 神经网络数据处理装置、方法和电子设备 |
| CN113568665B (zh) * | 2020-04-29 | 2023-11-17 | 北京希姆计算科技有限公司 | 一种数据处理装置 |
| CN113341959B (zh) * | 2021-05-25 | 2022-02-11 | 吉利汽车集团有限公司 | 一种机器人数据统计方法及其系统 |
| US12050532B2 (en) | 2022-09-23 | 2024-07-30 | Apple Inc. | Routing circuit for computer resource topology |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5129092A (en) | 1987-06-01 | 1992-07-07 | Applied Intelligent Systems,Inc. | Linear chain of parallel processors and method of using same |
| US6948050B1 (en) * | 1989-11-17 | 2005-09-20 | Texas Instruments Incorporated | Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware |
| JPH04114262A (ja) * | 1990-09-05 | 1992-04-15 | Fujitsu Ltd | 高速データ処理装置 |
| JPH05151347A (ja) * | 1991-11-28 | 1993-06-18 | Olympus Optical Co Ltd | 並列画像処理プロセツサ |
| US6116768A (en) * | 1993-11-30 | 2000-09-12 | Texas Instruments Incorporated | Three input arithmetic logic unit with barrel rotator |
| EP1181648A1 (en) * | 1999-04-09 | 2002-02-27 | Clearspeed Technology Limited | Parallel data processing apparatus |
| US7526630B2 (en) | 1999-04-09 | 2009-04-28 | Clearspeed Technology, Plc | Parallel data processing apparatus |
| US6832307B2 (en) | 2001-07-19 | 2004-12-14 | Stmicroelectronics, Inc. | Instruction fetch buffer stack fold decoder for generating foldable instruction status information |
| CN101084483A (zh) | 2004-05-03 | 2007-12-05 | 硅奥普迪思公司 | 用于simd阵列处理机的位串行处理元件 |
| TWI256560B (en) | 2004-06-15 | 2006-06-11 | Sunplus Technology Co Ltd | A system with dynamic adjustable coprocessor numbers |
| US20080235490A1 (en) * | 2004-06-18 | 2008-09-25 | Anthony Mark Jones | System for configuring a processor array |
| US8024549B2 (en) * | 2005-03-04 | 2011-09-20 | Mtekvision Co., Ltd. | Two-dimensional processor array of processing elements |
| US8032688B2 (en) * | 2005-06-30 | 2011-10-04 | Intel Corporation | Micro-tile memory interfaces |
| US8878860B2 (en) * | 2006-12-28 | 2014-11-04 | Intel Corporation | Accessing memory using multi-tiling |
| JP5101128B2 (ja) | 2007-02-21 | 2012-12-19 | 株式会社東芝 | メモリ管理システム |
| US20080235493A1 (en) | 2007-03-23 | 2008-09-25 | Qualcomm Incorporated | Instruction communication techniques for multi-processor system |
| US10078620B2 (en) | 2011-05-27 | 2018-09-18 | New York University | Runtime reconfigurable dataflow processor with multi-port memory access module |
| US9183614B2 (en) | 2011-09-03 | 2015-11-10 | Mireplica Technology, Llc | Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets |
-
2012
- 2012-09-04 US US13/602,958 patent/US9183614B2/en not_active Expired - Fee Related
-
2013
- 2013-08-09 HK HK15111225.7A patent/HK1210530A1/xx unknown
- 2013-08-09 KR KR1020157008715A patent/KR102106360B1/ko not_active Expired - Fee Related
- 2013-08-09 JP JP2015529830A patent/JP6388865B2/ja not_active Expired - Fee Related
- 2013-08-09 WO PCT/US2013/054340 patent/WO2014039210A1/en unknown
- 2013-08-09 EP EP13753372.5A patent/EP2893460A1/en not_active Withdrawn
-
2015
- 2015-04-23 US US14/694,053 patent/US10013733B2/en not_active Expired - Fee Related
- 2015-04-23 US US14/694,066 patent/US10540734B2/en not_active Expired - Fee Related
- 2015-11-09 US US14/935,801 patent/US9984432B2/en not_active Expired - Fee Related
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