JP2015524203A5 - - Google Patents
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- Publication number
- JP2015524203A5 JP2015524203A5 JP2015514983A JP2015514983A JP2015524203A5 JP 2015524203 A5 JP2015524203 A5 JP 2015524203A5 JP 2015514983 A JP2015514983 A JP 2015514983A JP 2015514983 A JP2015514983 A JP 2015514983A JP 2015524203 A5 JP2015524203 A5 JP 2015524203A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- controlled oscillator
- output
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/484,236 US8724764B2 (en) | 2012-05-30 | 2012-05-30 | Distortion tolerant clock and data recovery |
| US13/484,236 | 2012-05-30 | ||
| PCT/US2013/023926 WO2013180766A1 (en) | 2012-05-30 | 2013-01-30 | Distortion tolerant clock and data recovery system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015524203A JP2015524203A (ja) | 2015-08-20 |
| JP2015524203A5 true JP2015524203A5 (enExample) | 2016-01-28 |
| JP5937753B2 JP5937753B2 (ja) | 2016-06-22 |
Family
ID=47710353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015514983A Active JP5937753B2 (ja) | 2012-05-30 | 2013-01-30 | 歪耐性クロックデータリカバリシステム |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8724764B2 (enExample) |
| EP (1) | EP2856648B1 (enExample) |
| JP (1) | JP5937753B2 (enExample) |
| KR (1) | KR102023796B1 (enExample) |
| CN (1) | CN104488195B (enExample) |
| WO (1) | WO2013180766A1 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9590567B2 (en) | 2015-07-02 | 2017-03-07 | Xilinx, Inc. | Moving mean and magnitude dual path digital predistortion |
| US9992049B1 (en) * | 2016-06-17 | 2018-06-05 | Xilinx, Inc. | Numerically controlled oscillator for fractional burst clock data recovery applications |
| US11129596B2 (en) * | 2016-10-06 | 2021-09-28 | General Electric Company | Systems and methods for ultrasound multiplexing |
| US10348312B1 (en) | 2018-05-30 | 2019-07-09 | Xilinx, Inc. | Circuit for and method of implementing a bursty clock and data recovery circuit using an eyescan detection circuit |
| US11705910B1 (en) | 2022-01-05 | 2023-07-18 | Xilinx, Inc. | Fast line rate switching in peripheral component interconnect express (PCIe) analyzers |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5301196A (en) | 1992-03-16 | 1994-04-05 | International Business Machines Corporation | Half-speed clock recovery and demultiplexer circuit |
| EP0758171A3 (en) * | 1995-08-09 | 1997-11-26 | Symbios Logic Inc. | Data sampling and recovery |
| US6531926B1 (en) * | 2001-09-13 | 2003-03-11 | Overture Networks, Inc. | Dynamic control of phase-locked loop |
| US7049869B2 (en) * | 2003-09-02 | 2006-05-23 | Gennum Corporation | Adaptive lock position circuit |
| US20060064725A1 (en) * | 2004-09-22 | 2006-03-23 | Rosum Corporation | Pilot acquisition and local clock calibration with reduced MIPS |
| US7751521B2 (en) | 2004-11-16 | 2010-07-06 | Electronics And Telecommunications Research Institute | Clock and data recovery apparatus |
| KR100724895B1 (ko) * | 2005-06-17 | 2007-06-04 | 삼성전자주식회사 | 위상고정루프와 위상고정루프에서의 위상 검출방법 및 그를이용하는 수신기 |
| US7580497B2 (en) * | 2005-06-29 | 2009-08-25 | Altera Corporation | Clock data recovery loop with separate proportional path |
| US7268633B2 (en) * | 2005-09-12 | 2007-09-11 | P.A. Semi, Inc. | Voltage-controlled oscillator for low-voltage, wide frequency range operation |
| US7996749B2 (en) * | 2007-07-03 | 2011-08-09 | Altera Corporation | Signal loss detector for high-speed serial interface of a programmable logic device |
| US7692501B2 (en) * | 2007-09-14 | 2010-04-06 | Intel Corporation | Phase/frequency detector and charge pump architecture for referenceless clock and data recovery (CDR) applications |
| US20090154626A1 (en) * | 2007-12-15 | 2009-06-18 | Anderson Warren R | Continuous receiver clock alignment and equalization optimization |
| CA2774482C (en) | 2008-10-02 | 2015-12-01 | Zenko Technologies, Inc. | Data sampling circuit and method for clock and data recovery |
| JP5385718B2 (ja) | 2009-07-28 | 2014-01-08 | ルネサスエレクトロニクス株式会社 | クロックデータリカバリ回路 |
| CN101777911A (zh) * | 2010-01-08 | 2010-07-14 | 智原科技股份有限公司 | 时钟数据恢复器 |
-
2012
- 2012-05-30 US US13/484,236 patent/US8724764B2/en active Active
-
2013
- 2013-01-30 JP JP2015514983A patent/JP5937753B2/ja active Active
- 2013-01-30 EP EP13703978.0A patent/EP2856648B1/en active Active
- 2013-01-30 KR KR1020147036755A patent/KR102023796B1/ko active Active
- 2013-01-30 WO PCT/US2013/023926 patent/WO2013180766A1/en not_active Ceased
- 2013-01-30 CN CN201380039014.8A patent/CN104488195B/zh active Active
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