JP2015518995A5 - - Google Patents

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Publication number
JP2015518995A5
JP2015518995A5 JP2015516123A JP2015516123A JP2015518995A5 JP 2015518995 A5 JP2015518995 A5 JP 2015518995A5 JP 2015516123 A JP2015516123 A JP 2015516123A JP 2015516123 A JP2015516123 A JP 2015516123A JP 2015518995 A5 JP2015518995 A5 JP 2015518995A5
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JP
Japan
Prior art keywords
instruction
pipeline
execution
execution pipeline
priority
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JP2015516123A
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English (en)
Japanese (ja)
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JP6317339B2 (ja
JP2015518995A (ja
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Priority claimed from US13/741,849 external-priority patent/US9858077B2/en
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Publication of JP2015518995A publication Critical patent/JP2015518995A/ja
Publication of JP2015518995A5 publication Critical patent/JP2015518995A5/ja
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Publication of JP6317339B2 publication Critical patent/JP6317339B2/ja
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JP2015516123A 2012-06-05 2013-06-04 レジスタ関連優先度に基づく実行パイプラインへの命令の発行、ならびに関係する命令処理回路、プロセッサシステム、方法、およびコンピュータ可読媒体 Active JP6317339B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261655655P 2012-06-05 2012-06-05
US61/655,655 2012-06-05
US13/741,849 2013-01-15
US13/741,849 US9858077B2 (en) 2012-06-05 2013-01-15 Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media
PCT/US2013/044125 WO2013184689A1 (en) 2012-06-05 2013-06-04 Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media

Publications (3)

Publication Number Publication Date
JP2015518995A JP2015518995A (ja) 2015-07-06
JP2015518995A5 true JP2015518995A5 (enExample) 2016-07-07
JP6317339B2 JP6317339B2 (ja) 2018-04-25

Family

ID=49671778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015516123A Active JP6317339B2 (ja) 2012-06-05 2013-06-04 レジスタ関連優先度に基づく実行パイプラインへの命令の発行、ならびに関係する命令処理回路、プロセッサシステム、方法、およびコンピュータ可読媒体

Country Status (5)

Country Link
US (1) US9858077B2 (enExample)
EP (1) EP2856304B1 (enExample)
JP (1) JP6317339B2 (enExample)
CN (1) CN104335167B (enExample)
WO (1) WO2013184689A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160364237A1 (en) * 2014-03-27 2016-12-15 Intel Corporation Processor logic and method for dispatching instructions from multiple strands
US10152101B2 (en) * 2015-09-22 2018-12-11 Qualcomm Incorporated Controlling voltage deviations in processing systems
US20230315446A1 (en) * 2022-03-30 2023-10-05 Fujitsu Limited Arithmetic processing apparatus and method for arithmetic processing
US11855831B1 (en) 2022-06-10 2023-12-26 T-Mobile Usa, Inc. Enabling an operator to resolve an issue associated with a 5G wireless telecommunication network using AR glasses
US11886767B2 (en) 2022-06-17 2024-01-30 T-Mobile Usa, Inc. Enable interaction between a user and an agent of a 5G wireless telecommunication network using augmented reality glasses

Family Cites Families (21)

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US5021945A (en) * 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US6047369A (en) 1994-02-28 2000-04-04 Intel Corporation Flag renaming and flag masks within register alias table
US5956747A (en) * 1994-12-15 1999-09-21 Sun Microsystems, Inc. Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines
JPH10143365A (ja) 1996-11-15 1998-05-29 Toshiba Corp 並列処理装置及びその命令発行方式
US5963723A (en) 1997-03-26 1999-10-05 International Business Machines Corporation System for pairing dependent instructions having non-contiguous addresses during dispatch
US5941983A (en) 1997-06-24 1999-08-24 Hewlett-Packard Company Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues
JP3209205B2 (ja) 1998-04-28 2001-09-17 日本電気株式会社 プロセッサにおけるレジスタ内容の継承装置
US6643762B1 (en) * 2000-01-24 2003-11-04 Hewlett-Packard Development Company, L.P. Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs
US6862677B1 (en) 2000-02-16 2005-03-01 Koninklijke Philips Electronics N.V. System and method for eliminating write back to register using dead field indicator
US6728866B1 (en) 2000-08-31 2004-04-27 International Business Machines Corporation Partitioned issue queue and allocation strategy
US6754807B1 (en) * 2000-08-31 2004-06-22 Stmicroelectronics, Inc. System and method for managing vertical dependencies in a digital signal processor
US6976152B2 (en) * 2001-09-24 2005-12-13 Broadcom Corporation Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard
US20040181651A1 (en) * 2003-03-11 2004-09-16 Sugumar Rabin A. Issue bandwidth in a multi-issue out-of-order processor
US7571302B1 (en) 2004-02-04 2009-08-04 Lei Chen Dynamic data dependence tracking and its application to branch prediction
US20060095732A1 (en) 2004-08-30 2006-05-04 Tran Thang M Processes, circuits, devices, and systems for scoreboard and other processor improvements
US20060190710A1 (en) 2005-02-24 2006-08-24 Bohuslav Rychlik Suppressing update of a branch history register by loop-ending branches
US7774582B2 (en) 2005-05-26 2010-08-10 Arm Limited Result bypassing to override a data hazard within a superscalar processor
US20070022277A1 (en) 2005-07-20 2007-01-25 Kenji Iwamura Method and system for an enhanced microprocessor
US20070260856A1 (en) 2006-05-05 2007-11-08 Tran Thang M Methods and apparatus to detect data dependencies in an instruction pipeline
US8055883B2 (en) * 2009-07-01 2011-11-08 Arm Limited Pipe scheduling for pipelines based on destination register number
US20120023314A1 (en) 2010-07-21 2012-01-26 Crum Matthew M Paired execution scheduling of dependent micro-operations

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