JP2015510255A - 多層構造体を基板に製造する方法 - Google Patents
多層構造体を基板に製造する方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title abstract description 29
- 239000000758 substrate Substances 0.000 title abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 32
- 239000011521 glass Substances 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Element Separation (AREA)
- Joining Of Glass To Other Materials (AREA)
Abstract
Description
1/2VvEvεv = 1/2VsEsεs (1)
ここで、Vvが最後の支持体の体積であり、Vsが最初の支持体の体積であり、Evが最後の支持体のヤング率であり、Esが最初の支持体のヤング率であり、εv が最後の支持体の変形量であり、εs が最初の支持体の変形量である。ヤング率Ev及びヤング率Esは、結合面と平行な面で測定されたヤング率である。支持体の内の一方のヤング率が、結合面と平行な面で一定ではないことがある。この場合、関係式(1)のヤング率Es又はヤング率Evは平均値に相当する。
VvEv = VsEs (2)
es = Ev/Es・ev (3)
ここで、esが最初の支持体の厚さであり、evが最後の支持体の厚さである。一般に、集積回路ウエハをガラス製の支持体に形成するために、ガラス製の支持体のヤング率は約70GPa である一方、単結晶シリコン製の最初の支持体のヤング率は約140GPaである。その結果、最初の支持体の厚さesは、以下の関係式(4)によって得られる。
Claims (9)
- 多層構造体(16)を第1の支持体(30)に製造する方法において、
ヤング率Ev及び厚さevを有する第1の材料から形成された前記第1の支持体、及び、前記多層構造体で覆われてヤング率Evとは異なるヤング率Es及び厚さesを有する第2の材料から形成された第2の支持体(12)を準備する工程、
前記第1の支持体及び前記多層構造体の分子結合を行う結合工程、及び
前記第2の支持体を除去する工程
を順次的に有し、
厚さes及び厚さevは、es=Ev/Es・evの関係式を10%の範囲内で満たすことを特徴とする製造方法。 - 前記第2の支持体(12)は、厚さesより大きな厚さを最初に有しており、
前記製造方法は、前記結合工程の前に、前記第2の支持体を厚さesまで薄くする工程を更に有することを特徴とする請求項1に記載の製造方法。 - 厚さes及び厚さevは50μmより大きいことを特徴とする請求項1又は2に記載の製造方法。
- 前記第2の材料は単結晶シリコンであることを特徴とする請求項1乃至3のいずれかに記載の製造方法。
- 前記第1の材料は絶縁性を有することを特徴とする請求項1乃至4のいずれかに記載の製造方法。
- 前記第1の材料は透明であることを特徴とする請求項1乃至5のいずれかに記載の製造方法。
- 前記第1の材料はガラスであることを特徴とする請求項1乃至6のいずれかに記載の製造方法。
- ヤング率Ev及び厚さevを有する第1の材料から形成された更なる支持体(30)に結合されるべき多層構造体(16)のための支持体(12)において、
該支持体は、ヤング率Evとは異なるヤング率Esと、es=Ev/Es・evの関係式を10%の範囲内で満たす厚さesとを有する第2の材料から形成されていることを特徴とする支持体。 - 前記第2の材料は単結晶シリコンであることを特徴とする請求項8に記載の支持体。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1162525 | 2011-12-29 | ||
FR1162525A FR2985371A1 (fr) | 2011-12-29 | 2011-12-29 | Procede de fabrication d'une structure multicouche sur un support |
PCT/FR2012/053089 WO2013098528A1 (fr) | 2011-12-29 | 2012-12-27 | Procede de fabrication d'une structure multicouche sur un support |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015510255A true JP2015510255A (ja) | 2015-04-02 |
JP5770949B2 JP5770949B2 (ja) | 2015-08-26 |
Family
ID=47628332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014549523A Expired - Fee Related JP5770949B2 (ja) | 2011-12-29 | 2012-12-27 | 多層構造体を基板に製造する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9362255B2 (ja) |
EP (1) | EP2798667B1 (ja) |
JP (1) | JP5770949B2 (ja) |
FR (1) | FR2985371A1 (ja) |
WO (1) | WO2013098528A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2985369B1 (fr) * | 2011-12-29 | 2014-01-10 | Commissariat Energie Atomique | Procede de fabrication d'une structure multicouche sur un support |
DE102015210384A1 (de) | 2015-06-05 | 2016-12-08 | Soitec | Verfahren zur mechanischen Trennung für eine Doppelschichtübertragung |
CN114071903B (zh) * | 2020-07-31 | 2024-04-05 | 群创光电股份有限公司 | 可挠性电子装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004247405A (ja) * | 2003-02-12 | 2004-09-02 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
WO2009090780A1 (ja) * | 2008-01-15 | 2009-07-23 | Sharp Kabushiki Kaisha | 半導体装置、その製造方法及び表示装置 |
JP2009177155A (ja) * | 2007-12-28 | 2009-08-06 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法 |
WO2011010685A1 (ja) * | 2009-07-24 | 2011-01-27 | 日本電気硝子株式会社 | 太陽電池用導電膜付ガラス基板 |
JP2013534056A (ja) * | 2010-06-30 | 2013-08-29 | コーニング インコーポレイテッド | 補剛層を有するガラス上半導体基板及びその作製プロセス |
JP2013239716A (ja) * | 2006-09-06 | 2013-11-28 | Board Of Trustees Of The Univ Of Illinois | 2次元デバイスアレイ |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US7094666B2 (en) * | 2004-07-29 | 2006-08-22 | Silicon Genesis Corporation | Method and system for fabricating strained layers for the manufacture of integrated circuits |
US7427554B2 (en) * | 2005-08-12 | 2008-09-23 | Silicon Genesis Corporation | Manufacturing strained silicon substrates using a backing material |
JP2008066500A (ja) * | 2006-09-07 | 2008-03-21 | Sumco Corp | 貼り合わせウェーハおよびその製造方法 |
US7811900B2 (en) | 2006-09-08 | 2010-10-12 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a thick layer transfer process |
JP4820801B2 (ja) * | 2006-12-26 | 2011-11-24 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
US8450779B2 (en) * | 2010-03-08 | 2013-05-28 | International Business Machines Corporation | Graphene based three-dimensional integrated circuit device |
JP5752264B2 (ja) * | 2010-12-27 | 2015-07-22 | シャンハイ シングイ テクノロジー カンパニー リミテッドShanghai Simgui Technology Co., Ltd | 不純物のゲッタリングプロセスで絶縁層付きの半導体基板を製造する方法 |
JP5959877B2 (ja) * | 2012-02-17 | 2016-08-02 | キヤノン株式会社 | 撮像装置 |
US9709740B2 (en) * | 2012-06-04 | 2017-07-18 | Micron Technology, Inc. | Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate |
-
2011
- 2011-12-29 FR FR1162525A patent/FR2985371A1/fr not_active Withdrawn
-
2012
- 2012-12-27 JP JP2014549523A patent/JP5770949B2/ja not_active Expired - Fee Related
- 2012-12-27 WO PCT/FR2012/053089 patent/WO2013098528A1/fr active Application Filing
- 2012-12-27 US US14/369,701 patent/US9362255B2/en not_active Expired - Fee Related
- 2012-12-27 EP EP12819115.2A patent/EP2798667B1/fr not_active Not-in-force
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004247405A (ja) * | 2003-02-12 | 2004-09-02 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2013239716A (ja) * | 2006-09-06 | 2013-11-28 | Board Of Trustees Of The Univ Of Illinois | 2次元デバイスアレイ |
JP2009177155A (ja) * | 2007-12-28 | 2009-08-06 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法 |
WO2009090780A1 (ja) * | 2008-01-15 | 2009-07-23 | Sharp Kabushiki Kaisha | 半導体装置、その製造方法及び表示装置 |
WO2011010685A1 (ja) * | 2009-07-24 | 2011-01-27 | 日本電気硝子株式会社 | 太陽電池用導電膜付ガラス基板 |
JP2013534056A (ja) * | 2010-06-30 | 2013-08-29 | コーニング インコーポレイテッド | 補剛層を有するガラス上半導体基板及びその作製プロセス |
Also Published As
Publication number | Publication date |
---|---|
JP5770949B2 (ja) | 2015-08-26 |
EP2798667B1 (fr) | 2016-03-09 |
EP2798667A1 (fr) | 2014-11-05 |
FR2985371A1 (fr) | 2013-07-05 |
WO2013098528A1 (fr) | 2013-07-04 |
US9362255B2 (en) | 2016-06-07 |
US20140353853A1 (en) | 2014-12-04 |
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