WO2011104461A3 - Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche - Google Patents

Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche Download PDF

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Publication number
WO2011104461A3
WO2011104461A3 PCT/FR2011/050238 FR2011050238W WO2011104461A3 WO 2011104461 A3 WO2011104461 A3 WO 2011104461A3 FR 2011050238 W FR2011050238 W FR 2011050238W WO 2011104461 A3 WO2011104461 A3 WO 2011104461A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
multilayer structure
fragments
material present
eliminating
Prior art date
Application number
PCT/FR2011/050238
Other languages
English (en)
Other versions
WO2011104461A2 (fr
Inventor
Bénédicte OSTERNAUD
Original Assignee
Soitec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec filed Critical Soitec
Priority to CN2011800104804A priority Critical patent/CN102763191A/zh
Priority to JP2012554392A priority patent/JP2013520829A/ja
Priority to KR1020127022089A priority patent/KR20120137475A/ko
Priority to SG2012059895A priority patent/SG183298A1/en
Priority to EP11707462A priority patent/EP2539922A2/fr
Priority to US13/580,860 priority patent/US20130045584A1/en
Publication of WO2011104461A2 publication Critical patent/WO2011104461A2/fr
Publication of WO2011104461A3 publication Critical patent/WO2011104461A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01J—CHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS OR COLLOID CHEMISTRY; THEIR RELEVANT APPARATUS
    • B01J19/00—Chemical, physical or physico-chemical processes in general; Their relevant apparatus
    • B01J19/08—Processes employing the direct application of electric or wave energy, or particle radiation; Apparatus therefor
    • B01J19/10—Processes employing the direct application of electric or wave energy, or particle radiation; Apparatus therefor employing sonic or ultrasonic vibrations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Abstract

L'invention concerne un procédé d'élimination de fragments de matériau (118) présents sur Ia surface exposée d'une première couche (116) collée sur une deuxième plaque (110), le procédé comprenant une étape consistant à placer la première couche (116) dans une solution liquide et à propager dans la solution des ondes ultrasonores. L'invention concerne en outre un procédé de fabrication d'une structure multicouche (111) comprenant les étapes successives suivantes: collage d'une première plaque sur une deuxième plaque de manière à former une structure multicouche, recuit de la structure, amincissement de la première plaque comprenant au moins une étape de gravure chimique de la première plaque, le procédé comprenant en outre, après l'étape de gravure chimique, l'élimination de fragments de matériau (118) présents sur la surface exposée de la première plaque amincie (116).
PCT/FR2011/050238 2010-02-26 2011-02-07 Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche WO2011104461A2 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN2011800104804A CN102763191A (zh) 2010-02-26 2011-02-07 消除多层结构的表面上存在的材料碎片的方法
JP2012554392A JP2013520829A (ja) 2010-02-26 2011-02-07 多層構造体の表面に存在する材料の断片を除去する方法
KR1020127022089A KR20120137475A (ko) 2010-02-26 2011-02-07 멀티레이어 구조의 표면상에 있는 물질 프래그먼트들을 제거하는 방법
SG2012059895A SG183298A1 (en) 2010-02-26 2011-02-07 Method of eliminating fragments of material present on the surface of a multilayer structure
EP11707462A EP2539922A2 (fr) 2010-02-26 2011-02-07 Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche
US13/580,860 US20130045584A1 (en) 2010-02-26 2011-02-07 Method of eliminating fragments of material present on the surface of a multilayer structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1051367 2010-02-26
FR1051367A FR2956822A1 (fr) 2010-02-26 2010-02-26 Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche

Publications (2)

Publication Number Publication Date
WO2011104461A2 WO2011104461A2 (fr) 2011-09-01
WO2011104461A3 true WO2011104461A3 (fr) 2012-05-10

Family

ID=42797115

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2011/050238 WO2011104461A2 (fr) 2010-02-26 2011-02-07 Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche

Country Status (8)

Country Link
US (1) US20130045584A1 (fr)
EP (1) EP2539922A2 (fr)
JP (1) JP2013520829A (fr)
KR (1) KR20120137475A (fr)
CN (1) CN102763191A (fr)
FR (1) FR2956822A1 (fr)
SG (1) SG183298A1 (fr)
WO (1) WO2011104461A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112014000888T5 (de) * 2013-02-19 2015-11-26 Ngk Insulators, Ltd. Verbundsubstrat, Elastische-Wellen-Vorrichtung und Verfahren zur Herstellung einer Elastische-Wellen-Vorrichtung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1434255A2 (fr) * 2002-12-25 2004-06-30 Canon Kabushiki Kaisha Appareillage pour le traitement de substrats avec une solution de traitement
EP1662560A2 (fr) * 2004-11-26 2006-05-31 Applied Materials, Inc. Évacuation du bord d'une structure transférée de silicium-sur-isolant
US20070045738A1 (en) * 2005-08-26 2007-03-01 Memc Electronic Materials, Inc. Method for the manufacture of a strained silicon-on-insulator structure
US20070249139A1 (en) * 2006-04-21 2007-10-25 Kishor Purushottam Gadkaree Semiconductor on glass insulator made using improved thinning process

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1434255A2 (fr) * 2002-12-25 2004-06-30 Canon Kabushiki Kaisha Appareillage pour le traitement de substrats avec une solution de traitement
EP1662560A2 (fr) * 2004-11-26 2006-05-31 Applied Materials, Inc. Évacuation du bord d'une structure transférée de silicium-sur-isolant
US20070045738A1 (en) * 2005-08-26 2007-03-01 Memc Electronic Materials, Inc. Method for the manufacture of a strained silicon-on-insulator structure
US20070249139A1 (en) * 2006-04-21 2007-10-25 Kishor Purushottam Gadkaree Semiconductor on glass insulator made using improved thinning process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HOLSTEYNS FRANK ET AL: "Megasonics : a cavitation driven process", DIFFUSION AND DEFECT DATA. SOLID STATE DATA. PART B, SOLID STATEPHENOMENA, VADUZ, LI, vol. 103-104, 1 April 2005 (2005-04-01), pages 159 - 162, XP009086003, ISSN: 1012-0394 *

Also Published As

Publication number Publication date
WO2011104461A2 (fr) 2011-09-01
EP2539922A2 (fr) 2013-01-02
FR2956822A1 (fr) 2011-09-02
SG183298A1 (en) 2012-09-27
US20130045584A1 (en) 2013-02-21
KR20120137475A (ko) 2012-12-21
CN102763191A (zh) 2012-10-31
JP2013520829A (ja) 2013-06-06

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